MICROCONTROLLER OVERVIEW OF MICROPROCESSOR BASED SYSTEM

Chapter-1. Overview of Microprocessor based System

Overview of Microprocessor based system

Computer Architecture Computer Organization
Computer Architecture is concerned with the way Computer Organization is concerned with the
hardware components are connected together to structure and behaviour of a computer system as
form a computer system. seen by the user.

It acts as the interface between hardware and It deals with the components of a connection in a
software. system.
Computer Architecture helps us to understand the Computer Organization tells us how exactly all
functionalities of a system. the units in the system are arranged and
interconnected.

A programmer can view architecture in terms of Whereas Organization expresses the realization of
instructions, addressing modes and registers. architecture.
While designing a computer system architecture is An organization is done on the basis of
considered first. architecture.
Computer Architecture deals with high-level Computer Organization deals with low-level
design issues. design issues.
Architecture involves Logic (Instruction sets, Organization involves Physical Components
Addressing modes, Data types, Cache (Circuit design, Adders, Signals, Peripherals)
optimization)
MICROCONTROLLER OVERVIEW OF MICROPROCESSOR BASED SYSTEM

Structural Overview of a Computer

•Computer structure is the way that each component
is arranged so that communication is possible.

• It is made up of three main components

1. Central Procession Unit (CPU)
2. Memory
3. Input/Output

• These three units are connected with

help of system interconnection i.e. buses

• Memory is used to store code (programs) and data. • It can be various kinds of like
I

Cs, magnetic memory or optical memory

• Memory is used to store code (programs) and data I/O devices are used
• It can be various kinds of like semiconductor
memory using ICs, magnetic or optical memory
• I/O devices are used to accept a input or give an
output by the CPU.
• There are various input devices like keyboard,
mouse, scanner; and various a
output devices like CRT, printer etc.
• CPU is further divided into three units
1. Arithmetic & Logic Unit (ALU)
2. Control Unit (CU)
3. CPU Registers
• ALU is used to perform arithmetic operations like
addition, subtraction and
logical operation like AND, OR etc.
• CPU Registers are used to store the data
temporarily in the CPU to save memory access time
• Control Unit is divided into three parts
1. Control Memory
2. Control Unit Registers and Decoders
3. Sequencing Logic
• The control memory stores the microinstructions
and loads it into the control unit register
• The Sequencing Logic gives these signals in a
proper sequence to execute a instruction
MICROCONTROLLER OVERVIEW OF MICROPROCESSOR BASED SYSTEM

Von Neumann & Harvard Architecture Arithmetic & Logic

Unit (ALU)
VON NEUMANN ARCHITECTURE HARVARD ARCHITECTURE
It is ancient computer architecture based on It is modern computer architecture based on
stored program computer concept. Harvard Mark I relay based model.
Same physical memory address is used for Separate physical memory address is used for
instructions and data. instructions and data.
There is common bus for data and instruction Separate buses are used for transferring data and
transfer. instruction.
Two clock cycles are required to execute single
An instruction is executed in a single cycle.
instruction.
It is cheaper in cost. It is costly than Von Neumann Architecture.
CPU can not access instructions and read/write at CPU can access instructions and read/write at the
the same time. same time.

It is used in personal computers and small It is used in micro controllers and signal
computers. processing.

2.
MICROCONTROLLER OVERVIEW OF MICROPROCESSOR BASED SYSTEM

Data Transfer Techniques 1 Programmed I/O

• Data transfer between CPU and the I/O devices may be

done in any of the three possible ways:
1. Programmed I/O
• In the programmed I/O method of interfacing, CPU has
direct control over I/O
• The processor checks the status of the and issues read or
write commands and then transfers data
• During the data transfer, CPU waits for 1/0 module to
complete operation and hence this system wastes the CPU
time.
1. CPU requests for I/O operation.
2. I/O module performs the said operation.
3. I/O module updates the status bits.
4. CPU checks these status bits periodically. Neither the
I/O module cannot inform CPU directly nor can I/O
module interrupt CPU.
5. CPU may wait for the operation to complete or may
continue the operation later

Data Transfer Techniques 2 Interrupt Driven I/O

• Interrupt Driven I/O overcomes the disadvantage of

programmed I/O i.e. the CPU waiting for I/O device.
• This disadvantage is overcome by CPU not
repeatedly checking for the device being ready or not
instead the I/O module interrupts when ready.
The sequence of operations for interrupt Driven I/O
is as below:
1. CPU issues the read command to I/O device.
2. I/O module gets data from peripheral while CPU
does other work.
3. Once the I/0 module completes the data transfer
from I/O device, it interrupts CPU.
4. On getting the interrupt, CPU requests data from
the I/O module.
5. 1/0 module transfers the data to CPU.
MICROCONTROLLER OVERVIEW OF MICROPROCESSOR BASED SYSTEM

Direct Memory Access

• DMA stands for Direct Memory Access.

• The I/O module can directly access (read or
write) the memory using this method.
• Interrupt driven and programmed I/O
require active operation of the CPU, hence
transfer rate is limited and CPU is also busy
doing the transfer operation. DMA is the
solution for these problems.
• DMA controller takes over the control of the
bus from CPU for I/O transfer.
• The internal block diagram of a DMA
controller of the I/O module for DMA method
of I/O interfacing
1. The first information is whether the data
has to be read from memory or the data has
to be written to the memory.
• It passes this information via read or writes
control lines that are between the processor
and DMA controllers control logic unit.
2. The processor also provides the starting
address of/ for the data block in the
memory, from where the data block in
memory has to be read or where the data
block has to be written in memory.
• DMA controller stores this in its address
register. It is also called the starting address
register.
3. The processor also sends the word count,
i.e. how many words are to be read or
written.
• It stores this information in the data count
or the word count register.
4. The most important is the address of I/O
device that wants to read or write data. This
information is stored in the data register.
MICROCONTROLLER OVERVIEW OF MICROPROCESSOR BASED SYSTEM

RISC vs CISC

RISC CISC
It is a Reduced Instruction Set Computer. It is a Complex Instruction Set Computer.
It emphasizes on software to optimize the It emphasizes on hardware to optimize the
instruction set. instruction set.
It is a hard wired unit of programming in the Microprogramming unit in CISC Processor.
RISC Processor.
It requires multiple register sets to store the It requires a single register set to store the
instruction. instruction.
RISC has simple decoding of instruction. CISC has complex decoding of instruction
Uses of the pipeline are simple in RISC. Uses of the pipeline are difficult in CISC.
It uses a limited number of instruction that It uses a large number of instruction that requires
requires less time to execute the instructions. more time to execute the instructions.
It used LOAD and STORE that are independent It used LOAD and STORE instruction in the
instructions in the register-to-register a memory interaction of a program.
program’s interaction.
RISC has more transistors on memory registers. CISC has transistors to store complex
instructions.
The execution time of RISC is very short. The execution time of CISC is longer.
RISC architecture can be used with high-end CISC architecture can be used with low- end
applications like telecommunication, image applications like home automation, security
processing, video processing, etc. system, etc.
It has fixed format instruction. It has variable format instruction.
The program written for RISC architecture needs Program written for CISC architecture tends to
to take more space in memory. take less space in memory.
Example of RISC: ARM, PA-RISC, Power Examples of CISC: VAX, Motorola 68000
Architecture, Alpha, AVR, ARC and the SPARC family, System/360, AMD and the Intel x86
CPUs.
MICROCONTROLLER OVERVIEW OF MICROPROCESSOR BASED SYSTEM

Stack & Stack Pointer

• A stack is one of the most commonly used

data structure.
• A stack, also called Last In First Out (LIFO)
system, is a linear list in which insertion and
deletion can take place only at one end, called
top.
• This structure operates in much the same
way as stack of trays.
• If we want to remove a tray from stack of
trays it can only be removed from the top only.
• The insertion and deletion operation in stack
terminology are known as PUSH and POP
operations.

• Following operation can be performed on stack :

1. Create stack (s) : To create an empty stack s.
2. PUSH (s, i) : To push an element i into stack s.
3. POP (s) : To access and remove the top element of the stack s.
4. Peek (s) : To access the top element of stack s without removing it from the stack s.
5. Overflow : To check whether the stack is full.
6. Underflow : To check whether the stack is empty

• Applications of Stacks are : -

• Stacks can be used for expression evaluation.
• Stacks can be used to check parenthesis matching in an expression.
• Stacks can be used for Conversion from one form of expression to another.
• Stacks can be used for Memory Management.
• Stack data structures are used in backtracking problems.

• Stack Pointer:
• It is used as a memory pointer.
• It points to a memory location in read/write memory, called the stack.
• It is always incremented / decremented by 2 during push and pop operation.
• A stack pointer is a small register that stores the address of the last program request in a stack.
• A stack is a specialized buffer which stores data from the top down. As new requests come in, they
"push down" the older ones.
MICROCONTROLLER THE MEMORY SYSTEMS

Chapter-2. THE MEMORY SYSTEMS

Memory Hierarchy
• The Computer memory hierarchy looks like a
pyramid structure which is used to describe the
differences among memory types.
• It separates the computer storage based on hierarchy.
• Level 0: CPU registers
• Level 1: Cache memory
• Level 2: Main memory or primary memory
• Level 3: Magnetic disks or secondary memory
• Level 4: Optical disks or magnetic types or tertiary
Memory
Level-0 – Registers
• The registers are present inside the CPU. As they
are present inside the CPU, they have least access
time.
• Registers are most expensive and smallest in
size generally in kilobytes.
• They are implemented by using Flip-Flops.
Level-1 – Cache
• Cache memory is used to store the segments of
a program that are frequently accessed by the
processor. It is expensive and smaller in size
generally in Megabytes and is implemented by
using static RAM.
Level-2 − Primary or Main Memory
• It directly communicates with the CPU and with
auxiliary memory devices through an I/O processor.
• Main memory is less expensive than cache
memory and larger in size generally in Gigabytes.
• This memory is implemented by using dynamic
RAM.
Level-3 − Secondary storage
• Secondary storage devices like Magnetic Disk are
present at level 3.
• They are used as backup storage.
• They are cheaper than main memory and larger in
size generally in a few TB.
Level-4 − Tertiary storage
• Tertiary storage devices like magnetic tape are present at level 4.
• They are used to store removable files and are the cheapest and largest in size (1-20 TB).
MICROCONTROLLER THE MEMORY SYSTEMS

Key Characteristics of Memory Devices

1. Location
2. Capacity
3. Unit of Transfer
4. Access Method
5. Performance
6. Physical type
7. Physical characteristics
8. Organization
1. Location:
• It deals with the location of the memory device in the computer system. There are three possible
locations:
• CPU : This is often in the form of CPU registers and small amount of cache
• Internal or main: This is the main memory like RAM or ROM. The CPU can directly access the main
memory.
• External or secondary: It comprises of secondary storage devices like hard disks, magnetic tapes. The
CPU doesn’t access these devices directly. It uses device controllers to access secondary storage devices.
2. Capacity:
• The capacity of any memory device is expressed in terms of:
i)word size
ii)Number of words
• Word size: Words are expressed in bytes (8 bits). A word can however mean any number of bytes.
Commonly used word sizes are 1 byte (8 bits), 2bytes (16 bits) and 4 bytes (32 bits).
• Number of words: This specifies the number of words available in the particular memory device. For
example, if a memory device is given as 4K x [Link] means the device has a word size of 16 bits and a
total of 4096(4K) words in memory.
3. Unit of Transfer:
• It is the maximum number of bits that can be read or written into the memory at a time.
• In case of main memory, it is mostly equal to word size.
• In case of external memory, unit of transfer is not limited to the word size; it is often larger and is
referred to as blocks.

4. Access Methods
• It is a fundamental characteristic of memory devices. It is the sequence or order in which memory can
be accessed. There are three types of access methods:
• Random Access: If storage locations in a particular memory device can be accessed in any order and
access time is independent of the memory location being accessed. Such memory devices are said to
have a random access mechanism. RAM (Random Access Memory) IC’s use this access method.
• Serial Access: If memory locations can be accessed only in a certain predetermined sequence, this access
method is called serial access. Magnetic Tapes, CD-ROMs employ serial access methods.
• Semi random Access: Memory devices such as Magnetic Hard disks use this access method. Here each
track has a read/write head thus each track can be accessed randomly but access within each track is
restricted to a serial access.
MICROCONTROLLER THE MEMORY SYSTEMS

5. Performance:
• The performance of the memory system is determined using three parameters
Access Time: In random access memories, it is the time taken by memory to complete the read/write
operation from the instant that an address is sent to the memory. For non-random access memories, it is
the time taken to position the read write head at the desired location. Access time is widely used to
measure performance of memory devices.
Memory cycle time: It is defined only for Random Access Memories and is the sum of the access time
and the additional time required before the second access can commence.
Transfer rate: It is defined as the rate at which data can be transferred into or out of a memory unit.

6. Physical type:
Memory devices can be either semiconductor memory (like RAM) or magnetic surface memory (like Hard disks).

[Link] Characteristics:
Volatile/Non- Volatile: If a memory devices continues hold data even if power is turned off. The memory device
is non-volatile else it is volatile.

8. Organization:
Erasable/Non-erasable: The memories in which data once programmed cannot be erased are called Non-erasable
memories. Memory devices in which data in the memory can be erased is called erasable memory.
E.g. RAM(erasable), ROM(non-erasable).

Memory & its types

• Computer memory is any physical
device, used to store data, information or
instruction temporarily or permanently.
• It is the collection of storage units that
stores binary information in the form of
bits.
• The memory block is split into a small
number of components, called cells.
• Each cell has a unique address to store
the data in memory, ranging from zero to
memory size minus one. • It is classified
into
1. RAM – Random Access Memory
2. ROM – Read Only Memory
MICROCONTROLLER THE MEMORY SYSTEMS

RAM
• It is also called read-write memory or the main memory or the primary memory.
• The programs and data that the CPU requires during the execution of a program are stored in this
memory.
• It is a volatile memory as the data is lost when the power is turned off.
• RAM is further classified into two types
1. SRAM (Static Random Access Memory)
2. DRAM (Dynamic Random Access Memory).

ROM
• Stores crucial information essential to operate the system, like the program essential to boot the
computer.
• It is not volatile.
• Always retains its data.
• Used in embedded systems or where the programming needs no change.
• Used in calculators and peripheral devices.
• ROM is further classified into 4 types- ROM, PROM, EPROM, and EEPROM.
• Types of Read Only Memory (ROM) –
1. PROM (Programmable read-only memory) – It can be programmed by user. Once programmed, the
data and instructions in it cannot be changed.
2. EPROM (Erasable Programmable read only memory) – It can be reprogrammed. To erase data from
it, expose it to ultra violet light. To reprogram it, erase all the previous data.
3. EEPROM (Electrically erasable programmable read only memory) – The data can be erased by
applying electric field, no need of ultra violet light. We can erase only portions of the chip.

RAM ROM
It is a Random-Access Memory. It is a Read Only Memory.

Read and write operations can be performed. Only Read operation can be performed.

Data can be lost in volatile memory when the Data cannot be lost in non-volatile memory when
power supply is turned off. the power supply is turned off.

It is a faster and expensive memory. It is a slower and less expensive memory.

Storage data requires to be refreshed in RAM. Storage data does not need to be refreshed in ROM.

The size of the chip is bigger than the ROM chip to The size of the chip is smaller than the RAM chip
store the data. to store the same amount of data.

Types of RAM: DRAM and SRAM Types of ROM: MROM, PROM, EPROM,
EEPROM
MICROCONTROLLER THE MEMORY SYSTEMS

SRAM DRAM
It is a Static Random-Access Memory. It is a Dynamic Random Access Memory.

The access time of SRAM is slow. The access time of DRAM is high.

It uses flip-flops to store each bit of information. It uses a capacitor to store each bit of information.

It does not require periodic refreshing to preserve It requires periodically refreshing to preserve the
the information. information.

It uses in cache memory. It is used in the main memory.

The cost of SRAM is expensive. The cost of DRAM is less expensive.

It has a complex structure. Its structure is simple.

It requires low power consumption. It requires more power consumption.

MICROCONTROLLER THE MEMORY SYSTEMS

Virtual Memory
• In the most computer system, the
physical main memory is not as large as
address space of the processor.
• When we try to run a program, if it do
not completely fit into the main memory
the parts of its currently being executed
are stored in main memory and remaining
portion is stored in secondary storage
device such as HDD.
• When a new part of program is to be
brought into main memory for execution
and if the memory is full, it must replace
another part which is already is in main
memory.
• As this secondary memory is not actually
part of system memory, so for CPU,
secondary memory is Virtual Memory.
• Techniques that automatically more
program and data blocks into physical
memory when they are required for
execution are called virtual memory
• Virtual Memory is used to logically
extend the size of main memory.
• When Virtual Memory is used, the
address field is virtual address.
• A special hardware unit knows as MMU translates Virtual Address into Physical Address.
MICROCONTROLLER THE MEMORY SYSTEMS

Cache Memory
• Cache Memory is a special very highspeed memory.
• It is used to speed up and synchronize with high-speed CPU.
• Cache memory is costlier than main memory or disk memory but more economical than CPU registers.
• Cache memory is an extremely fast memory type that acts as a buffer between RAM and the CPU.
• It holds frequently requested data and instructions so that they are immediately available to the CPU
when needed.

Level 1:
• It is the first level of cache memory, which
is called Level 1 cache or L1 cache.
• In this type of cache memory, a small
amount of memory is present inside the
CPU itself. If a CPU has four cores (quad
core cpu), then each core will have its own
level 1 cache.
• As this memory is present in the CPU, it
can work at the same speed as of the CPU.
• The size of this memory ranges from 2KB
to 64 KB.
• The L1 cache further has two types of
caches: Instruction cache, which stores
instructions required by the CPU, and the
data cache that stores the data required by
the CPU.

Level 2:
• This cache is known as Level 2 cache or
L2 cache.
• This level 2 cache may be inside the CPU
or outside the CPU.
• All the cores of a CPU can have their own
separate level 2 cache, or they can share one L2 cache among themselves.
• In case it is outside the CPU, it is connected with the CPU with a very high-speed bus.
• The memory size of this cache is in the range of 256 KB to the 512 KB.
• In terms of speed, they are slower than the L1 cache.

Level 3:
• It is known as Level 3 cache or L3 cache.
• This cache is not present in all the processors; some high-end processors may have this type of cache.
• This cache is used to enhance the performance of Level 1 and Level 2 cache.
• It is located outside the CPU and is shared by all the cores of a CPU.
• Its memory size ranges from 1 MB to 8 MB.
• Although it is slower than L1 and L2 cache, it is faster than Random Access Memory (RAM).
MICROCONTROLLER THE MEMORY SYSTEMS

There are a few basic design elements that serve to classify and differentiate cache architectures.
They are listed down:
1. Cache Addresses
2. Cache Size
3. Mapping Function
4. Replacement Algorithm
5. Write Policy
6. Line Size
7. Number of caches

1. Cache Addresses
• When virtual addresses are used, the cache can be
placed between the processor and the MMU or
between the MMU and main memory.
• A logical cache, also known as a virtual cache,
stores data using virtual addresses.
• The processor accesses the cache directly, without
going through the MMU.

2. Cache Size:
• The size of the cache should be small enough so that
the overall average cost per bit is close to that of main
memory alone and large enough so that the overall
average access time is close to that of the cache alone.

3. Mapping Function
• As there are fewer cache lines than main memory
blocks, an algorithm is needed for mapping main
memory blocks into cache lines.
• Further, a means is needed for determining which
main memory block currently occupies a cache line. •
The choice of the mapping function dictates how the
cache is organized. Three techniques can be used:
direct, associative, and set associative.
• DIRECT MAPPING: The simplest technique,
known as direct mapping, maps each block of main
memory into only one possible cache line.
• The direct mapping technique is simple and
inexpensive to implement.
• ASSOCIATIVE MAPPING: Associative mapping
overcomes the disadvantage of direct mapping by
permitting each main memory block to be loaded into
any line of the cach
• SET-ASSOCIATIVE MAPPING: Set-associative
mapping is a compromise that exhibits the strengths of
both the direct and associative approaches. With set-
associative mapping, block can be mapped into any of the lines of set j.
MICROCONTROLLER THE MEMORY SYSTEMS

4. Replacement Algorithms
• Once the cache has been filled, when a new block is brought into the cache, one of the existing blocks
must be replaced.
• For direct mapping, there is only one possible line for any particular block, and no choice is possible.
• For the associative and set associative techniques, a replacement algorithm is needed.
• To achieve high speed, such an algorithm must be implemented in hardware.
• Least Recently Used (LRU), Least Frequently Used(LFU), First In First Out (FIFO) are some
replacement algorithms.

5. Write Policy
• When a block that is resident in the cache is to be replaced, there are two cases to consider.
• If the old block in the cache has not been altered, then it may be overwritten with a new block without
first writing out the old block.
• If at least one write operation has been performed on a word in that line of the cache, then main memory
must be updated by writing the line of cache out to the block of memory before bringing in the new block.

6. Line Size
• When a block of data is retrieved and placed in the cache, not only the desired word but also some
number of adjacent words is retrieved.
• Basically, as the block size increases, more useful data are brought into the cache.
• The hit ratio will begin to decrease, however, as the block becomes even bigger and the probability of
using the newly fetched information becomes less than the probability of reusing the information that has
to be replaced.

[Link] of Caches
• When caches were originally introduced, the typical system had a single cache.
• More recently, the use of multiple caches has become an important aspect. There are two design issues
surrounding number of caches.
• MULTILEVEL CACHES: Most contemporary designs include both on-chip and external caches.
• The simplest such organization is known as a two-level cache, with the internal cache designated as
level 1 (L1) and the external cache designated as level 2 (L2).
• There can also be 3 or more levels of cache. This helps in reducing main memory accesses.
• UNIFIED VERSUS SPLIT CACHES: Earlier on-chip cache designs consisted of a single cache used
to store references to both data and instructions.
• This is the unified approach. More recently, it has become common to split the cache into two: one
dedicated to instructions and one dedicated to data. These two caches both exist at the same level.
• This is the split cache. Using a unified cache or a split cache is another design issue.
MICROCONTROLLER THE MEMORY SYSTEMS

Interleaved Memory
• The memory system in which successive addresses are evenly spread across memory bank to compensate
for the relatively slow speed of DRAM.
• The contagious memory reads and writes are using each bank in term, resulting in higher memory
throughputs due to reduced waiting for memory banks to become ready for desired operations.
Types of Interleaved Memory
1. High order interleaving:
• In high order memory interleaving,
the most significant bits of the
memory address decides memory
banks where a particular location
resides.
• But, in low order interleaving the
least significant bits of the memory
address decides the memory banks.
• The least significant bits are sent
as addresses to each chip.
• One problem is that consecutive
addresses tend to be in the same chip.
• The maximum rate of data transfer is limited by the memory cycle time. It is also known as Memory
Banking.
• The least significant bits are sent as addresses to each chip.
• One problem is that consecutive addresses tend to be in the same chip.
• The maximum rate of data transfer is limited by the memory cycle time.
• It is also known as Memory Banking.

2. Low order interleaving:

The least significant bits select the
memory bank (module) in low-order
interleaving. In this, consecutive
memory addresses are in different
memory modules, allowing memory
access faster than the cycle time.
MICROCONTROLLER THE MEMORY SYSTEMS

Associative Memory
• This memory is also known as content
addressable memory.
• Its hardware organization consist of
argument register to hold CPU's request &
a key register to hold predefined "mask"
which is logically 'AND'ed with the CPU's
request in argument register.
• The result of CPU's request will be
masked and remaining unmasked bits are
then parallel y searched against each word
in the associative memory array as shown
below.
• During this parallel search as soon as the
match is found the corresponding match
register bit will be set and the data word
from this matched location is placed on the
OUTPUT for CPU.

parameters paging segmentation

Individual Memory In Paging, we break a process In the case of Segmentation, we
address space into blocks known break a process address space
as pages. into blocks known as sections.
Memory Size The pages are blocks of fixed The sections are blocks of
size. varying sizes.
Accountability The OS divides the available The compiler mainly calculates
memory into individual pages. the size of individual segments,
their actual address as well as
virtual address.
Speed This technique is comparatively This technique is comparatively
much faster in accessing much slower in accessing
memory. memory than Paging.
Size The available memory The user determines the
determines the individual page individual segment sizes.
sizes.
Fragmentation The Paging technique may The Segmentation technique
underutilize some of the pages- may not use some of the memory
thus leading to internal blocks at all. Thus, it may lead to
fragmentation. external fragmentation.
Logical Address A logical address divides into A logical address divides into
page offset and page number in section offset and section
the case of Paging. number in the case of
Segmentation.
Data Storage In the case of Paging, the page In the case of Segmentation, the
table leads to the storage of the segmentation table leads to the
page data. storage of the segmentation data.
MICROCONTROLLER 8051 MICROCONTROLLER

Chapter-3. 8051 MICROCONTROLLER

8051 MICROCONTROLLER
parameter microprocessor microcontroller
Definition Microprocessors can be Microcontrollers can be
understood as the heart of a understood as the heart of an
computer system. embedded system.
What is it? A microprocessor is a processor A microcontroller is a
where the memory and I/O controlling device wherein the
component are connected memory and I/O output
externally. component are present
internally.
Circuit complexity The circuit is complex due to Microcontrollers are present on
external connection. chip memory. The circuit is less
complex.
Memory and I/O components The memory and I/O The memory and I/O
components are to be connected components are available.
externally.
Compact system compatibility Microprocessors can't be used in Microcontrollers can be used
compact system. with a compact system.
Efficiency Microprocessors are not Microcontrollers are efficient.
efficient.
Zero status flag Microprocessors have a zero Microcontroller doesn't have a
status flag. zero status flag.
Number of registers Microprocessors have less Microcontrollers have more
number of registers. number of registers.
Applications Microprocessors are generally Microcontrollers are generally
used in personal computers. used in washing machines, and
air conditioners.
MICROCONTROLLER 8051 MICROCONTROLLER

Architecture of 8051 Microcontroller

Feature of 8051 Microcontroller

• It has 8 bit Data bus.
• It has 8 bit Stack Pointer.
• It has 16 bit Program Counter.
• It has 16 bit address bus which can access almost 65,536 memory locations.
• Data memory or RAM of 128 bytes. (On-Chip). The data memory can be expanded up to 64kb.
• Program Memory or ROM of 4 KB. (On Chip).
• It has 4 parallel I/O port: port0, port1, port2, port3. Each port is 8-bit bidirectional I/O port. Each port
is bit/byte addressable.
• It has 4 register banks: bank 0, bank 1, bank 2, and bank 3. Each register bank consists of 8 register (R0
to R7).
• Serial Port or UART (This serial communication port makes chip to use simply as a serial
communication interface).
• It features Power Saving Mode which saves power.
• Two Timers/Counters each of 16 bit.
• Internal and External Interrupt Sources.
• It has 11 special function register.
• It has 111 instructions, 64 instructions are single cycle.
MICROCONTROLLER 8051 MICROCONTROLLER

Blocks in 8051 Microcontroller

1. Accumulator (ACC or Register A)
• It is used as a general register to accumulate the results of a large number of instructions.
• It can hold an 8-bit (1-byte) value and is the most versatile register the 8051 has due to the shear number
of instructions that make use of the accumulator.
• More than half of the 8051s 255 instructions manipulate or use the accumulator in some way.
• For example, to add the number 10 and 20, the resulting 30 will be stored in the Accumulator.
• MOV A,R3 ;Move the value of R3 into the accumulator
• ADD A,R4 ;Add the value of R4

2. Register B
• The "B" register is very similar to the Accumulator in the sense that it may hold an 8-bit (1-byte) value.
• The "B" register is used only by two 8051 instructions: MUL AB and DIV AB.
• To quickly and easily multiply or divide A by another number, it may store the other number in "B" and
make use of these two instructions.

3. ALU : Arithmetic and Logical Unit

• It performs arithmetic like addition, subtraction, multiplication and Logical Operations like NAND, NOR etc.
Since 8051 is an 8 bit microcontroller, it takes input from two 8 bit registers namely A and B and processes them.

4. Program Status Word (PSW or

Flag Register)
• The PSW register is an 8-bit register.
• It is also referred to as the flag register.
• Although the PSW register is 8 bits wide,
only 6 bits of it are used by the 8051.
• The two unused bits are userdefinable
flags.
• Four of the flags are called conditional
flags, meaning that they indicate some
conditions that result after an instruction is
executed.
• These four are CY (carry), AC (auxiliary
carry), P (parity), and OV (overflow).

a. CY : Carry flag
• This flag is set whenever there is a carry out from the D7 bit.
• This flag bit is affected after an 8-bit addition or subtraction.
• It can also be set to 1 or 0 directly by an instruction such as “SETB C” and “CLR C” where “SETB C”
stands for “set bit carry” and “CLR C” for “clear carry”.

b. AC : Auxiliary Carry flag

• If there is a carry from D3 to D4 during an ADD or SUB operation, this bit is set; otherwise, it is cleared.
• This flag is used by instructions that perform BCD (binary coded decimal) arithmetic.
MICROCONTROLLER 8051 MICROCONTROLLER

c. P : Parity flag
• The parity flag reflects the number of 1 s in the A (accumulator) register only.
• If the A register contains an odd number of Is, then P = 1.
• Therefore, P = 0 if A has an even number of Is.

d. OV : Overflow flag
• This flag is set whenever the result of a signed number operation is too large, causing the high-order bit
to overflow into the sign bit.
• In general, the carry flag is used to detect errors in unsigned arithmetic operations.
• The overflow flag is only used to detect errors in signed arithmetic operations.

5. Clock and Oscillator

• Clock pulses are required any digital systems.
• Microprocessor embedded system digital system.
• Some microcontrollers have on chip oscillator
circuit and require only a crystal to be connected
externally, while some require external oscillator
circuit.
• 8051 has an on chip oscillator but needs and
external clock to run it.
• The oscillator circuit generates the clock pulses so
that all the internal and external operations are
synchronized.
• The pins XTAL1 & XTAL2 are used to connect
crystal.
• The Crystal is always connected along with the
capacitors as shown in figure.
• 8051 microcontroller are available in market with
varying range of operation from 1MHz to 16 MHz
• Generally 11.0592 MHz crystal oscillators are
used so that the 8051 microcontroller systems are compatible with the serial port.
• One machine cycle comprises of 12 oscillator periods.
• Hence to find the time for one machine cycle we need to consider 1/12th of Crystal frequency.
MICROCONTROLLER 8051 MICROCONTROLLER

Stack & Stack Pointer Register

• It is a section of RAM used by the CPU to
store information temporarily information
could be data or an address.
• The register used to access the stack is
called stack pointer register.
• Stack is used to store data temporary during
any program execution.
• The 8 bit stack pointer is used to hold an
internal RAM address which is called the top
of stack.
• Generally 8051 used bank1 of internal
RAM as the stack so the default stack pointer
is 07H.
• The stack pointer in the 8051 only 8 bit
wide which means that it can take value of 00
to FFH.
• When the 8051 is powered up the sp register
contain value 07H.
• RAM location 08H is the first location
begin used for the stack by the 8051.
• When data is retrieved from the stack the byte is read from the stack and then sp register increment.
• The stack is used during PUSH, POP, CALL, RET instruction.
• Stack pointer work on the principal of last ID first output (LIFO).
MICROCONTROLLER 8051 MICROCONTROLLER

DPTR : Data Pointer

• The DPTR register is made up of two 8-bit registers, named DPH and DPL, that are used to furnish
memory addresses for internal and external code access and external data access.
• The DPTR is under the control of program instructions and can be specified by its 16-bit name, DPTR,
or by each individual byte name, DPH (High Byte) and DPL (Low Byte)
• DPTR does not have a single internal address; DPH and DPL are each assigned an address.

PC : Program Counter
• The Program Counter is one of the most important registers in the CPU.
• A program is a series of instructions stored in the memory.
• These instructions tell the CPU exactly how to get the desired result.
• It is important that these instructions must be executed in a proper order to get the correct result.
• This sequence of instruction execution is monitored by the program counter.
• It keeps track of which instruction is being executed and what the next instruction will be.
MICROCONTROLLER 8051 MICROCONTROLLER

Internal Memory (RAM) Organization

• 8051 has 128 bytes of internal RAM.

• It is divided into three sections.
1. Register banks
2. Bit/Byte addressable area
3. The general purpose memory area

Register Banks:
• It has four register banks i.e Bank 0 to Bank 3
• Each bank has 8 registers.
• Therefore there are 32 registers in the register bank area and each register is of 8 bit. Each bank has
register RO to R7.
• RSO and RS1 bits of Program status word register are used to select register bank.
• The address of the register bank area starts at 00h and ends at 1Fh.

Bit Addressable Area:

• It can store or remove 1-bit of data as well as 1-byte data.
• This area has total of 128 bit addresses starting from00h to 07Fh.
• They have byte address from 20H to 2FH.
• Separate instructions are used to read and write a single bit.

General Purpose Memory Area:

• It is used to store any general purpose data. • The addresses of the general purpose memory area is from
30H to 7FH
MICROCONTROLLER 8051 MICROCONTROLLER

Pin Configuration of 8051

• 8051 microcontroller is a 40 pin Dual Inline Package
(DIP).
• These 40 pins serve different functions like read,
write, I/O operations, interrupts etc.
• 8051 has four I/O ports wherein each port has 8 pins
which can be configured as input or output depending
upon the logic state of the pins.
• Therefore, 32 out of these 40 pins are dedicated to
I/O ports.
• The rest of the pins are dedicated to VCC, GND,
XTAL1, XTAL2, RST, ALE, EA’ and PSEN

Pin 1 to Pin 8 (Port 1) –

• Pin 1 to Pin 8 are assigned to Port 1 for simple I/O
operations.
• They can be configured as input or output pins
depending on the logic control i.e. if logic zero (0) is
applied to the I/O port it will act as an output pin and
if logic one (1) is applied the pin will act as an input
pin.
• These pins are also referred to as P1.0 to P1.7 (where
P1 indicates that it is a pin in port 1 and the number
after ‘.’ tells the pin number i.e. 0 indicates first pin of the port.
• So, P1.0 means first pin of port 1, P1.1 means second pin of the port 1 and so on). These pins are
bidirectional pins.

Pin 9 (RST) –Reset pin.

• It is an active-high, input pin.
• Therefore if the RST pin is high for a minimum of 2 machine cycles, the microcontroller will reset i.e.
it will close and terminate all activities.
• It is often referred as “power-on-reset” pin because it is used to reset the microcontroller to it’s initial
values when power is on (high).

Pin 10 to Pin 17 (Port 3) –

• Pin 10 to pin 17 are port 3 pins which are also referred to as P3.0 to P3.7.
• These pins are similar to port 1 and can be used as universal input or output pins. These pins are
bidirectional pins.

P3.0 (RXD) :
• 10th pin is RXD (serial data receive pin) which is for serial input.
• Through this input signal microcontroller receives data for serial communication.

P3.1 (TXD) :
• 11th pin is TXD (serial data transmit pin) which is serial output pin.
• Through this output signal microcontroller transmits data for serial communication.
MICROCONTROLLER 8051 MICROCONTROLLER

P3.2 and P3.3 (INT0′, INT1′ ) :

• 12th and 13th pins are for External Hardware Interrupt 0 and Interrupt 1 respectively.
• When this interrupt is activated(i.e. when it is low), 8051 gets interrupted in whatever it is doing and
jumps to the vector value of the interrupt (0003H for INT0 and 0013H for INT1) and starts performing
Interrupt Service Routine (ISR) from that vector location.

P3.4 and P3.5 (T0 and T1) :

• 14th and 15th pin are for Timer 0 and Timer 1 external input. They can be connected with 16 bit
timer/counter.

P3.6 (WR’) :
• 16th pin is for external memory write i.e. writing data to the external memory.

P3.7 (RD’) :
• 17th pin is for external memory read i.e. reading data from external memory.

Pin 18 and Pin 19 (XTAL2 And XTAL1) –

• These pins are connected to an external oscillator which is generally a quartz crystal oscillator.
• They are used to provide an external clock frequency of 4MHz to 30MHz.

Pin 20 (GND) –
• This pin is connected to the ground. It has to be provided with 0V power supply.
• Hence it is connected to the negative terminal of the power supply.

Pin 21 to Pin 28 (Port 2) –

• Pin 21 to pin 28 are port 2 pins also referred to as P2.0 to P2.7.
• When additional external memory is interfaced with the 8051 microcontroller, pins of port 2 act as
higher-order address bytes.
• These pins are bidirectional.

Pin 29 (PSEN) – Program Store Enable.

• It is output, active-low pin. This is used to read external memory.
• In 8031 based system where external ROM holds the program code, this pin is connected to the OE pin
of the ROM.

Pin 30 (ALE/ PROG) –ALE stands for Address Latch Enable

• It is input, active-high pin.
• This pin is used to distinguish between memory chips when multiple memory chips are used.
• It is also used to de-multiplex the multiplexed address and data signals available at port 0.
• During flash programming i.e. Programming of EPROM, this pin acts as program pulse input (PROG).

Pin 31 (EA/ VPP) –EA stands for External Access input.

• It is used to enable/disable external memory interfacing.
• In 8051, EA is connected to Vcc as it comes with on-chip ROM to store programs.
• For other family members such as 8031 and 8032 in which there is no on-chip ROM, the EA pin is
connected to the GND.
MICROCONTROLLER 8051 MICROCONTROLLER

Pin 32 to Pin 39 (Port 0) –

• Pin 32 to pin 39 are port 0 pins also referred to as P0.0 to P0.7.
• They are bidirectional input/output pins.
• They don’t have any internal pull-ups.
• Hence, 10 K? pull-up registers are used as external pull-ups.
• Port 0 is also designated as AD0-AD7 because 8051 multiplexes address and data through port 0 to save
pins.

Pin 40 (VCC) –
• This pin provides power supply voltage i.e. +5 Volts to the circuit.

Port 0 Structure of 8051

• Port 0 can be used as a normal
bidirectional I/O port or it can be used
for address/ data interfacing for
accessing external memory when
control ‘1’ the port is used for
address/data interfacing, when the
control is ‘0’ the port can be used as a
bidirectional I/O port 0.

Port 0 as an Input Port :

• Assume that control is ‘0’ when the
port 0 is used as an input port ‘1’ is
written to the latch, in this situation
both the output FET are off, hence the
output pin have floats hence whatever,
data written on pin is directly read by
read pin

Port 0 as an Output Port :

• To write ‘1’ on pin of port o a ‘1’
written to the latch which turns off the
lower FET while due to ‘0’ control
signal upper FET also turns off, here
we want logic ‘1’ on pin but we getting
floating value so to convert that
floating value so to convert that
floating value into logic ‘1’ to connect
the pull up resistor parallel to upper FET
MICROCONTROLLER 8051 MICROCONTROLLER

Port 1 Structure of 8051

• Port 1 dedicated only for I/O interfacing
when used as output port not needed to
connect additional pull up register like
port 0.
• It have provided internally pull up
resistor the pin is pulles up or down
through internal pull-up when we want to
initialize as an output port.
• To use port-1 as input port 1 has to be
written to the latch., Input mode when ‘1’
is written to the pin by the external device
then it read fine.
• But when ‘0’ is written to the pin by the
external device then the external source.
• Must sink current due to internal pull-up
if the external device is not able to sink the
current the pin voltage may rise leading to
a possible.
• The internal FET pull up is used to help
the port-1 to speed up when it is used as an
output port the internal FET pull up has
another FET that is in parallel to lower
FET.
• FET is turned on for two clock periods when the transition on the pin is low to high arrangement
provides low impedance path to the positive supply voltage

Port 2 Structure of 8051

• Port-2 we use for higher external address
byte or a normal input/output port.
• The I/O operation is similar to Port 1
• Port-2 latch remains stable when Port-2
pin are used for external memory access.
• Here again due to internal pull-up there is
limited current driving capability.
MICROCONTROLLER 8051 MICROCONTROLLER

Port 3 Structure of 8051

• Port 3 is multifunction part it can be used as a simple input/output port.
Port 3 as simple input port :
• When port 3 is used as an input port ‘1’ must be written to the corresponding port 3 latch bit this cause
the FET to turn off pin & input to pin buffer are pulled to logic high by internal pull up load.
Port 3 as simple output port :
• when port 3 is used as an output the latch pins that are programmed to o cause the lower FET to turn on
the internal pull up turn off & input to the circuit is logic 0 if a ‘1’ is written onto the latch pin then it drive
the input of external circuit high through the pull up, lower FET turns off.

TMOD : Timer Mode Control

BIT TMOD Bit Function

0 MO--Timer/counter operating mode select bit 0. Set/cleared by program to select mode.
1 M1 -- Timer/counter operating mode select bit 1. Set/cleared by program to select mode.
2 C/T-- Set to 1 by program to make timer 0 act as a counter by counting pulses from external
input pin 3.4. Cleared to zero by program to make timer act as a timer by counting internal
frequency.
3 Gate -- OR gate enable bit which controls RUN/STOP of timer 0. Set to 1 by program to enable
timer to run if bit TRO in TCON is set and signal on external interrupt is high. Cleared to 0 by
program to enable time to run if bit TRO is set.
 UNIT – 3

8051 MICROCONTROLLER
What is a Microcontroller?
A Microcontroller is a programmable digital processor with necessary peripherals. Both microcontrollers
and microprocessors are complex sequential digital circuits meant to carry out job according to the program
/ instructions. Sometimes analog input/output interface makes a part of microcontroller circuit of mixed
mode (both analog and digital nature).
A microcontroller can be compared to a Swiss knife with multiple functions incorporated in the same IC.

Fig. 5.1 A Microcontroller compared with a Swiss knife

Microcontrollers Vs Microprocessors

1. A microprocessor requires an external memory for program/data storage. Instruction execution

requires movement of data from the external memory to the microprocessor or vice versa. Usually,
microprocessors have good computing power and they have higher clock speed to facilitate faster
computation.
2. A microcontroller has required on-chip memory with associated peripherals. A microcontroller can
be thought of a microprocessor with inbuilt peripherals.
3. A microcontroller does not require much additional interfacing ICs for operation and it functions as a
standalone system. The operation of a microcontroller is multipurpose, just like a Swiss knife.
4. Microcontrollers are also called embedded controllers. A microcontroller clock speed is limited only
 to a few tens of MHz Microcontrollers are numerous and many of them are application specific.

Development/Classification of microcontrollers (Invisible)

Microcontrollers have gone through a silent evolution (invisible). The evolution can be rightly termed as silent
as the impact or application of a microcontroller is not well known to a common user, although
microcontroller technology has undergone significant change since early 1970's. Development of some
popular microcontrollers is given as follows.

Intel 4004 4 bit (2300 PMOS trans, 108 kHz) 1971

Intel 8048 8 bit 1976

Intel 8031 8 bit (ROM-less) .

Intel 8051 8 bit (Mask ROM) 1980

Microchip PIC16C64 8 bit 1985

Motorola 68HC11 8 bit (on chip ADC) .

Intel 80C196 16 bit 1982

Atmel AT89C51 8 bit (Flash memory) .

Microchip PIC 16F877 8 bit (Flash memory + ADC) .

Development of microprocessors (Visible)

Microprocessors have undergone significant evolution over the past four decades. This development is
clearly perceptible to a common user, especially, in terms of phenomenal growth in capabilities of personal
computers. Development of some of the microprocessors can be given as follows.

Intel 4004 4 bit (2300 PMOS transistors) 1971

Intel 8080 8 bit (NMOS)

1974
8085 8 bit

Intel 8088 16 bit

1978
8086 16 bit

Intel 80186 16 bit

1982
80286 16 bit
 Intel 80386 32 bit (275000 transistors) 1985

Intel 80486 SX 32 bit

1989
DX 32 bit (built in floating point unit)

Intel 80586 I
1993
MMX
1997
Celeron II 64 bit
1999
III
2000
IV

Z-80 (Zilog) 8 bit 1976

Motorola Power PC 601 32-bit 1993

602
603 1995

Some of the microcontrollers of 8051 family are given as follows:

DEVICE ON-CHIP ON-CHIP 16-BIT NO. OF FULL
DATA PROGRAM TIMER/COUNTER VECTORED DUPLEX I/O
MEMORY MEMORY INTERUPTS
(bytes) (bytes)

8031 128 None 2 5 1

8032 256 none 2 6 1
8051 128 4k ROM 2 5 1

8052 256 8k ROM 3 6 1

8751 128 4k EPROM 2 5 1

8752 256 8k EPROM 3 6 1

AT89C51 128 4k Flash Memory 2 5 1

AT89C52 256 8k Flash memory 3 6 1

Various features of 8051 microcontroller are given as follows:
• 8-bit CPU
• 16-bit Program Counter
• 8-bit Processor Status Word (PSW)
• 8-bit Stack Pointer
• Internal RAM of 128bytes
• Special Function Registers (SFRs) of 128 bytes
• 32 I/O pins arranged as four 8-bit ports (P0 - P3)
• Two 16-bit timer/counters : T0 and T1
• Two external and three internal vectored interrupts
• One full duplex serial I/O

ARCHITECTURE OF 8051 MICROCONTROLLER:

It is 8-bit microcontroller, means MC 8051 can Read, Write and Process 8 bit data. This is
mostly used microcontroller in the robotics, home appliances like mp3 player, washing machines,
electronic iron and industries. Mostly used blocks in the architecture of 8051 are as follows:
1. Oscillator and clock generator:
All operations in a microcontroller are synchronized by the help of an oscillator clock. The
oscillator clock generates the clock pulses by which all internal operations are synchronized. A
resonant network connected through pins XTAL1 and XTAL2 forms up an oscillator. For this
purpose a quartz crystal and capacitors are employed. The crystal run at specified maximum and
minimum frequencies typically at 1 MHz to 16 MHz.
2. ALU:
It is 8 bit unit. It performs arithmetic operation as addition, subtraction, multiplication,
division, increment and decrement. It performs logical operations like AND, OR and EX-OR. It
manipulates 8 bit and 16 bit data. It calculates address of jump locations in relative branch
instruction. It performs compare, rotate and compliment operations. It consists of Boolean
processor which performs bit, set, test, clear and compliment. 8051 micro controller contains 34
general purpose registers or working registers.2 of them are called math registers A & B and 32
are bank of registers.
a. Accumulator(A-reg):
It is 8 bit register. Its address is E0H and it is bit and byte accessible. Result of arithmetic
& logic operations performed by ALU is accumulated by this register. Therefore it is called
accumulator register. It is used to store 8 bit data and to hold one of operand of ALU units during
arithmetical and logical operations. Most of the instructions are carried out on accumulator data.
It is most versatile of 2 CPU registers.
b. B-register:
It is special 8 bit math register. It is bit and byte accessible. It is used in conjunction with
A register as I/P operand for ALU. It is used as general purpose register to store 8 bit data.
c. PSW:
It is 8 bit register. Its address is D0H and It is bit and byte accessible. It has 4 conditional
flags or math flags which sets or resets according to condition of result. It has 3 control flags, by
setting or resetting bit required operation or function can be achieved. The format of flag register
is as shown below:
d. FLAG:
1. Carry Flag(CY): During addition and subtraction any carry or borrow is generated then
carry flag is set otherwise carry flag resets. It is used in arithmetic, logical, jump, rotate
and Boolean operations.
2. Auxiliary carry flag(AC): If during addition and subtraction any carry or borrow is
generated from lower 4 bit to higher 4 bit then AC sets else it resets. It is used in BCD
arithmetic operations.
3. Overflow flag(OV): If in signed arithmetic operations result exceeds more than 7 bit
than OV flag sets else [Link] is used in signed arithmetic operations only.
4. Parity flag(P): If in result, even no. Of ones "1" are present than it is called even parity
and parity flag sets. In result odd no. Of ones "1"are present than it is called odd parity
and parity flag resets.

ii. CONTROL FLAGS:

1. FO: It is user defined flag. The user defines the function of this flag. The user can set
,test n clear this flag through software.
2. RS1 and RS0: These flags are used to select bank of register by resetting those flags
which are as shown in table :
 3. Program counter (PC): The Program Counter (PC) is a 2-byte address which tells the
8051 where the next instruction to execute is found in memory. It is used to hold 16 bit
address of internal RAM, external RAM or external ROM locations. When the 8051 is
initialized PC always starts at 0000h and is incremented each time an instruction is
executed. It is important to note that PC isnt always incremented by one and never
decremented.
4. Data pointer register (DTPR): It is a 16 bit register used to hold address of external or
internal RAM where data is stored or result is to be stored. It is used to store 16 bit data.
It is divided into2- 8bit registers, DPH-data pointer higher order (83H) and DPL-data
pointer lower order (82H). Each register can be used as general purpose register to store
8 bit data and can also be used as memory location. DPTR does not have single internal
address. It functions as Base register in base relative addressing mode and in-direct jump.
5. Stack pointer (SP): It is 8-bit register. It is byte addressable. Its address is 81H. It is used
to hold the internal RAM memory location addresses which are used as stack memory.
When the data is to be placed on stack by push instruction, the content of stack pointer
is incremented by 1, and when data is retrieved from stack, content of stack of stack
pointer is decremented by 1.

iii. Special function Registers(SFR): The 8051 microcontroller has 11 SFR divided in 4 groups:
A. Timer/Counter register: 8051 microcontroller has 2-16 bit Timer/counter registers called
Timer-reg-T0 And Timer/counter [Link] register is 16 bit register divide into lower and
higher byte register as shown below: These register are used to hold initial no. of count. All of
the 4 register are byte addressable.
1. Timer control register: 8051 microcontroller has two 8-bit timer control register i.e.
TMOD and TCON register. TMOD Register: it is 8-bit register. Its address is 89H. It is byte
addressable. It used to select mode and control operation of time by writing control word.
2. TCON register: It is 8-bit register. Its address is 88H. It is byte addressable. Its MSB 4-
bit are used to control operation of timer/ counter and LSB 4-bit are used for external
interrupt control.
B. Serial data register: 8051 micro controller has 2 serial data register viz. SBUF and SCON.
1. Serial buffer register (SBUF): it is 8-bit register. It is byte addressable .Its address is
99H. It is used to hold data which is to be transferred serially.
2. Serial control register (SCON): it is 8-bit register. It is bit/byte addressable. Its address
is 98H. The 8-bit loaded into this register controls the operation of serial communication.
C. Interrupt register: 8051 µC has 2 8-bit interrupt register.
1. Interrupt enable register (IE): it is 8-bit register. It is bit/byte addressable. Its address
is [Link] is used to enable and disable function of interrupt.
2. Interrupt priority register (IP): It is 8-bit register. It is bit/byte addressable. Its address
is B8H. it is used to select low or high level priority of each individual interrupts.
D. Power control register (PCON): it is 8-bit register. It is byte addressable .Its address is 87H. Its
bits are used to control mode of power saving circuit, either idle or power down mode and also
one bit is used to modify baud rate of serial communication.
Internal RAM
Internal RAM has memory 128-byte. See 8051 hardware for further internal RAM design.
Internal RAM is organized into three distinct areas: 32 bytes working registers from address 00h
to 1Fh 16 bytes bit addressable occupies RAM byte address 20h to 2Fh, altogether 128
addressable bits General purpose RAM from 30h to 7Fh.
Internal ROM
Data memory and program code memory both are in different physical memory but both
have the same addresses. An internal ROM occupied addresses from 0000h to 0FFFh. PC
addresses program codes from 0000h to 0FFFh. Program addresses higher than 0FFFh that
exceed the internal ROM capacity will cause 8051 architecture to fetch codes bytes from external
program memory.

28 bytes of Internal RAM Structure (lower address space)

Fig 5.3: Internal RAM Structure

The lower 32 bytes are divided into 4 separate banks. Each register bank has 8 registers of one byte each. A
register bank is selected depending upon two bank select bits in the PSW register. Next 16bytes are bit
addressable. In total, 128bits (16X8) are available in bitaddressable area. Each bit can be accessed and
modified by suitable instructions. The bit addresses are from 00H (LSB of the first byte in 20H) to 7FH (MSB
of the last byte in 2FH). Remaining 80bytes of RAM are available for general purpose.

Internal Data Memory and Special Function Register (SFR) Map

Fig 5.4 : Internal Data Memory Map

The special function registers (SFRs) are mapped in the upper 128 bytes of internal data memory address.
Hence there is an address overlap between the upper 128 bytes of data RAM and SFRs. Please note that the
upper 128 bytes of data RAM are present only in the 8052 family. The lower128 bytes of RAM (00H - 7FH)
can be accessed both by direct or indirect addressing while the upper 128 bytes of RAM (80H - FFH) are
accessed by indirect [Link] SFRs (80H - FFH) are accessed by direct addressing only. This feature
distinguishes the upper 128 bytes of memory from the SFRs, as shown in fig 5.4.

SFR Map

The set of Special Function Registers (SFRs) contains important registers such as Accumulator, Register B, I/O
Port latch registers, Stack pointer, Data Pointer, Processor Status Word (PSW) and various control registers.
Some of these registers are bit addressable (they are marked with a * in the diagram below). The detailed
map of various registers is shown in the following figure.
Address
F8H
F0H B*
E8H
E0H ACC*
D8H
D0H PSW*
C8H (T2CON)* (RCAP2L) (RCAP2H) (TL2) (TH2)
C0H
B8H IP*
B0H P3*
 A8H IE*
A0H P2*
98H SCON* SBUF
90H P1*
88H TCON* TMOD TL0 TL1 TH0 TH1
80H P0* SP DPL DPH PCON

Fig 5.5: SFR Map

It should be noted hat all registers appearing in the first column are bit addressable. The bit address of a bit
in the register is calculated as follows.
Bit address of 'b' bit of register 'R' is
Address of register 'R' + b
where 0 ≤ b ≤ 7
Processor Status Word (PSW) Address=D0H

Fi g 5.6: Processor Status Word

PSW register stores the important status conditions of the microcontroller. It also stores the bank select bits
(RS1 & RS0) for register bank selection.

Power saving modes of operation :

8051 has two power saving modes. They are -

1. Idle Mode
2. Power Down mode.

The two power saving modes are entered by setting two bits IDL and PD in the special function register
(PCON) respectively.

The structure of PCON register is as follows.

PCON: Address 87H

The schematic diagram for 'Power down' mode and 'Idle' mode is given as follows:
 Fig 12.2 Schematic diagram for Power Down and Idle mode implementation

Idle Mode

Idle mode is entered by setting IDL bit to 1 (i.e., =0). The clock signal is gated off to CPU, but not to
the interrupt, timer and serial port functions. The CPU status is preserved entirely. SP, PC, PSW,
Accumulator and other registers maintain their data during IDLE mode. The port pins hold their logical

states they had at the time Idle was initiated. ALE and are held at logic high levels.
Ways to exit Idle Mode:
1. Activation of any enabled interrupt will clear PCON.0 bit and hence the Idle Mode is exited. The
program goes to the Interrupt Service Routine (ISR). After RETI is executed at the end of the ISR,
the next instruction will start from the one following the instruction that enabled Idle Mode.
2. A hardware reset exits the idle mode. The CPU starts from the instruction following the
instruction that invoked the 'Idle' mode.
Power Down Mode:
The Power down Mode is entered by setting the PD bit to 1. The internal clock to the entire
microcontroller is stopped (frozen). However, the program is not dead. The Power down Mode is exited
(PCON.1 is cleared to 0) by Hardware Reset only. The CPU starts from the next instruction where the
Power down Mode was invoked. Port values are not changed/ overwritten in power down mode. Vcc
can be reduced to as low as 2V in Power Down mode. However, Vcc has to be restored to normal value
before Power Down mode is exited.

MEMORY ORGANISATION:
The 8051 has two types of memory and these are Program Memory and Data Memory. Program Memory
(ROM) is used to permanently save the program being executed, while Data Memory (RAM) is used for
temporarily storing data and intermediate results created and used during the operation of the
microcontroller. Depending on the model in use (we are still talking about the 8051 microcontroller
family in general) at most a few Kb of ROM and 128 or 256 bytes of RAM is used
All 8051 microcontrollers have a 16-bit addressing bus and are capable of addressing 64 kb memory. It
is neither a mistake nor a big ambition of engineers who were working on basic core development. It is
a matter of smart memory organization which makes these microcontrollers a real “programmers’
goody“.
Program Memory
The first models of the 8051 microcontroller family did not have internal program memory. It was added
as an external separate chip. These models are recognizable by their label beginning with 803 (for
example 8031 or 8032). All later models have a few Kbyte ROM embedded. Even though such an amount
of memory is sufficient for writing most of the programs, there are situations when it is necessary to use
additional memory as well. A typical example are so called lookup tables. They are used in cases when
equations describing some processes are too complicated or when there is no time for solving them. In
such cases all necessary estimates and approximates are executed in advance and the final results are
put in the tables (similar to logarithmic tables).

How does the microcontroller handle external memory depends on the EA pin logic state:
EA=0 In this case, the microcontroller completely ignores internal program memory and executes only
the program stored in external memory.
EA=1 In this case, the microcontroller executes first the program from built-in ROM, then the program
stored in external memory.
In both cases, P0 and P2 are not available for use since being used for data and address transmission.
Besides, the ALE and PSEN pins are also used.

Data Memory
As already mentioned, Data Memory is used for temporarily storing data and intermediate results
created and used during the operation of the microcontroller. Besides, RAM memory built in the 8051
family includes many registers such as hardware counters and timers, input/output ports, serial data
buffers etc. The previous models had 256 RAM locations, while for the later models this number was
incremented by additional 128 registers. However, the first 256 memory locations (addresses 0-FFh) are
the heart of memory common to all the models belonging to the 8051 family. Locations available to the
user occupy memory space with addresses 0-7Fh, i.e. first 128 registers. This part of RAM is divided in
several blocks.
The first block consists of 4 banks each including 8 registers denoted by R0-R7. Prior to accessing any of
these registers, it is necessary to select the bank containing it. The next memory block (address 20h-
2Fh) is bit- addressable, which means that each bit has its own address (0-7Fh). Since there are 16 such
registers, this block contains in total of 128 bits with separate addresses (address of bit 0 of the 20h
byte is 0, while address of bit 7 of the 2Fh byte is 7Fh). The third group of registers occupy addresses
2Fh-7Fh, i.e. 80 locations, and does not have any special functions or features.
Additional RAM
In order to satisfy the programmers’ constant hunger for Data Memory, the manufacturers decided to
embed an additional memory block of 128 locations into the latest versions of the 8051 microcontrollers.
However, it’s not as simple as it seems to be… The problem is that electronics performing addressing
has 1 byte (8 bits) on disposal and is capable of reaching only the first 256 locations, therefore. In order
to keep already existing 8-bit architecture and compatibility with other existing models a small trick was
done.
What does it mean? It means that additional memory block shares the same addresses with locations
intended for the SFRs (80h- FFh). In order to differentiate between these two physically separated
memory spaces, different ways of addressing are used. The SFRs memory locations are accessed by
direct addressing, while additional RAM memory locations are accessed by indirect addressing.
Memory expansion
In case memory (RAM or ROM) built in the microcontroller is not sufficient, it is possible to add two
external memory chips with capacity of 64Kb each. P2 and P3 I/O ports are used for their addressing
and data transmission.
From the user’s point of view, everything works quite simply when properly connected because most
operations are performed by the microcontroller itself. The 8051 microcontroller has two pins for data
read RD#(P3.7) and PSEN#. The first one is used for reading data from external data memory (RAM),
while the other is used for reading data from external program memory (ROM). Both pins are active
low. A typical example of memory expansion by adding RAM and ROM chips (Hardward architecture), is
shown in figure above.
Even though additional memory is rarely used with the latest versions of the microcontrollers, we will
describe in short what happens when memory chips are connected according to the previous
schematic. The whole process described below is performed automatically.
When the program during execution encounters an instruction which resides in external memory
(ROM), the microcontroller will activate its control output ALE and set the first 8 bits of address (A0-A7)
on P0. IC circuit 74HCT573 passes the first 8 bits to memory address pins.
A signal on the ALE pin latches the IC circuit 74HCT573 and immediately afterwards 8 higher bits of
address (A8-A15) appear on the port. In this way, a desired location of additional program memory is
addressed. It is left over to read its content.
Port P0 pins are configured as inputs, the PSEN pin is activated and the microcontroller reads from
memory chip.
Similar occurs when it is necessary to read location from external RAM. Addressing is performed in the
same way, while read and write are performed via signals appearing on the control outputs RD (is short
for read) or WR (is short for write).

Interfacing External Memory

If external program/data memory are to be interfaced, they are interfaced in the following way.

Fig 6.1: Circuit Diagram for Interfacing of External Memory

External program memory is fetched if either of the following two conditions are satisfied.

1. (Enable Address) is low. The microcontroller by default starts searching for program from
external program memory.
2. PC is higher than FFFH for 8051 or 1FFFH for 8052.

tells the outside world whether the external memory fetched is program memory or data memory.
is user configurable. is processor controlled.
8051 INSTRUCTION SET AND PROGRAMMING:
8051 Addressing Modes

8051 has four addressing modes.

1. Immediate Addressing: Data is immediately available in the instruction.

For example -
ADD A, #77; Adds 77 (decimal) to A and stores in A
ADD A, #4DH; Adds 4D (hexadecimal) to A and stores in A
MOV DPTR, #1000H; Moves 1000 (hexadecimal) to data pointer

2. Register Addressing: This way of addressing accesses the bytes in the current register bank. Data is
available in the register specified in the instruction. The register bank is decided by 2 bits of Processor
Status Word (PSW).
For example-
ADD A, R0; Adds content of R0 to A and stores in A

3. Direct Addressing: The address of the data is available in the instruction.

For example -
MOV A, 088H; Moves content of SFR TCON (address 088H)to A

4. Register Indirect Addressing: The address of data is available in the R0 or R1 registers as specified in the
instruction.
For example -
MOV A, @R0 moves content of address pointed by R0 to A

External Data Addressing:

Pointer used for external data addressing can be either R0/R1 (256 byte access) or DPTR (64kbyte access).
For example -
MOVX A, @R0; Moves content of 8-bit address pointed by R0 to A
MOVX A, @DPTR; Moves content of 16-bit address pointed by DPTR to A

External Code Addressing:

Sometimes we may want to store non-volatile data into the ROM e.g. look-up tables. Such data may require
reading the code memory. This may be done as follows -
MOVC A, @A+DPTR; Moves content of address pointed by A+DPTR to A
MOVC A, @A+PC; Moves content of address pointed by A+PC to A
INSTRUCTION SET OF 8051:
The C8051 instructions are divided into five functional groups:
1. Arithmetic operations
2. Logical operations
3. Data transfer operations
4. Boolean variable operations
5. Program branching operation

Arithmetic Operations:

OPCODE OPERAND DESCRIPTION NO. OF BYTES

ADD A,Rn Add register to Accumulator 1

ADD A,direct Add direct byte to Accumulator 2

ADD A,@Ri Add indirect RAM to Accumulator 1

ADD A,#data Add immediate data to Accumulator 2

ADDC A,Rn Add register to Accumulator with Carry 1

ADDC A,direct Add direct byte to Accumulator with Carry 2

ADDC A,@Ri Add indirect RAM to Accumulator with Carry 1

ADDC A,#data Add immediate data to Acc with Carry 2

SUBB A,Rn Subtract Register from Acc with borrow 1

SUBB A,direct Subtract direct byte from Acc with borrow 2

SUBB A,@Ri Subtract indirect RAM from ACC with borrow 1

SUBB A,#data Subtract immediate data from Acc with 2

borrow

INC A Increment Accumulator 1

INC Rn Increment register 1

Each port of 8051 has bidirectional capability. Port 0 is called 'true bidirectional port' as it floats (tristated)
when configured as input. Port-1, 2, 3 are called 'quasi bidirectional port'.

Port-0 Pin Structure

Port -0 has 8 pins (P0.0-P0.7).

The structure of a Port-0 pin is shown in fig 6.2.

Fig 6.2: Port-0 Structure

Port-0 can be configured as a normal bidirectional I/O port or it can be used for address/data interfacing for
accessing external memory. When control is '1', the port is used for address/data interfacing. When the
control is '0', the port can be used as a normal bidirectional I/O port.
Let us assume that control is '0'. When the port is used as an input port, '1' is written to the latch. In this
situation both the output MOSFETs are 'off'. Hence the output pin floats. This high impedance pin can be
pulled up or low by an external source. When the port is used as an output port, a '1' written to the latch
again turns 'off' both the output MOSFETs and causes the output pin to float. An external pull-up is required
to output a '1'. But when '0' is written to the latch, the pin is pulled down by the lower MOSFET. Hence the
output becomes zero.
When the control is '1', address/data bus controls the output driver MOSFETs. If the address/data bus
(internal) is '0', the upper MOSFET is 'off' and the lower MOSFET is 'on'. The output becomes '0'. If the
address/data bus is '1', the upper transistor is 'on' and the lower transistor is 'off'. Hence the output is '1'.
Hence for normal address/data interfacing (for external memory access) no pull-up resistors are required.
Port-0 latch is written to with 1's when used for external memory access.

Port-1 Pin Structure

Port-1 has 8 pins (P1.1-P1.7) .The structure of a port-1 pin is shown in fig 6.3.

Fig 6.3 Port 1 Structure

Port-1 does not have any alternate function i.e. it is dedicated solely for I/O interfacing. When used as
output port, the pin is pulled up or down through internal pull-up. To use port-1 as input port, '1' has to be
written to the latch. In this input mode when '1' is written to the pin by the external device then it read fine.
But when '0' is written to the pin by the external device then the external source must sink current due to
internal pull-up. If the external device is not able to sink the current the pin voltage may rise, leading to a
possible wrong reading.

PORT 2 Pin Structure

Port-2 has 8-pins (P2.0-P2.7) . The structure of a port-2 pin is shown in fig 6.4.

Fig 6.4 Port 2 Structure

Port-2 is used for higher external address byte or a normal input/output port. The I/O operation is similar to
Port-1. Port-2 latch remains stable when Port-2 pin are used for external memory access. Here again due to
internal pull-up there is limited current driving capability.

PORT 3 Pin Structure

Port-3 has 8 pin (P3.0-P3.7) . Port-3 pins have alternate functions. The structure of a port-3 pin is shown in
fig 6.5.

Fig 6.5 Port 3 Structure

Each pin of Port-3 can be individually programmed for I/O operation or for alternate function. The alternate
function can be activated only if the corresponding latch has been written to '1'. To use the port as input
port, '1' should be written to the latch. This port also has internal pull-up and limited current driving
capability.

Alternate functions of Port-3 pins are -

P3.0 RxD

P3.1 TxD

P3.2

P3.3

P3.4 T0
 P3.5 T1

P3.6

P3.7

Note:

1. Port 1, 2, 3 each can drive 4 LS TTL inputs.

2. Port-0 can drive 8 LS TTL inputs in address /data mode. For digital output port, it needs external pull-
up resistors.
3. Ports-1,2and 3 pins can also be driven by open-collector or open-drain outputs.
4. Each Port 3 bit can be configured either as a normal I/O or as a special function bit.

Reading a port (port-pins) versus reading a latch

There is a subtle difference between reading a latch and reading the output port pin.
The status of the output port pin is sometimes dependant on the connected load. For instance if a port is
configured as an output port and a '1' is written to the latch, the output pin should also show '1'. If the
output is used to drive the base of a transistor, the transistor turns 'on'.
If the port pin is read, the value will be '0' which is corresponding to the base-emitter voltage of the
transistor.
Reading a latch: Usually the instructions that read the latch, read a value, possibly change it, and then
rewrite it to the latch. These are called "read-modify-write" instructions. Examples of a few instructions are-

ORL P2, A; P2 <-- P2 or A

MOV P2.1, C; Move carry bit to PX.Y bit.

In this the latch value of P2 is read, is modified such that P2.1 is the same as Carry and is then written back
to P2 latch.

Reading a Pin: Examples of a few instructions that read port pin, are-
MOV A, P0 ; Move port-0 pin values to A
MOV A, P1; Move port-1 pin values to A

INTERRUPTS OF 8051:
There are five interrupt sources for the 8051, which means that they can recognize 5 different
events that can interrupt regular program execution. Each interrupt can be enabled or disabled
by setting bits of the IE register. Likewise, the whole interrupt system can be disabled by clearing
the EA bit of the same register. Refer to figure below.
Now, it is necessary to explain a few details referring to external interrupts- INT0 and INT1. If
the IT0 and IT1 bits of the TCON register are set, an interrupt will be generated on high to low
transition, i.e. on the falling pulse edge (only in that moment). If these bits are cleared, an
interrupt will be continuously executed as far as the pins are held low.

IE Register (Interrupt Enable)

• EA – global interrupt enable/disable:

o 0 – disables all interrupt requests.
o 1 – enables all individual interrupt requests.
• ES – enables or disables serial interrupt:
o 0 – UART system cannot generate an interrupt.
o 1 – UART system enables an interrupt.
• ET1 – bit enables or disables Timer 1 interrupt:
o 0 – Timer 1 cannot generate an interrupt.
o 1 – Timer 1 enables an interrupt.
• EX1 – bit enables or disables external 1 interrupt:
o 0 – change of the pin INT0 logic state cannot generate an interrupt.
 o 1 – enables an external interrupt on the pin INT0 state change.
• ET0 – bit enables or disables timer 0 interrupt:
o 0 – Timer 0 cannot generate an interrupt.
o 1 – enables timer 0 interrupt.
• EX0 – bit enables or disables external 0 interrupt:
o 0 – change of the INT1 pin logic state cannot generate an interrupt.
o 1 – enables an external interrupt on the pin INT1 state change.

Interrupt Priorities
It is not possible to forseen when an interrupt request will arrive. If several interrupts are
enabled, it may happen that while one of them is in progress, another one is requested. In order
that the microcontroller knows whether to continue operation or meet a new interrupt request,
there is a priority list instructing it what to do.
The priority list offers 3 levels of interrupt priority:
1. Reset! The absolute master. When a reset request arrives, everything is stopped and the
microcontroller restarts.
2. Interrupt priority 1 can be disabled by Reset only.
3. Interrupt priority 0 can be disabled by both Reset and interrupt priority 1.
The IP Register (Interrupt Priority Register) specifies which one of existing interrupt sources
have higher and which one has lower priority. Interrupt priority is usually specified at the
beginning of the program. According to that, there are several possibilities:
• If an interrupt of higher priority arrives while an interrupt is in progress, it will be immediately
stopped and the higher priority interrupt will be executed first.
• If two interrupt requests, at different priority levels, arrive at the same time then the higher
priority interrupt is serviced first.
• If the both interrupt requests, at the same priority level, occur one after another, the one which
came later has to wait until routine being in progress ends.
• If two interrupt requests of equal priority arrive at the same time then the interrupt to be
serviced is selected according to the following priority list:
1. External interrupt INT0
2. Timer 0 interrupt
3. External Interrupt INT1
4. Timer 1 interrupt
5. Serial Communication Interrupt

IP Register (Interrupt Priority)

The IP register bits specify the priority level of each interrupt (high or low priority).
 • PS – Serial Port Interrupt priority bit
o Priority 0
o Priority 1
• PT1 – Timer 1 interrupt priority
o Priority 0
o Priority 1
• PX1 – External Interrupt INT1 priority
o Priority 0
o Priority 1
• PT0 – Timer 0 Interrupt Priority
o Priority 0
o Priority 1
• PX0 – External Interrupt INT0 Priority
o Priority 0
o Priority 1

Handling Interrupt
When an interrupt request arrives the following occurs:
1. Instruction in progress is ended.
2. The address of the next instruction to execute is pushed on the stack.
3. Depending on which interrupt is requested, one of 5 vectors (addresses) is written to the
program counter in accordance to the table below:
4.
INTERRUPT SOURCE VECTOR (ADDRESS)

IE0 3h

TF0 Bh

TF1 1B h

RI, TI 23 h

All addresses are in hexadecimal format

 5. These addresses store appropriate subroutines processing interrupts. Instead of them,
there are usually jump instructions specifying locations on which these subroutines
reside.
6. When an interrupt routine is executed, the address of the next instruction to execute is poped
from the stack to the program counter and interrupted program resumes operation from where
it left off.
In short
From the moment an interrupt is enabled, the microcontroller is on alert all the time. When an
interrupt request arrives, the program execution is stopped, electronics recognizes the source
and the program “jumps” to the appropriate address (see the table above). This address usually
stores a jump instruction specifying the start of appropriate subroutine. Upon its execution, the
program resumes operation from where it left off.

Reset
Reset occurs when the RS pin is supplied with a positive pulse in duration of at least 2 machine
cycles (24 clock cycles of crystal oscillator). After that, the microcontroller generates an internal
reset signal which clears all SFRs, except SBUF registers, Stack Pointer and ports (the state of the
first two ports is not defined, while FF value is written to the ports configuring all their pins as
inputs). Depending on surrounding and purpose of device, the RS pin is usually connected to a
power-on reset push button or circuit or to both of them. Figure below illustrates one of the
simplest circuit providing safe power-on reset.
Basically, everything is very simple: after turning the power on, electrical capacitor is being charged for
several milliseconds throgh a resistor connected to the ground. The pin is driven high during this process.
When the capacitor is charged, power supply voltage is already stable and the pin remains connected to
the ground, thus providing normal operation of the microcontroller. Pressing the reset button causes the
capacitor to be temporarily discharged and the microcontroller is reset. When released, the whole
process is repeated…
Microcontrollers normally operate at very high speed. The use of 12 Mhz quartz crystal enables
1.000.000 instructions to be executed per second. Basically, there is no need for higher
operating rate. In case it is needed, it is easy to built in a crystal for high frequency. The problem
arises when it is necessary to slow down the operation of the microcontroller. For example
during testing in real environment when it is necessary to execute several instructions step by
step in order to check I/O pins’ logic state.
Interrupt system of the 8051 microcontroller practically stops operation of the microcontroller
and enables instructions to be executed one after another by pressing the button. Two interrupt
features enable that:
• Interrupt request is ignored if an interrupt of the same priority level is in progress.
• Upon interrupt routine execution, a new interrupt is not executed until at least one instruction
from the main program is executed.
In order to use this in practice, the following steps should be done:
1. External interrupt sensitive to the signal level should be enabled (for example INT0).
2. Three following instructions should be inserted into the program (at the 03hex. address):
What is going on? As soon as the P3.2 pin is cleared (for example, by pressing the button), the
microcontroller will stop program execution and jump to the 03hex address will be executed.
This address stores a short interrupt routine consisting of 3 instructions.
The first instruction is executed until the push button is realised (logic one (1) on the P3.2 pin).
The second instruction is executed until the push button is pressed again. Immediately after
that, the RETI instruction is executed and the processor resumes operation of the main
program. Upon execution of any program instruction, the interrupt INT0 is generated and the
whole procedure is repeated (push button is still pressed). In other words, one button press –
one instruction.
Serial ports on 8051:

Serial Interface
The serial port of 8051 is full duplex, i.e., it can transmit and receive simultaneously.
The register SBUF is used to hold the data. The special function register SBUF is physically two registers. One
is, write-only and is used to hold data to be transmitted out of the 8051 via TXD. The other is, read-only and
holds the received data from external sources via RXD. Both mutually exclusive registers have the same
address 099H.
Serial Port Control Register (SCON)
Register SCON controls serial data communication.
Address: 098H (Bit addressable)

Mode select bits

SM2: multi processor communication bit

REN: Receive enable bit
TB8: Transmitted bit 8 (Normally we have 0-7 bits transmitted/received)
RB8: Received bit 8
TI: Transmit interrupt flag
RI: Receive interrupt flag
Power Mode control Register
Register PCON controls processor powerdown, sleep modes and serial data bandrate. Only one bit of PCON
is used with respect to serial communication. The seventh bit (b7)(SMOD) is used to generate the baud rate
of serial communication.
Address: 87H

SMOD: Serial baud rate modify bit

GF1: General purpose user flag bit 1
GF0: General purpose user flag bit 0
PD: Power down bit
IDL: Idle mode bit
Data Transmission
Transmission of serial data begins at any time when data is written to SBUF. Pin P3.1 (Alternate function bit
TXD) is used to transmit data to the serial data network. TI is set to 1 when data has been transmitted. This
signifies that SBUF is empty so that another byte can be sent.
Data Reception
Reception of serial data begins if the receive enable bit is set to 1 for all modes. Pin P3.0 (Alternate function
bit RXD) is used to receive data from the serial data network. Receive interrupt flag, RI, is set after the data
has been received in all modes. The data gets stored in SBUF register from where it can be read.
Serial Data Transmission Modes:
Mode-0: In this mode, the serial port works like a shift register and the data transmission works
synchronously with a clock frequency of fosc /12. Serial data is received and transmitted through RXD. 8 bits
are transmitted/ received aty a time. Pin TXD outputs the shift clock pulses of frequency f osc /12, which is
connected to the external circuitry for synchronization. The shift frequency or baud rate is always 1/12 of
the oscillator frequency.

Fig 11.1 Data transmission/reception in Mode-0

Mode-1 (standard UART mode) :
In mode-1, the serial port functions as a standard Universal Asynchronous Receiver Transmitter (UART)
mode. 10 bits are transmitted through TXD or received through RXD. The 10 bits consist of one start bit
(which is usually '0'), 8 data bits (LSB is sent first/received first), and a stop bit (which is usually '1'). Once
received, the stop bit goes into RB8 in the special function register SCON. The baud rate is variable.
The following figure shows the way the bits are transmitted/ received.
 Fig 11.2 Data transmission format in UART mode

Bit time= 1/fbaud

In receiving mode, data bits are shifted into the receiver at the programmed baud rate. The data word (8-
bits) will be loaded to SBUF if the following conditions are true.

1. RI must be zero. (i.e., the previously received byte has been cleared from SBUF)
2. Mode bit SM2 = 0 or stop bit = 1.

After the data is received and the data byte has been loaded into SBUF, RI becomes one.

Mode-1 baud rate generation:

Timer-1 is used to generate baud rate for mode-1 serial communication by using overflow flag of the timer
to determine the baud frequency. Timer-1 is used in timer mode-2 as an auto-reload 8-bit timer. The data
rate is generated by timer-1 using the following formula.

Where,
SMOD is the 7th bit of PCON register
fosc is the crystal oscillator frequency of the microcontroller

It can be noted that fosc/ (12 X [256- (TH1)]) is the timer overflow frequency in timer mode-2, which is the
auto-reload mode.

If timer-1 is not run in mode-2, then the baud rate is,

Timer-1 can be run using the internal clock, fosc/12 (timer mode) or from any external source via pin T1
(P3.5) (Counter mode).

Example: If standard baud rate is desired, then 11.0592 MHz crystal could be selected. To get a standard
9600 baud rate, the setting of TH1 is calculated as follows.

Assuming SMOD to be '0'

Or,

Or,

In mode-1, if SM2 is set to 1, no receive interrupt (RI) is generated unless a valid stop bit is received.

Serial Data Mode-2 - Multiprocessor Mode :

In this mode 11 bits are transmitted through TXD or received through RXD. The various bits are as follows: a
start bit (usually '0'), 8 data bits (LSB first), a programmable 9 th (TB8 or RB8)bit and a stop bit (usually '1').
While transmitting, the 9 th data bit (TB8 in SCON) can be assigned the value '0' or '1'. For example, if the
information of parity is to be transmitted, the parity bit (P) in PSW could be moved into TB8. On reception
of the data, the 9 th bit goes into RB8 in 'SCON', while the stop bit is ignored. The baud rate is programmable
to either 1/32 or 1/64 of the oscillator frequency.

f baud = (2 SMOD /64) fosc.

Mode-3 - Multi processor mode with variable baud rate :

In this mode 11 bits are transmitted through TXD or received through RXD. The various bits are: a start bit
(usually '0'), 8 data bits (LSB first), a programmable 9 th bit and a stop bit (usually '1').
Mode-3 is same as mode-2, except the fact that the baud rate in mode-3 is variable (i.e., just as in mode-1).

f baud = (2 SMOD /32) * ( fosc / 12 (256-TH1)) .

This baud rate holds when Timer-1 is programmed in Mode-2.

Counters and Timers:
As you already know, the microcontroller oscillator uses quartz crystal for its operation. As the
frequency of this oscillator is precisely defined and very stable, pulses it generates are always of
the same width, which makes them ideal for time measurement. Such crystals are also used in
quartz watches. In order to measure time between two events it is sufficient to count up pulses
coming from this oscillator. That is exactly what the timer does. If the timer is properly
programmed, the value stored in its register will be incremented (or decremented) with each
coming pulse, i.e. once per each machine cycle. A single machine-cycle instruction lasts for 12
quartz oscillator periods, which means that by embedding quartz with oscillator frequency of
12MHz, a number stored in the timer register will be changed million times per second, i.e. each
microsecond.
The 8051 microcontroller has 2 timers/counters called T0 and T1. As their names suggest, their
main purpose is to measure time and count external events. Besides, they can be used for
generating clock pulses to be used in serial communication, so called Baud Rate.
Timer T0
As seen in figure below, the timer T0 consists of two registers – TH0 and TL0 representing a low
and a high byte of one 16-digit binary number.

Accordingly, if the content of the timer T0 is equal to 0 (T0=0) then both registers it consists of
will contain 0. If the timer contains for example number 1000 (decimal), then the TH0 register
(high byte) will contain the number 3, while the TL0 register (low byte) will contain decimal
number 232.

Formula used to calculate values in these two registers is very simple:

TH0 × 256 + TL0 = T
Matching the previous example it would be as follows:
3 × 256 + 232 = 1000
Since the timer T0 is virtually 16-bit register, the largest value it can store is 65 535. In case of
exceeding this value, the timer will be automatically cleared and counting starts from 0. This
condition is called an overflow. Two registers TMOD and TCON are closely connected to this
timer and control its operation.
TMOD Register (Timer Mode)
The TMOD register selects the operational mode of the timers T0 and T1. As seen in figure
below, the low 4 bits (bit0 – bit3) refer to the timer 0, while the high 4 bits (bit4 – bit7) refer to
the timer 1. There are 4 operational modes and each of them is described herein.

Bits of this register have the following function:

• GATE1 enables and disables Timer 1 by means of a signal brought to the INT1 pin (P3.3):
o 1 – Timer 1 operates only if the INT1 bit is set.
o 0 – Timer 1 operates regardless of the logic state of the INT1 bit.
• C/T1 selects pulses to be counted up by the timer/counter 1:
o 1 – Timer counts pulses brought to the T1 pin (P3.5).
o 0 – Timer counts pulses from internal oscillator.
• T1M1,T1M0 These two bits select the operational mode of the Timer 1.
T1M1 T1M0 MODE DESCRIPTION

0 0 0 13-bit timer

0 1 1 16-bit timer

1 0 2 8-bit auto-reload

1 1 3 Split mode

• GATE0 enables and disables Timer 1 using a signal brought to the INT0 pin (P3.2):
 o 1 – Timer 0 operates only if the INT0 bit is set.
o 0 – Timer 0 operates regardless of the logic state of the INT0 bit.
• C/T0 selects pulses to be counted up by the timer/counter 0:
o 1 – Timer counts pulses brought to the T0 pin (P3.4).
o 0 – Timer counts pulses from internal oscillator.
• T0M1, T0M0 These two bits select the oprtaional mode of the Timer 0.
T0M1 T0M0 MODE DESCRIPTION

0 0 0 13-bit timer

0 1 1 16-bit timer

1 0 2 8-bit auto-reload

1 1 3 Split mode

Timer 0 in mode 0 (13-bit timer)

This is one of the rarities being kept only for the purpose of compatibility with the previuos
versions of microcontrollers. This mode configures timer 0 as a 13-bit timer which consists of all
8 bits of TH0 and the lower 5 bits of TL0. As a result, the Timer 0 uses only 13 of 16 bits. How
does it operate? Each coming pulse causes the lower register bits to change their states. After
receiving 32 pulses, this register is loaded and automatically cleared, while the higher byte
(TH0) is incremented by 1. This process is repeated until registers count up 8192 pulses. After
that, both registers are cleared and counting starts from 0.
Timer 0 in mode 1 (16-bit timer)
Mode 1 configures timer 0 as a 16-bit timer comprising all the bits of both registers TH0 and
TL0. That’s why this is one of the most commonly used modes. Timer operates in the same way
as in mode 0, with difference that the registers count up to 65 536 as allowable by the 16 bits.

Timer 0 in mode 2 (Auto-Reload Timer)

Mode 2 configures timer 0 as an 8-bit timer. Actually, timer 0 uses only one 8-bit register for
counting and never counts from 0, but from an arbitrary value (0-255) stored in another (TH0)
register.
The following example shows the advantages of this mode. Suppose it is necessary to constantly
count up 55 pulses generated by the clock.
If mode 1 or mode 0 is used, It is necessary to write the number 200 to the timer registers and
constantly check whether an overflow has occured, i.e. whether they reached the value 255.
When it happens, it is necessary to rewrite the number 200 and repeat the whole procedure.
The same procedure is automatically performed by the microcontroller if set in mode 2. In fact,
only the TL0 register operates as a timer, while another (TH0) register stores the value from
which the counting starts. When the TL0 register is loaded, instead of being cleared, the
contents of TH0 will be reloaded to it. Referring to the previous example, in order to register
each 55th pulse, the best solution is to write the number 200 to the TH0 register and configure
the timer to operate in mode 2.
Timer 0 in Mode 3 (Split Timer)
Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-bit timers. In
other words, the 16-bit timer consisting of two registers TH0 and TL0 is split into two
independent 8-bit timers. This mode is provided for applications requiring an additional 8-bit
timer or counter. The TL0 timer turns into timer 0, while the TH0 timer turns into timer 1. In
addition, all the control bits of 16-bit Timer 1 (consisting of the TH1 and TL1 register), now
control the 8-bit Timer 1. Even though the 16-bit Timer 1 can still be configured to operate in
any of modes (mode 1, 2 or 3), it is no longer possible to disable it as there is no control bit to
do it. Thus, its operation is restricted when timer 0 is in mode 3.

The only application of this mode is when two timers are used and the 16-bit Timer 1 the
operation of which is out of control is used as a baud rate generator.
Timer Control (TCON) Register
TCON register is also one of the registers whose bits are directly in control of timer operation.
Only 4 bits of this register are used for this purpose, while rest of them is used for interrupt
control to be discussed later.

• TF1 bit is automatically set on the Timer 1 overflow.

• TR1 bit enables the Timer 1.
o 1 – Timer 1 is enabled.
o 0 – Timer 1 is disabled.
• TF0 bit is automatically set on the Timer 0 overflow.
• TR0 bit enables the timer 0.
o 1 – Timer 0 is enabled.
o 0 – Timer 0 is disabled.

How to use the Timer 0 ?

In order to use timer 0, it is first necessary to select it and configure the mode of its operation.
Bits of the TMOD register are in control of it:

Referring to figure above, the timer 0 operates in mode 1 and counts pulses generated by
internal clock the frequency of which is equal to 1/12 the quartz frequency.
Turn on the timer:
The TR0 bit is set and the timer starts operation. If the quartz crystal with frequency of 12MHz is
embedded then its contents will be incremented every microsecond. After 65.536 microseconds,
the both registers the timer consists of will be loaded. The microcontroller automatically clears
them and the timer keeps on repeating procedure from the beginning until the TR0 bit value is
logic zero (0).
How to ‘read’ a timer?
Depending on application, it is necessary either to read a number stored in the timer registers
or to register the moment they have been cleared.
– It is extremely simple to read a timer by using only one register configured in mode 2 or 3. It is
sufficient to read its state at any moment. That’s all!
– It is somehow complicated to read a timer configured to operate in mode 2. Suppose the
lower byte is read first (TL0), then the higher byte (TH0). The result is:
TH0 = 15 TL0 = 255
Everything seems to be ok, but the current state of the register at the moment of reading was:
TH0 = 14 TL0 = 255
In case of negligence, such an error in counting (255 pulses) may occur for not so obvious but
quite logical reason. The lower byte is correctly read (255), but at the moment the program
counter was about to read the higher byte TH0, an overflow occurred and the contents of both
registers have been changed (TH0: 14→15, TL0: 255→0). This problem has a simple solution.
The higher byte should be read first, then the lower byte and once again the higher byte. If the
number stored in the higher byte is different then this sequence should be repeated. It’s about
a short loop consisting of only 3 instructions in the program.
There is another solution as well. It is sufficient to simply turn the timer off while reading is
going on (the TR0 bit of the TCON register should be cleared), and turn it on again after reading
is finished.
Timer 0 Overflow Detection
Usually, there is no need to constantly read timer registers. It is sufficient to register the
moment they are cleared, i.e. when counting starts from 0. This condition is called an overflow.
When it occurrs, the TF0 bit of the TCON register will be automatically set. The state of this bit
can be constantly checked from within the program or by enabling an interrupt which will stop
the main program execution when this bit is set. Suppose it is necessary to provide a program
delay of 0.05 seconds (50 000 machine cycles), i.e. time when the program seems to be
stopped:
First a number to be written to the timer registers should be calculated:

Then it should be written to the timer registers TH0 and TL0:

When enabled, the timer will resume counting from this number. The state of the TF0 bit, i.e.
whether it is set, is checked from within the program. It happens at the moment of overflow, i.e.
after exactly 50.000 machine cycles or 0.05 seconds.
How to measure pulse duration?
Suppose it is necessary to measure the duration of an operation, for example how long a device has
been turned on? Look again at the figure illustrating the timer and pay attention to the function of the
GATE0 bit of the TMOD register. If it is cleared then the state of the P3.2 pin doesn’t affect timer
operation. If GATE0 = 1 the timer will operate until the pin P3.2 is cleared. Accordingly, if this pin is
supplied with 5V through some external switch at the moment the device is being turned on, the timer
will measure duration of its operation, which actually was the objective.
How to count up pulses?
Similarly to the previous example, the answer to this question again lies in the TCON register.
This time it’s about the C/T0 bit. If the bit is cleared the timer counts pulses generated by the
internal oscillator, i.e. measures the time passed. If the bit is set, the timer input is provided
with pulses from the P3.4 pin (T0). Since these pulses are not always of the same width, the
timer cannot be used for time measurement and is turned into a counter, therefore. The highest
frequency that could be measured by such a counter is 1/24 frequency of used quartz-crystal.
Timer 1
Timer 1 is identical to timer 0, except for mode 3 which is a hold-count mode. It means that
they have the same function, their operation is controlled by the same registers TMOD and
TCON and both of them can operate in one out of 4 different modes.
 TH1 TU

bitl5 bit14 b it13 b it \Z bitl1 bit \0 b it9 hit8 tsit7 bit6 bits bit4 bits bitz bi Al bit0

Timer 1

0 0 D 0 0 0 0 0 **•• 'R •
Bitname
b'âT 5it6 bi‹s bit4 bits bit2 bit1 b'J0

0 0 0 0 0 0 0 0 *” ”^’R=‹*

TU Bit name
MICROCONTROLLER ARM7

Chapter-5. ARM7

Introduction to ARM7
ARM 7
• The ARM processor core originates within a British computer company called Acorn.
• In the mid-1980s they were looking for replacement for the 6502 processor used in their BBC computer
range, which were widely used in UK schools.
• None of the 16-bit architectures becoming available at that time met their requirements, so they designed
their own 32-bit processor.
• The RISC philosophy was used by ARM to create embedded processor.
• The first ARM processor was developed at Acorn Computers Limited.
• Initially ARM stood for Acorn RISC Machine. Later, it is renamed as Advanced RISC Machine.
• ARM Ltd now designs the ARM family of RISC processor cores with a range of other supporting
technologies.
• ARM does not fabricate silicon itself, but instead just produces the design.
• It is an Intellectual Property (or IP) company.

Features of ARM7
• 32/16-bit RISC architecture.
• 32-bit ARM instruction set for maximum performance and flexibility.
• 16-bit Thumb instruction set for increased code density.
• Unified bus interface, 32-bit data bus carries both instructions and data.
• Three-stage pipeline.
• 32-bit ALU.
• Very small die size and low power consumption.
• Fully static operation.
• Coprocessor interface.

Architecture of ARM7
MICROCONTROLLER ARM7

1. Data bus
• The data enters the ARM core through the data bus.
• The same data bus is used by all the instructions as the ARM core uses VonNeumann architecture.
• There are two buses A and B The data can be an instruction opcode

2. Multiply-Accumulate Unit (MAC) and Arithmetic Logic Unit (ALU)

• Generally the ARM Instructions are of three operands.
• In order to store the two input operands registers R and R₁ are used.
• The ALU or MAC reads the two operand values from R and R, registers using the Abs and B
• Then the desired operation is done and the result is stored using the result bus or Cbus in the destination
register Rd.

3. Address register
• It is responsible for storing the address generated by the load and store Instructions and placing it on the
address bus.

4. Incrementer
• The Incrementer is responsible for upgrading the address register contents before the core reads the next
register value from memory location or writes the next register value to memory location.
• In case of exception/interrupt the execution of instructions is changed.

5. Barrel shifter
• The R register contents can be preprocessed in the barrel shifter before applying them to the ALU.
• A wide range of shift operations are possible using the barrel shifter and the ALU.

6. Register file
• The register file is a bank of sixteen 32-bit registers. The registers are used for storing data.

7. Sign extend
• Some of the instructions require signed values.
• Whenever the processor reads an 8 or 16 bit signed number from the memory, the sign extend hardware
converts the numbers to 32 bit values and places the number in the register file.

8. Instruction decoder
The instruction decoder decodes the instruction opcode read from the memory and then the instruction is
executed.
The ARM cores are of three types:
(1) Application Core
(2) Embedded Core
(3) Secure Core
• Since the architecture of ARM based processor takes very less space and performs a lot of operations it
is fit to be used in embedded systems
MICROCONTROLLER ARM7

Programming Model of ARM7

• The ARM Processor can be operated in seven different modes.
• The current mode of the processor decides the availability of the registers to the programmer.
• The registers include of
(i) A dedicated program counter.
(ii) A dedicated current program status register.
(iii) a dedicated saved program status registers.
(iv) 30 general purpose registers.
• However these registers are arranged into several banks, with the accessible bank being governed by
the processor mode.
• Each processor mode can access a particular set of RO- R12 registers, R13 register (stack pointer) and
link register (R14), register R15 (program counter) and CPSR (current program status register).
• Privileged modes can access SPSR (saved program status register).

1. General purpose registers

• The registers R0 to R12 are used as general purpose registers.
• They can be used for holding the data or addresses.
• Depending on the purpose, the registers R13 to R15 can also be used as general purpose registers.

2. Stack Pointer (SP-R13)

• Register R13 is a stack pointer.
• It stores the top of the stack in the current processor mode

3. Link Register (LR-R14)

• Register R14 is a link register.
• It is used for storing the return address in case of subroutine calls.
MICROCONTROLLER ARM7

4. Program Counter (PC-R15)

• Register R15 is the program counter.
• It stores the address of the next instruction to be fetched from the memory by the processor.
• It can be used in place of registers RO to R14. Hence it is considered as one of the general purpose
registers.

5. Registers RO-R7
• These registers are called as unbanked registers.
• They are general purpose registers and can be used wherever general purpose registers can be used.
• Each register is a 32 bit physical register in all the processor modes.
• The registers RO-R7 do not have any specific use.

6. Registers R8-R14
• These registers are called as banked registers.
• This is because the physical size of each of these registers depends on the current processor mode.

Program Status Registers of ARM7

• The ARM architecture supports two program
status registers.
• They are the current program status register
(CPSR) and the saved program status register
(SPSR).
• The CPSR is accessible in all the processor
modes while the SPSR is accessible in
privileged modes.
• The CPSR contains condition code flags, interrupt disable bits, current processor mode and other control
and status information.
• Each exception mode contains a saved program status register (SPSR).
• It is responsible for holding the value of CPSR in case the exception occurs.

1. Control Bits (Bits 0-7)

• Bits (0-7) are the control bits of CPSR and SPSR
register.
• These bits change incase an exception occurs.
• The control bits can be altered by the software
only when the processor is in privilege mode.

2. Bits 0-4 (Processor Mode)

• These bits determine the processor mode

3. Bit 5 (Thumb Bit) (Architecture

version 4T only)
• The Thumb bit determines the state of the ARM
core.
• The state of core determines the instruction set
that is being executed.
MICROCONTROLLER ARM7

4. Bits 6, 7 (Interrupt Masks)

• The ARM core has two interrupts.
• They are fast interrupt request (FIQ) and interrupt request (IRQ).
• These interrupts are maskable. Bit 6 (F) controls the FIQ and Bit 7 (I) controls the IRQ.
• For their mask enable/disable.
• When bit is set i.e. F = 1 or I = 1 the respective interrupt is masked or disabled.
• When bit is clear, the interrupt is unmasked or available.
5. Condition code flags
• The flags are updated by the operations performed by the ALU.
• The flags in the CPSR can be tested by the instructions to determine whether the instruction is to be
executed or not.
• The flags can be updated by execution of a comparison instruction or by execution of arithmetic, logical
or move instruction where the destination register is not R15.

6. Bit 27 (Saturation Flag : Q)

• It is present on the DSP extension of ARM processor core.
• This bit is set if an overflow or saturation occurs. The hardware can only set this flag.
• In order to clear this bit we need to write to CPSR directly.
• In case of SPSR this bit is used to hold and restore the CPSR Q flag incase of exceptions.

7. Bit 28 (Overflow Flag : V)

• This flag is set if an overflow occurs while addition or subtraction.
• For operations other than addition/subtraction overflow is unchanged.

8. Bit 29 (Carry Flag : C)

• This flag is set if one of the following conditions exist.
a. For addition alongwith the comparison instruction CMP, if the addition produced a carry otherwise
flag is clear.
b. For subtraction alongwith the comparison instruction CMN, if subtraction produced a borrow, then the
carry flag is cleared otherwise it is set.
c. For operations not involved with addition/subtraction but include a shift operation, the carry flag is set
to the last bit shifted out of the value by the shifter. For operations that do not include a shift, carry flag
remains unaltered.

9. Bit 30 (Zero flag : Z)

• If the result of comparison is zero i.e. equal numbers are present then the zero flag is set to 1. Z flag is
otherwise cleared.

10. Bit 31 (Negative Flag : N)

• The negative flag is set if the result is negative and regarded as two’s complement of a signed integer.
• Otherwise the flag is cleared if the result is positive or zero.

11. Reserved bits

• These bits are reserved for further expansion in future.
• The user should write his program in such manner that the bits are unmodified.
• If the user fails to do this it may lead to side-effects on future versions of the architecture.
MICROCONTROLLER ARM7

Barrel Shifter
• The ARM processor does not support actual shift instructions.
• But instead it supports a Barrel shifter.
• The Barrel shifter is responsible for carrying the shifts as a part of other instructions.
• The barrel shifter can be used to perform left shift operation by required amount. i.e. it multiplies by the
powers of 2.
• The barrel shifter can also to used to
perform logical and arithmetic right.
• In logical shift right the barrel shifter
shifts the bits to the right by specified
amount. i.e. it divides by power of 2.
• In arithmetic shift right the barrel shifter
shifts the bits to the right by specified
amount and preserves the sign bit, for 2's
complement operations.
• The barrel shifter can also be used for
performing rotations.
• In Rotate Right (ROR) the barrel shifter
performs operation similar to arithmetic
shift right but wraps the bits around as
they leave the LSB and appear as MSB.
• The last bit rotated is also used as carry
out along with LSB.
• For Rotate Right through carry or
Rotate Right Extended (RRX) the barrel
shifter uses the CPSR C flag as 33rd bit.
• In this operation the bits are rotated
through the carry.
• The carry propagates to LSB and MSB
to carry.
• Using the barrel shifter alongwith
ALU a wide range of addresses can
be calculated.
• The contents of register Rm are
preprocessed in the barrel shifter
before applying them as input to the
ALU.
• The register Rm can be a register, shifted register or immediate value.
MICROCONTROLLER ARM7

Pipelining
• The Process of fetching the
next instruction while the
current instruction is being
executed is called as
“pipelining”.
• Pipelining is supported by
the processor to increase the
speed of program execution.
• Increases throughput.
Several operations take place
simultaneously, rather than
serially in pipelining.
• The Pipeline has three stages
fetch, decode and execute
• The three stages used in the
pipeline are:
(i) Fetch : In this stage the
ARM processor fetches the
instruction from the memory.
(ii) Decode : In this stage
recognizes the instruction that
is to be executed.
(iii) Execute : In this stage the
processor processes the
instruction and writes the result
back to desired register.
• If these three stages of
execution are overlapped, it will achieve higher speed of execution. Such pipeline exists in version 7 of
ARM processor.
• Once the pipeline is filled, each instructions require s one cycle to complete execution.
MICROCONTROLLER ARM7

Interrupt/Exceptions and its handling in ARM7

• An exception is an unexpected event that occurs during the execution of a task and halts its normal
execution
• It is up to the system designer who can decide which hardware peripheral can produce which
interrupt/execution. The different ARM exceptions are as follows :
• Exceptions that are a direct effect of executing an instruction - Software interrupts, undefined
instructions that include coprocessor instructions where the requested coprocessor is absent and pre-fetch
aborts.
• Both are caused by an instruction entering the execution stage of the ARM instruction pipeline.
• Exceptions generated as a side effect of an instruction - Data aborts that arise when a memory fault
occurs during a load or store data access.
• External exceptions, not related to instructions flow –
∗ Reset
∗ Interrupt Request
∗ Fast Interrupt Request
• When an exception/interrupt takes place , ARM completes the execution of its current instruction and
then moves on to handle the exception.
• The different ways in which interrupts are handled are as follows:

1. Non-nested interrupt handling scheme –

• This is the simplest interrupt handler. In this, interrupts are disabled until control is returned to the
interrupted task.
• One interrupt can be served at a time
• It is not suitable for complex embedded systems.

2. Nested interrupt handling scheme –

• It can handle more than one interrupt at a time by enabling interrupts before fully serving the current
interrupt.
• The latency is improved and system is more complex.
• Also, normal interrupts can block critical interrupts as there is no priority

3. Prioritized simple interrupt handling

• In this, each interrupt has a priority. Priority interrupts can be handled by software or hardware.
• Hence, the above mentioned ones are the main schemes to handle interrupts
MICROCONTROLLER ARM7

ARM Development Tool

• There are various tools available for the
development of the ARM based
programming.
• The programming can be done using
either assembly language programming
or high level language programming like
C.
• In case of programming is done by
assembly language programming, we
need an assembler.
• In case the programming is done using
C language, its need compiler.

ARM Assembler
• The source to the assembler is the
assembly file i.e. the near machine
language instructions.
• It includes the ARM and the THUMB instructions.
• The assembler as discussed earlier gives a of file.

Compiler
• The C compiler is mostly used for writing
programs
• The advantage of writing programs in C is
that it is a very simple programming language
and the complicated task be easily
implemented.
• The only disadvantage is that there are
certain operations that are not possible in C
and that we need to use the assembly
programming language
• C generates an object code that is extremely
fast an compact, but it is not as fast as the
object code generated by a good programmer
using assembly language.

Combining C and assembly

There are 2 ways of combining C and
Assembly language

Method 1
Some compilers have built-in inline
assembler that are used to include assembly
language routines in the C language program.
These assembly language routines are compiled along with the 'C' language routines rather and then
linked together using the linker in the C Compiler
MICROCONTROLLER ARM7

Method 2
Some compilers do not have an in-line assembler. In such cases we need to write separate C routines and
assembly routines.
• They are to be separately compiled or assembled.
• The C subroutines are to be compiled to give the object file; while the assembly files are to be assembled
to give the object file.
• The multiple object files generated in this manner are to be linked together to give a single executable
file.
• It shows Compile, Assemble, and link processes using C compiler, Assembler and Linker.

Linker
• The linker can link one or more .a of files or the object files.
• Hence the input to the Linker is one or multiple .aof files and its output is a .aif file.
• It uses the object libraries to perform its task.
• If the object files are compiled in such a manner that the full debug information is to be generated then
the full symbolic debug tables will be generated when linking the source code.

ARMsd
• It is a symbolic debugger.
• The ARMSd as discussed earlier can be used to emulate the ARM based programs written in C or in
assembly languages.
• It can be either interfaced with the ARM development tool kit or with the ARMulator.
• The ARMulator will give a proper timing related idea and works as an emulator for ARM processor.
• The ARMSd can also be used to interface the code with the development toolkit and verify the working
of the program written.

Addressing Modes in ARM7

• It refer to the different methods of addressing (selecting) the operand

Addressing modes for Data Processing Operand (i.e op1):

• These are two method for addressing these operands

Unmodified value :
• In this addressing mode, the register or a value is given unmodified i.e. without any shift or rotation e.
g,
• MOV R0, # 1234 H : This instruction will move the immediate constant value 1234 into register R0.
MICROCONTROLLER ARM7

Modified value :
• In this addressing mode, the given value or register is shifted or rotated.
• These are Different shift and rotate operations possible as listed below with examples.

(1) Logical shift left :

• This will take the value of a register and shift the value towards most Significant bits, by n bits. e.g.
MOV R0, R1, LSL # 2
• After the execution of this instruction R0 will become the value of R1 shifted 2 bits.

(2) Logical shift right :

• This will take the value of a register and shift the value towards right by n bits. e.g. MOV R0, R1, LSR
R2
• After the execution of this instruction R0 will have the value of R1 shifted right by R2 times.
• R1 and R2 are not altered.

(3) Arithmetic shift right

• This is similar to logical shift right, except that the MSB is retained as well as shifted for arithmetic
shift operation e.g. MOV R0, R1, ASR #2
• After the execution of this instruction R0 will have the value of R1 Arithmetic; shifted right by 2 bits.

(4) Rotate right :

• This will take the value of a register and rotate it right by n bits e.g. MOV R0, R1, ROR R2
• After the execution of this instruction R0 will have the value of R1 rotated right for R2 times.

(5) Rotate right extended :

• This is similar to Rotate right by one bit, with the carry flag moved into the MSB, i.e. it is similar to
rotate right through carry e. g. MOV R0, R1 RRX
• After the execution of this instruction R0 Will have the value of register R1 rotated right through carry
by 1 bit.

Addressing Modes for Memory Access Operand

• It load and store instructions are used to access memory. The different memory access addressing modes
are
• Each of these addressing modes have offset addressing, Pre-index addressing and post-index addressing
as explained in the examples for each addressing mode

(i) Register indirect addressing mode

• In this addressing mode, a register is used to give the address of the memory location to be accessed. e.
g. LDR R0, [R1]
• This instruction will load the register R0 with the 32-bit word at the memory address held in the register
R1.

(ii) Relative register indirect addressing mode

• In this addressing mode the memory address is generated by an immediate value added to a register.
• Pre index and post index are supported in this addressing mode.
e. g. (a) LDR R0, [R1, #4]
• This instruction will load the register R0 with the word at the memory areas calculated by adding the
constant address contained in the R1 register value 4 to the memory address contained in R1 register e.g.
MICROCONTROLLER ARM7

(b) LDR R0, [R1, #4]!

• This is a pre-index addressing.
• This instruction is same \as that in e. g. (a) this instruction also places the new address in R1 i.e R1 (R1
+ 4.
• e.g. (c)LDR R0, [R1], #4
• This is post-index addressing.
• This instruction will load register R0 with the word at memory address given in register R1.
• It will then calculate the new address by adding 4 to R1 and place this new address in R1

(iii) Base indexed indirect addressing mode

• In this addressing mode the memory address is generated by adding the values of two registers. Pre-
index and post-index are supported also in this addressing mode. e.g. (a) LDR R0, [R1, R2]
• This instruction will load the register R0 with the word at memory address calculated by adding register
R1 to register R2. e.g. (b) LDR R0, [R1, R2]!
• This is pre-index addressing.
• This instruction is same as that in e.g. (a).
• This instruction also places the new address in R1 i. e. R1 (-R1 + R2. e.g. (c) LDR R0, [R1], R2
• This is a post-index addressing.
• This instruction will load register R0 with the word at memory address given in register R1.
• It will then calculate the new address by adding the value in register R2 to register R1 and Place this
new address in R1.

(iv) Base with scaled register addressing mode

• In this addressing mode the memory address is generated by a register value added to another register
shifted left.
• Pre-index and post-index are supported in this addressing mode. e.g. (a) LDR R0, [R1, R2, LSL #2]
• This instruction will load the register R0 with the word at the memory address calculated by adding
register R1 with register R2 shifted left by 2 bits. e.g. (b) LDR RO,[R1, R2,_LSL #2]!
• This is a pre-indexed addressing.
• This instruction will load the register R0 with the word at the memory address calculated by adding
register R1
• It will then calculate the new address by adding register R1 with register R2 shifted left by two bits.
The new address is placed in register.
MICROCONTROLLER ARM7

ARM Instruction Set

• ARM instructions processes data which is in register and access memory with load store instructions.
ARM instructions commonly take two or three operands.
• ARM instructions are categorized in following
A. Data Processing
B. Branch & Branch with Link Instructions (Control Flow)
C. Counting Leading Zero Instruction
D. Multiplication Instruction
E. Status Register Access Instruction
F. Semaphore / Swap Instruction
G. Exception – Generating Instructions ( Software Interrupt )
H. Coprocessor Instructions
I. Load-Store or Data Transfer Instructions

A) Data Processing Instructions

• The data processing instructions manipulate data within registers. They are performing

1. Arithmetic Operations
• Arithmetic instructions implements addition and subtraction of 32 bit signed and unsigned values.
Syntax : <instruction>{<cond>} {S} Rd, Rn, N
MICROCONTROLLER ARM7

2. Comparison & Test Operations

• The Comparison instructions are used to compare a register with a 32 bit value.
• After operation they will update cpsr flag bits according to the result.
• Here no need to apply the S suffix for comparison instruction to update flags
Syntax: <instruction>{<cond>} Rn, N

3. Logical Operations
• Logical Instructions perform
bitwise logical operations on
the two register.
Syntax:
<instruction>{<cond>} {S}
Rd, Rn, N
MICROCONTROLLER ARM7

4. Data Movement between Registers Operations

• Move is the simplest ARM instruction. It is used to move intermediate value or register value to another
register.
Syntax: <instruction> {<cond>} {S} Rd, N

B) Branch & Branch with Link Instructions (Control Flow)

• It is used to change flow of execution. It is also used to call a routine.
• To add subroutine, if-then-else and loops in program then branching instructions needs to be used. These
instructions will point program counter to new address.
• In a register if link bit value is 0 that means it is Branch operation.
• If link bit is 1 then it is Branch with link.

C) Counting Leading Zero Instruction

• Count Leading Zeros counts the number of binary zero bits before the first binary one bit in the value of
the source register, and writes the result to the destination register.
CLZ{cond} Rd, Rm
• Cond is an optional condition code.
• Rd is the destination register.
• Rm is the operand register. Ex. CLZ r4,r9
• Use the CLZ T32 instruction followed by a left shift of Rm by the resulting Rd value to normalize the
value of register Rm. Use MOVS, rather than MOV, to flag the case where Rm is zero:
MICROCONTROLLER ARM7

D) Multiplication Instruction
• Multiply instruction will multiply contents of pair of registers and depending upon the instruction store
the result in another register.
Syntax: MLA{<cond>} {S} Rd, Rm, Rs, Rn
MUL{<cond>} {S} Rd, Rm, Rs

• Example: MUL r0, r1, r2 :This instruction will r0=r1*r2

E) Status Register Access Instruction

• For transferring the contents of program status register to a general purpose register or vice versa, two
instructions are used.
1. MRS : Move to ARM register from system coprocessor register.
MRS{cond} Rn, coproc_register
• cond is an optional condition code.
• coproc_register is the name of the coprocessor register.
• special_register is the name of the coprocessor register that can be written to APSR_nzcv.
• R is the ARM destination register. Rn must not be PC.
Ex. MRS R1, SCTLR ; writes the contents of the CP15 coprocessor register SCTLR ; into R1

2. MSR : Move to system coprocessor register from ARM register.

MSR { cond } coproc_register , Rn
• cond is an optional condition code.
• coproc_register is the name of the coprocessor register.
• Rn is the ARM source register. Rn must not be PC.
Ex. MSR SCTLR, R1 ; writes the contents of R1 into the CP15 coprocessor register ; SCTLR

F) Semaphore / Swap Instruction

• Swap between memory and register.
• Atomic operation preventing any other instruction from reading/writing to that location until it
completes
Syntax: SWP {B} {<cond>} Rd, Rm, [Rn]
MICROCONTROLLER ARM7

G) Exception – Generating Instructions ( Software Interrupt )

• Software Interrupt Instruction (SWI) is used for software interrupt exception which will provide
mechanism for various applications to call operating system routines.
Syntax: SWI{<cond>} SWI_number

H) Coprocessor Instructions
1. CDP : Coprocessor Data Operation
CDP {<cond>} <coproc>, <opcode_1>
<𝑪𝑹𝒅 >, <𝑪𝑹𝒏 >, <𝑪𝑹𝒎 >, <opcode_2>

2. MCR : Move to Coprocessor from ARM register

MICROCONTROLLER ARM7

3. MRC : Move to ARM register from Coprocessor

4. LDC : Load Coprocessor Register

5. STC : Store Coprocessor Register

MICROCONTROLLER ARM7

I) Load-Store or Data Transfer Instructions

• It is used to transfer data between memory and registers.

LDR r0, [r1]

• This will load a word from the address stored in register r1 and placed in register r0.
STR r0, [r1]
• This instruction will store the content of register r0 to the address contained in register r1
MICROCONTROLLER ARM7

Von Neumann & Harvard Architecture Arithmetic & Logic

Unit (ALU)
VON NEUMANN ARCHITECTURE HARVARD ARCHITECTURE

It is ancient computer architecture based on stored It is modern computer architecture based on

program computer concept. Harvard Mark I relay based model.

Same physical memory address is used for Separate physical memory address is used for
instructions and data. instructions and data.

There is common bus for data and instruction Separate buses are used for transferring data and
transfer. instruction.

Two clock cycles are required to execute single

An instruction is executed in a single cycle.
instruction.

It is cheaper in cost. It is costly than Von Neumann Architecture.

CPU can not access instructions and read/write at CPU can access instructions and read/write at the
the same time. same time.

It is used in personal computers and small It is used in micro controllers and signal
computers. processing.

2.
MICROCONTROLLER ARM7

Data Transfer Techniques

1. Programmed I/O
• Data transfer between CPU and the I/O devices may be done in any of the three possible ways:

1. Programmed I/O
In the programmed I/O method of interfacing CPU has direct
control over I/O
• The processor checks the status of the and issues read or write
commands and then transfers data.
• During the data transfer, CPU waits for 1/0 module to
complete operation and hence this system wastes the CPU time.

1. CPU requests for I/O operation.

2. I/O module performs the said operation.
3. I/O module updates the status bits.
4. CPU checks these status bits periodically. Neither the I/O
module cannot inform CPU directly nor can I/O module
interrupt CPU.
5. CPU may wait for the operation to complete or may continue
the operation later

2. Interrupt Driven I/O

• Interrupt Driven I/O overcomes the disadvantage of
programmed I/O i.e. the CPU waiting for I/O device.
• This disadvantage is overcome by CPU not
repeatedly checking for the device being ready or
not instead the I/O module interrupts when ready.

The sequence of operations for interrupt Driven I/O is as below:

1. CPU issues the read command to I/O device.
2. I/O module gets data from peripheral while CPU
does other work.
3. Once the I/0 module completes the data transfer
from I/O device, it interrupts CPU.
4. On getting the interrupt, CPU requests data from the I/O module.
5. 1/0 module transfers the data to CPU.
MICROCONTROLLER ARM7

Direct Memory Access

• DMA stands for Direct Memory Access.

• The I/O module can directly access (read or
write) the memory using this method.
• Interrupt driven and programmed I/O require
active operation of the CPU, hence transfer rate
is limited and CPU is also busy doing the
transfer operation. DMA is the solution for
these problems.
• DMA controller takes over the control of the
bus from CPU for I/O transfer.
• The internal block diagram of a DMA
controller of the I/O module for DMA method
of I/O interfacing
1. The first information is whether the data has
to be read from memory or the data has to be
written to the memory.
• It passes this information via read or writes
control lines that are between the processor and
DMA controllers control logic unit.
2. The processor also provides the starting
address of/ for the data block in the memory,
from where the data block in memory has to be
read or where the data block has to be written
in memory.
• DMA controller stores this in its address
register. It is also
called the starting address register.
3. The processor also sends the word count, i.e.
how many
words are to be read or written.
• It stores this information in the data count or
the word count register
4. The most important is the address of I/O
device that wants
to read or write data. This information is
stored in the data register
MICROCONTROLLER ARM7

RISC vs CISC

RISC CISC
It is a Reduced Instruction Set Computer. It is a Complex Instruction Set Computer.
It emphasizes on software to optimize the It emphasizes on hardware to optimize the
instruction set. instruction set.
It is a hard wired unit of programming in the Microprogramming unit in CISC Processor.
RISC Processor.
It requires multiple register sets to store the It requires a single register set to store the
instruction. instruction.
RISC has simple decoding of instruction. CISC has complex decoding of instruction.
Uses of the pipeline are simple in RISC. Uses of the pipeline are difficult in CISC.
It uses a limited number of instruction that It uses a large number of instruction that
requires less time to execute the instructions. requires more time to execute the instructions.
It uses LOAD and STORE that are independent It uses LOAD and STORE instruction in the
instructions in the register-to-register a program memory to memory interaction of program. a
Interaction.
RISC has more transistors on memory registers. CISC has transistors to store complex
instructions.
The execution time of RISC is very short. The execution time of CISC is longer.
RISC architecture can be used with high-end CISC architecture can be used with low- end
application like telecommunication image applications like home automation, security
processing, video processing, etc. system, etc.
It has fixed format instruction. It has variable format instruction.
The program written for RISC architecture needs Program written for CISC architecture tends to
to take more space in memory. take less space in memory.
Example of RISC: ARM, PA-RISC, Power Examples of CISC: VAX, Motorola 68000
Architecture, Alpha, AVR, ARC and the family, System/360, AMD and the Intel x86
SPARC. CPUs.
MICROCONTROLLER ARM7

Stack & Stack Pointer

• A stack is one of the most commonly used
• A stack, also called Last In First Out (LIFO)
system, is a linear list in which insertion and
deletion can take place
only at one end, called top.
• This structure operates in much the
same way as stack of trays.
• If we want to remove a tray from stack
of trays it can only be removed from the top
only.
• The insertion and deletion operation in
stack terminology are known as PUSH and POP operations.

• Following operation can be performed on stack :

1. Create stack (s) : To create an empty stack s.
2. PUSH (s, i) : To push an element i into stack s.
3. POP (s) : To access and remove the top element of the stack s.
4. Peek (s) : To access the top element of stack s without removing it from the stack s.
5. Overflow : To check whether the stack is full.
6. Underflow : To check whether the stack is empty

• Applications of Stacks are : -

• Stacks can be used for expression evaluation.
• Stacks can be used to check parenthesis matching in an expression.
• Stacks can be used for Conversion from one form of expression to another.
• Stacks can be used for Memory Management.
• Stack data structures are used in backtracking problems.

• Stack Pointer:
• It is used as a memory pointer.
• It points to a memory location in read/write memory, called the stack.
• It is always incremented / decremented by 2 during push and pop operation.
• A stack pointer is a small register that stores the address of the last program request in a stack.
• A stack is a specialized buffer which stores data from the top down. As new requests come in, they "push
the older ones.
MICROCONTROLLER Study 8 bit microcontroller Applications

Chapter-1. Study 8 bit microcontroller Applications

PIC
• PIC is an abbreviation used for Peripheral Interface Controller.
• PIC microcontroller is the smallest microcontroller in the world and are programmed to execute large
number of operations.
• PIC microcontrollers hold the ability of faster execution of programs than microcontrollers.
• It was invented in 1989 by microchip technology corporation and was an 8-bit microcontroller.
• Microchip Inc. has developed the PIC18 series of microcontrollers for use in high-pin count, high-
density, and complex applications.
• The PIC18F microcontrollers offer costefficient solutions for general purpose applications written in C
that use a real-time
• operating system (RTOS) and require a complex communication protocol stack such as TCP/IP, CAN,
USB, or ZigBee

Basic features of PIC18F-Series Microcontrollers

• 77 instructions
• PIC16 source code compatible
• Program memory addressing up to 2Mbytes
• Data memory addressing up to 4Kbytes
• DC to 40MHz operation
• 8 x 8 hardware multiplier
• Interrupt priority levels
• 16-bit-wide instructions, 8-bit-wide data path
• Up to two 8-bit timers/counters
• Up to three 16-bit timers/counters

The 18FXX2 microcontroller family

MICROCONTROLLER Study 8 bit microcontroller Applications

Pin Diagram of PIC18XX Family

MICROCONTROLLER Study 8 bit microcontroller Applications

Architecture of PIC18XX Family

[Link] (Central Processing Unit):

• PIC microcontroller’s CPU consists of
A. Arithmetic logic unit (ALU)
B. Memory unit (MU)
C. Control unit (CU)
D. Accumulator
• ALU is used for arithmetic operations and for logical decisions.
• Memory is used for storing the instructions after processing.
• Control unit is used to control the internal and external peripherals which are connected to the CPU
• Accumulator is used for storing the results

A. Arithmetic logic unit (ALU)

• The ALU gets one of the input operand from W register (WREG) or the IR (in case of immediate
addressing mode).
• The other operand may be given either from a register or a memory location, and hence the other input
side of ALU is connected to the internal data bus.
• For transfer of data, ALU is not required.
• The task of ALU is to perform arithmetic and logical operations.
• The task of data transfer is carried out by the control unit by issuing various control signals

2. CPU Registers : Total 7 registers

• Working Register (WREG)
• Status Register
• File Selection Register (FSR)
MICROCONTROLLER Study 8 bit microcontroller Applications

• Indirect Through FSR (INDF)

• Program Counter Latch Higher (PCLATH)
• Program Counter Low Byte (PCL)
• Program Counter Latch Upper (PCLATU)
• Program Counter Stack

A. Working Register (WREG)

• The WREG (Working Register) Register is one of the most widely used registers of the PIC.
• 8-bit register any data larger than 8 bits must be broken into 8-bits chunks before it is processed.
• There is only one.
• To Moves 8-bit data into WREG (00H ≤ k ≤ FFH) & Move literal value k into WREG (WREG = k)
Example:
• MOVLW 25H  WREG = 25H
• MOVLW 5AH  WREG = 5AH
• Values can be loaded directly into the WREG.
• If values 0 to F are moved into an 8-bit register such as WREG, the rest of the bits are assumed to be
all zeros.
• Moving a value larger than 255 (FF in hex) into the WREG register will truncate the upper byte and
cause a warning in the .err file.
Ex. MOVLW 7F2H; Illegal , becomes F2H
• Add literal value k to WREG (WREG = WREG + k)
Ex. MOVLW 12H → WREG = 12H
ADDLW 16H → WREG = 28H

B. Status Register
• To indicate arithmetic
conditions
• It is a 8-bit register
• Five bits are used
D0: C Carry Flag
D1: DC Digital Carry Flag
D2: Z Zero Flag
D3: OV Overflow Flag
D4: N Negative Flag
D5, D6 & D7 are not implemented & reserved for future used

C. Stack
• PIC18CXX8 has a 21-bit stack with 31 levels, or in other words, a group of 31 memory locations, 21
bits wide, with special purpose.
• Its basic role is to keep the value of program counter after a jump from the main program to an address
of a subprogram.
• In order for a program to know how to go back to the point where it started from, it has to return the
value of a program counter from a stack.
• When moving from a program to a subprogram, program counter is being pushed onto a stack
• When executing instructions such as RETURN, RETLW or RETFIE which were executed at the end of
a subprogram, program counter will be taken from a stack so that program will continue where was
MICROCONTROLLER Study 8 bit microcontroller Applications

stopped before it was interrupted.

• These operations of placing on and taking off from a program counter stack are called PUSH and POP,
and are named according to similar instructions on some bigger microcontrollers.

3. Data Memory
• The data memory address bus is 12 bits with the capability to address up to 4Mbytes.
• The memory in general consists of sixteen banks, each of 256 bytes, where only 6 banks are used.
• The PIC18F452 has 1536 bytes of data memory (6 banks 256 bytes each) occupying the lower end of
the data memory.
• Bank switching happens automatically when a high-level language compiler is used, and thus the user
need not worry about selecting memory banks during programming.

4. Program Memory
• Program memory addresses consist of 21 bits, capable of accessing 2Mbytes of program memory
locations.
• The PIC18F452 has only 32Kbytes of program memory, which requires only 15 bits.
• The remaining 6 address bits are redundant and not used.
• A table pointer provides access to tables and to the data stored in program memory.
• The program memory contains a 31-level stack which is normally used to store the interrupt and
subroutine return addresses.

5. PWM Mode
• The pulse width modulation (PWM) mode
produces a PWM output at 10-bit resolution.
• A PWM output is basically a square waveform
with a specified period and duty cycle.
• The module is controlled by Timer 2. The PWM
period is given by:
Where
PR2 is the value loaded into Timer
2 register TMR2PS is the Timer 2
prescaler value TOSC is the clock
oscillator period (seconds) The
PWM frequency is defined as
1/(PWM period).
• The resolution of the PWM duty
cycle is 10 bits.
• The PWM duty cycle is selected by
writing the eight most significant bits
into the CCPR1L register and the two
least
MICROCONTROLLER Study 8 bit microcontroller Applications

Steps for Programming CCP Module for PWM Generation

• Set the PWM period by writing to the PR2 register
• Set PWM duty cycle by writing to the CCPR1L register and CCP1CON bits
• Make the CCP1 pin an output by clearing the TRISC bit
• Set the TMR2 prescale value and enable Timer 2 by writing to T2CON
• Configure the CCP1 module for PWM operation

Speed Control of DC Motor using PWM Mode of CCP

Module
• A DC motor works by converting electric power into
mechanical work.
• This is accomplished by forcing current through a coil
and producing a magnetic field that spins the motor.
• The speed of the motor is dependent on the voltage given
to it.
• Hence by varying the voltage to DC motor we can control
the speed of DC motor.
• This is mainly implemented by PWM (Pulse Width
Modulation)
• In PWM, a variation in the duty cycle generates variation
in the average DC voltage.
• Pulse Width Modulation (PWM) is one of the methods
to provide Digital to Analog Conversion, by controlling the
duty cycle of the square wave provided at the output the
average voltage varies and hence a DC voltage at the output
of the filter available is dependent on the pulse width
(counter digital value).
• A RC circuit provides filtering and gives the average DC
voltage proportional to the count as shown fig (a)
• The Fig (b) shows how it can be used to turn on a LED and
then to control its intensity by varying the voltage (inversely
proportional) across it.
• The Fig (c) shows how it can be used to turn on a DC motor
and then to control its speed by varying the voltage across it.
MICROCONTROLLER Study 8 bit microcontroller Applications

Features of Atmega 328P

1. High performance, low power AVR® 8-bit microcontroller

2. Advanced RISC architecture

• 131 powerful instructions - most single clock cycle execution
• 32 × 8 general purpose working registers
• Up to 16MIPS throughput at 16MHz
• On-chip 2-cycle multiplier

3. High endurance non-volatile memory segments

• 32K bytes of in-system self-programmable flash program memory
• 1Kbytes EEPROM
• 2Kbytes Internal SRAM

4. Peripheral features
• Two 8-bit Timer/Counters with separate prescaler and compare mode
• One 16-bit Timer/Counter with separate prescaler, compare mode, and capture mode
• Real time counter with separate oscillator
• Six PWM channels
• 8-channel 10-bit ADC in TQFP and QFN/MLF package

5. I/O and packages

• 23 programmable I/O lines
• 32-lead TQFP, and 32-pad QFN/ML

6. Operating voltage:
• 2.7V to 5.5V for ATmega328

7. Temperature range:
• Automotive temperature range: -40°C to +125°C

8. Speed grade:
• 0 to 8MHz at 2.7 to 5.5V (automotive temperature range: -40°C to +125°C)
• 0 to 16MHz at 4.5 to 5.5V (automotive temperature range: -40°C to +125°C)

9. Low power consumption

• Active mode: 1.5mA at 3V-4MHz • Power-down mode: 1μA at 3V
MICROCONTROLLER Study 8 bit microcontroller Applications

Architecture of Atmega 328P

Architecture of Atmega 328P : AVR Core

• In order to maximize performance and parallelism, the AVR uses a Harvard architecture with separate
memories and buses for program and data.
• Instructions in the program memory are executed with single-level pipelining.
• While one instruction is being executed, the next instruction is pre-fetched from the program memory.
• This concept enables instructions to be executed in every clock cycle.
• The program memory is In-System Reprogrammable Flash memory.
MICROCONTROLLER Study 8 bit microcontroller Applications

Architecture of Atmega 328P : ALU

• The ALU supports arithmetic and logic operations between registers or between a constant and a register.
• Single clock cycle access time allows single-cycle ALU operations. • In a typical ALU operation, two
operands are output from the Register file, the operation is executed and the result is stored back in the
Register file in one clock cycle.
• Single register operations can also be executed in the ALU.
• After an arithmetic operation, the Status register is updated to reflect information about the result of the
operation.
• Program flow is provided by conditional and unconditional jump and call instructions, able to directly
address the whole address space.
• Most AVR instructions have a single 16-bit word format.
• Every program memory address contains a 16- or 32-bit instruction.

AVR General Purpose Register

• The AVR® register file structure is optimized for the AVR Enhanced Reduced Instruction Set Computer
(RISC) instruction set.
• In order to achieve the required performance and flexibility, the following I/O schemes are supported
by the register file:
1. One 8-bit output operand and one 8-bit result input.
2. Two 8-bit output operands and one 8-bit result input.
3. Two 8-bit output operands and one 16-bit result input.
4. One 16-bit output operand and one 16-bit result input.

AVR General Purpose Register

• Most of the instructions operating on the register file have direct access to all registers and most of them
are single cycle instructions.
• Each register is also assigned a data memory address, mapping them directly into the first 32 locations
of the user data space
MICROCONTROLLER Study 8 bit microcontroller Applications

AVR Registers X,Y & Z

• Registers R26 through R31 have some added functions to their general purpose usage.
• These registers are 16-bit address pointers for indirect addressing of the data space.
• The three indirect address registers (X, Y, and Z) are defined as described in the figure.

AVR Status Register

• The status register is an 8-bit register in the microcontroller's I/O memory space.
• It contains 8 flags that are updated based on the results of the previous instruction.

• C : Carry Flag: It indicates a carry in an arithmetic or logic operation.

• Z : Zero Flag: It indicates a zero result in an arithmetic or logic operation.

• N : Negative Flag: The Negative Flag, N, indicates a negative result in an arithmetic or logic operation.

• V : Two's Compliment Overflow Flag: The Two’s Complement Overflow Flag, V, supports two’s
complement arithmetic.

• S : Sign Flag : The S-bit is always an exclusive or between the Negative Flag and the Two’s
Complement Overflow Flag.

• H : Half Carry Flag: It indicates a half carry in some arithmetic operations. It is useful in Binary Code
Decimal (BCD) arithmetic.

• T : Copy Storage: The Bit Copy instructions Bit Load (BLD) and Bit Store (BST) use the T-bit as a
source or destination for the operated bit

• I : Global Interrupt Enable: This bit must be set for the interrupts to be enabled. The individual
interrupt enable control is then performed in separate control registers.
MICROCONTROLLER Study 8 bit microcontroller Applications

AVR Stack Pointer

• The stack is mainly used for storing temporary data, local variables, and return addresses after interrupts
and subroutine calls.
• It is implemented as growing from higher to lower memory locations.
• The Stack Pointer register always points to the top of the stack;
• It points to the data SRAM stack area where the subroutine and interrupt stacks are located.
• The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits
actually used depends on the implementation.

• Stack Instruction Set

• A stack PUSH command will decrease the Stack Pointer.
• The stack in the data SRAM must be defined by the program before any subroutine calls are executed
or interrupts are enabled.
• The initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must
be set to point above the start of the SRAM.
MICROCONTROLLER Study 8 bit microcontroller Applications

AVR Memory Access & Instruction Execution Timing

• The AVR Central Processing Unit (CPU) is driven by the CPU clock clkCPU, directly generated from
the selected clock source for the chip.
• No internal clock division is used.
• Parallel instruction fetches and instruction executions are enabled by the Harvard architecture and the
fast-access register file concept.
• This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique
results for functions per cost, functions per clocks, and functions per power-unit.

• The Parallel Instruction Fetches and Instruction Executions

• In a single clock cycle, an Arithmetic Logic Unit (ALU) operation using two register operands is
executed and the result is stored back to the destination register.

• Single Cycle ALU Operation

MICROCONTROLLER Study 8 bit microcontroller Applications

Atmega 328P Pin Configuration

Pin no Pin name Description Secondary Function

1 PC6 (RESET) Pin6 of PORTC Pin by default is used as RESET pin. PC6 can
only be used as I/O pin when RSTDISBL Fuse
is programmed.
2 PDO (RXD) Pin0 of PORTD RXD (Data Input pin for USART) USART
Serial Communication Interface [Can be used
for programming]
3 PD1 (TXD) Pin1 of PORTD TXD (Data Output Pin for USART) USART
Serial Communication Interface [Can be used
for programming]
INT2 (External Interrupt 2 Input)
4 PD2 (INTO) Pin2 of PORTD External Interrupt Source 0
5 PD3 Pin3 of PORTD External Interrupt Source 1
(INT1/OC2B) OC2B(PWM-Timer/Counter2 Output Compare
Match B Output)
6 PD4(XCK/TO) Pin4 of PORTD TO(Timer0 External Counter Input) XCK
(USART External Clock I/O)
7 VCC Connected to positive voltage
8 GND Connected to ground
9 PB6 Pin6 of PORTB XTAL1 (Chip Clock Oscillator pin 1 or External
(XTAL1/TOSC1) clock input)
TOSC1(Timer Oscillator pin 1)
MICROCONTROLLER Study 8 bit microcontroller Applications

10 PB7 Pin7 of PORTB XTAL2 (Chip Clock Oscillator pin 2)

(XTAL2/TOSC2) TOSC2(Time Oscillator pin 2)
11 PD5 Pin5 of PORTB T1(Time1 External Counter Input)
(T1/OC0B) OC0B (PWM-Timer/Counter0 Output Compare
Match B Output)
12 PD6 Pin6 of PORTD AINO(Analog Comparator Positive I/P)
(AINO/OC0A)
13 PD7 (AIN1) Pin7 of PORTD AIN1(Analog Comparator Negative I/P)
14 PBO Pino of PORTB ICP1(Timer/Counter1 Input Capture Pin)
(ICP1/CLKO) CLKO (Divided System Clock. The divided
system clock can be output on the PBO pin)
15 PB1 (OC1A) Pin1 of PORTB OC1A (Timer/Counter1 Output Compare Match
A Output)
16 PB2 (SS/OC1B) Pin2 of PORTB SS (SPI Slave Select Input). This pin is low
when controller acts as slave.
[Serial Peripheral Interface (SPI) for
programming]
OC1B (Timer/Counter1 Output Compare Match
B Output)
17 PB3 Pin3 of PORTB MOSI (Master Output Slave Input). When
(MOSI/OC2A) controller acts as slave, the data is received by
this pin. [Serial Peripheral Interface (SPI) for
programming]
OC2 (Timer/Counter2 Output Compare Match
Output)
18 PB4 (MISO) Pin4 of PORTB MISO (Master Input Slave Output). When
controller acts as slave, the data is sent to master
by this controller through this pin.
Serial Peripheral Interface (SPI) for
programming]
19 PB5 (SCK) Pin5 of PORTB SCK (SPI Bus Serial Clock). This is the clock
shared between this controller and other system
for accurate data transfer.
[Serial Peripheral Interface (SPI) for
programming]
20 AVCC Power for Internal ADC Converter
21 AREF Analog Reference Pin for ADC
22 GND GROUND
23 PCO (ADCO) Pin of PORTC ADCO (ADC Input Channel 0)
24 PC1 (ADC1) Pin of PORTC ADC1 (ADC Input Channel 1)
25 PC2 (ADC2) Pin of PORTC ADC2 (ADC Input Channel 2)
26 PC3 (ADC3) Pin of PORTC ADC3 (ADC Input Channel 3)
27 PC4 Pin of PORTC ADC4 (ADC Input Channel 4)
(ADC4/SDA) SDA (Two-wire Serial Bus Data Input/output
Line)
28 PC5 (ADC5/SCL) Pin of PORTC ADC5 (ADC Input Channel 5)
SCL (Two-wire Serial Bus Clock Line)
MICROCONTROLLER Study 8 bit microcontroller Applications

ATmega328P Memory Organization

Flash Program Memory

• The ATmega328P contains 32Kbytes On-chip
InSystem Reprogrammable Flash memory for
program storage.
• Since all AVR instructions are 16 or 32 bits
wide, the Flash is organized as 16K x 16.
• For software security, the Flash Program
memory space is divided into two sections, Boot
Loader Section and Application Program section.
• The Flash memory has an endurance of at least
10,000 writes/erase cycles.
• The ATmega328P Program Counter (PC) is 14
bits wide and addresses the 16K program memory
locations.
• The Range of memory address for ATmega328P
Flash Memory is 0x0000 – 0x3FFF.

ATmega328P Memory Organization

SRAM Data Memory
• Data can be accessed through the
standard data bus (Load/Store
Instructions).
• There is a secondary In/Out Bus for
rapid direct access to select locations.
• The ATmega328P is a complex
microcontroller with more peripheral
units than can be supported within the
64 locations reserved in the Opcode for
the IN and OUT instructions.
• For the Extended I/O space from
0x60 – 0xFF in SRAM, only the
ST/STS/STD (Store) and
LD/LDS/LDD (Load) instructions can
be used.
• The IN/OUT data bus has direct
access to the 64- byte I/O Memory
section (not Extended) using a 0x00 to
0x1F address.
• This memory can also be accessed by the standard data bus using a 0x20 address offset in the access
command.
• There are five different data bus addressing modes for the data memory:
1. Direct – The direct addressing reaches the entire data space.
2. Indirect – In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
MICROCONTROLLER Study 8 bit microcontroller Applications

3. Indirect with Displacement – The Indirect with Displacement mode reaches 63 address locations from
the base address given by the Y or Z register.
4. Indirect with Pre-decrement – The address registers X, Y, & Z are decremented
5. Indirect with Post-increment – The address registers X, Y, & Z are incremented

EEPROM Data Memory

• The ATmega328P contains 1Kbytes of data EEPROM memory.
• It is organized as a separate data space, in which single bytes can be read and written.
• The EEPROM has an endurance of at least 100,000 writes/erase cycles.
• The access between the EEPROM and the CPU is performed using the EEPROM Address Registers,
the EEPROM Data Register, and the EEPROM Control Register.
• The EEPROM Access Registers are accessible in the I/O space.

LCD Interfacing AVR (ATmega328P)

• LCDs (Liquid Crystal Displays) are used for displaying status or parameters in embedded systems.
• LCD 16x2 is a 16-pin device that has 8 data pins (D0-D7) and 3 control pins (RS, RW, EN).
• The remaining 5 pins are for the supply and backlight for the LCD.
• The control pins help us configure the LCD in command mode or data mode.
• They also help configure read mode or write mode & also when to read or write.
• LCD 16x2 can be used in 4-bit mode or 8-bit mode depending on the requirement of the application.
• In order to use it we need to send certain commands to the LCD in command mode and once the LCD
is configured according to our need, we can send the required data in data mode.
MICROCONTROLLER Study 8 bit microcontroller Applications

ATmega328P based remote temperature monitoring with

LCD Display
• This circuit is developed using “LM35”, a linear voltage sensor.
• Temperature is usually measured in “Centigrade” or “Faraheite”.
• “LM35” sensor provides output based on scale of centigrade.
• LM35 is three pin transistor like device.
• It has VCC, GND and OUTPUT.
• This sensor provides variable voltage at output based on temperature.
• For every +1 centigrade raise in temperature there will be +10mV higher output.
• So if the temperature is 0◦centigrade the output of sensor will be 0V, if the temperature is 10◦ centigrade
the output of sensor will be +100mV, if the temperature is 25◦ centigrade the output of sensor will be
+250mV.
• So for now with LM35 we get temperature in the form of variable voltage.
• This temperature dependent voltage is given as input to ADC (Analog to Digital Converter) of
ATMEGA32A.
MICROCONTROLLER Study 8 bit microcontroller Applications

89v51 based Clock Using I2C RTC

• I2C : Inner Integrated Circuit
RTC : Real Time Clock

Features of I2C RTC DS12887

• Binary or BCD representation of time, calendar, and alarm
• 12– or 24–hour clock with AM and PM in 12–hour mode
• Daylight Savings Time option • Selectable between Motorola and Intel bus timing
• Multiplex bus for pin efficiency
• Interfaced with software as 128 RAM locations 14 bytes of clock and control registers 114 bytes of
general purpose RAM

Features of I2C RTC DS12887

• Programmable square wave output signal
• Bus–compatible interrupt signals (IRQ)
• Three interrupts are separately software–maskable and testable
⊳ Time–of–day alarm once/second to once/day
⊳ Periodic rates from 122 µs to 500 ms
⊳ End of clock update cyclesssss