Application Specific Integrated Circuit

BEC714A :Credits -3

Text Books:

1. Michael John Sebastian Smith, Application - Specific Integrated Circuits,

Addison-Wesley Professional, 2005.

2. Khosrow Golshan Conexant Systems, Inc. 2007 Springer Science Business

Media “ Physical Design Essentials “ An ASIC Design Implementation
Perspective.
 Module :1

1. Introduction to ASICs:
2. Full custom, Semi-custom and Programmable ASICs,
3. ASIC Design flow,
4. ASIC cell libraries.
5. CMOS Logic: Data path Logic Cells: Data Path Elements,
6. Adders: Carry skip, Carry bypass, Carry save, Carry select, Conditional
sum,
7. Multiplier (Booth encoding),
8. Data path Operators, I/O cells, Cell Compilers.

Text Book 1
Introduction to ASICs
 Integrated Circuits

Die: A rectangular piece of silicon that contains

one IC design
Wafer : A circular piece of pure silicon (10-15 cm in dia);
wafers of 30 cm dia are expected soon)
Wafer Lot: 5-30 wafers, each containing hundreds
of chips (dies) depending upon size of the die

Mask Layers: Each IC is manufactured with successive

mask layers(10 - 15 layers)
❖ First half-dozen or so layers define transistors
❖ Other half-dozen define Interconnect
 Module :1

a. A pin-grid array (PGA) package

b. The silicon die or chip is under the
package
 Levels of Integration

Levels of Integration Number of Gates per Chip Year evels of Integration

Small Scale Integration (SSI) ~10 gates per chip 1960’s Small Scale Integration (SSI)
Medium Scale Integration (MSI) ~100–1000 gates per chip 1970’s Medium Scale Integration (MSI)
Large Scale Integration (LSI) ~1000–10,000 gates per chip 1980’s Large Scale Integration (LSI)
~10,000–100,000 gates per Very Large Scale Integration
Very Large Scale Integration (VLSI) 1990’s
chip (VLSI)
2000
Ultra Large Scale Integration
Ultra Large Scale Integration (ULSI) ~1M–10M gates per chip and
(ULSI)
above
evels of Integration Number of Gates per Chip Year evels of Integration
 ASIC and Non ASIC

Examples of ICs that are not ASICs include standard parts such as:
 Memory chips
 ROMs, DRAM, and SRAM;
microprocessors;
 TTL or TTL-equivalent ICs at SSI, MSI, and LSI levels.

Examples of ICs that are ASICs include:

 a chip for a toy bear that talks;
 a chip for a satellite;
 a chip designed to handle the interface between memory and a
microprocessor for a workstation CPU;
 a chip containing a microprocessor as a cell together with
other logic.
 Application Specific Standard Products (ASSP)

ASSP (two ICs that might or might not be considered ASICs )

 Controller chip for a PC
 A chip for a modem.

Both of these examples are specific to an application (shades of an ASIC)

but are sold to many different system vendors (shades of a standard part).
ASICs such as these are sometimes called application-specific standard
products ( ASSPs ).
// A simple Verilog module for an inverter
module inverter ( input wire a, output wire b );
assign b = ~a;
endmodule

// Synthesized netlist for the 'inverter' module

module inverter ( input a, output b );
INV X1 (.I(a), .Z(b));
endmodule
• // A simple Verilog module for an inverter
module inverter ( input wire a, output wire b );
assign b = ~a;
endmodule

// Synthesized netlist for the 'inverter' module

module inverter ( input a, output b );
INV X1 (.I(a), .Z(b));
endmodule
Types of ASIC
 Full-Custom ASICs

Include some (possibly all) customized logic cells

 Have all their mask layers customized
 Manufacturing lead time is typically 8 weeks (time taken to make the
IC does not include design time)

Full-custom ASIC design makes sense only

1. When no suitable existing libraries exist or
2. Existing library cells are not fast enough or
3. The available pre-designed/pre-tested cells consume too much power
that a design can allow or
4. The available logic cells are not compact enough to fit or
5. ASIC technology is new or/and so special that no cell library exits.
Advantages:
 Offer highest performance
 lowest cost (smallest die size)
Disadvantages
 Increased design time
 Increased Complexity
 Higher design cost
 Higher risk.

Some Examples:
 Microporcessor
 High-Voltage Automobile Control Chips
 Ana-Digi Communication Chips
 Sensors and Actuators
 Semi-Custom ASICs

Manufacturing lead time is about 8 weeks

Custom blocks can be embedded

Standard-Cell based ASICs (CBIC- “sea-bick”)

 Use predesigned logic cells (Called standard cells) from standard cell
libraries
 other mega-cells (Microcontroller or Microprocessors)
full-custom blocks
System-Level Macros(SLMs)
Functional Standard Blocks (FSBs)
 Standard-Cell based ASIC Design
• A cell-based ASIC (cell-based IC, or CBIC—a common term in Japan,
pronounced "sea-bick") uses predesigned logic cells (AND gales, OR gates,
multiplexers, and flip-flops, for example) known as standard cells.

• The standard-cell areas may be used in combination with larger predesigned

cells, perhaps microcontrollers or even micro- processors, known as megacells.
Megacells are also called megafunctions, full- custom blocks, system-level
macros (SLMs), fixed blocks, cores, or Functional Standard Blocks (FSBs).

• The advantage of CBICs is that designers save time, money, and reduce risk by
using a
• predesigned,
• pretested, and
• precharacterized standard-cell library.

• The disadvantages are

• the time or
• expense of designing or buying the standard-cell library and
• the time needed to fabricate all layers of the ASIC for each new design.
 Standard-Cell based ASIC Design cont…
FIGURE 1.2 A cell-based ASIC (CBIC) die
with
• a single standard-cell area (a flexible
block) together with
• four fixed blocks.
• The flexible block contains rows of
standard cells.
• The small squares around the edge of the
die are bonding pads that are connected to
the pins of the ASIC package.

Each standard cell in the library is constructed using full-custom design methods, but you
can use these predesigned and pre characterized circuits without having to do any full-
custom design yourself.

This design style gives you the same performance and flexibility advantages of a full-
custom ASIC but reduces design time and reduces risk.
FIGURE 1A Routing the CBIC (cell-based IC)
 Gate based ASIC Design

In gate array based ASIC the transistors are

pre-defined on a silicon wafer. Only the
metal interconnect layers are customized.
The base layers, which contain the transistors
and other primitive components, are pre-
fabricated and fixed. It often called Masked
Gate Array (MGA) The designer's task is to
define the wiring that connects these existing
components to create the desired circuit. The
smallest element is the base cell also called
primitive cell.

There are the following different types of MGA or gate-array-based ASICs:

• Channeled gate arrays.

• Channelless gate arrays.
• Structured gate arrays.
 Channeled Gate Array based ASIC Design

A channeled gale array is similar to a CBIC—both use rows of cells separated by

channels used for interconnect. One difference is that the space for interconnect
between rows of cells are fixed in height in a channeled gate array, whereas the space
between rows of cells may be adjusted in a CBIC.
 Channelless Gate Array based ASIC Design
Figure 1.6 shows a channelless gale array (also known as
a channel-free gate array, sea-of-gates array, or SOG
array).

The important features of this type of MGA are as

follows:
• Only some (the top few) mask layers are customized—
the interconnect.
• Manufacturing lead time is between two days and two
weeks.

• The key difference between a channelless gate array and channeled gate array is that there are
no predefined areas set aside for routing between cells on a channelless gate array.

• Instead we route over the top of the gate-array devices.

• We can do this because we customize the contact layer that defines the connections between
metal 1, the first layer of metal, and the transistors. When we use an area of transistors for
routing in a channelless array, we do not make any contacts to the devices lying underneath; we
simply leave the transistors unused.
 Structured Gate Arraybased ASIC Design
• An embedded gate array or structured gate array (also known
as masterslice or master image) combines some of the Specific
features of CBlCs and MGAs. function
• One of the disadvantages of the MGA is the fixed gate-array
base cell. This makes the implementation of memory,
difficult and inefficient.
• In an embedded gate array we set aside some of the IC area
and dedicate it to a specific function. This embedded area
either can contain a different base cell that is more suitable
for building memory cells, or it can contain a complete
circuit block, such as a microcontroller.
Figure shows an embedded gate array. The important features of this type of MGA are the
following:
• Only the interconnect is customized.
• Custom blocks (the same for each design) can be embedded.
• Manufacturing lead time is between two days and two weeks.
• An embedded gate array gives the improved area efficiency and increased performance of a
CBIC but with the lower cost and faster turnaround of an MGA.
• One disadvantage of an embedded gate array is that the embedded function is fixed
 Programmable logic devices (PLDs)
Programmable logic devices (PLDs) are standard ICs that are
available in standard configurations and are sold in very high
volume to many different customers. The following important
features that all PLDs have in common:

• No customized mask layers or logic cells

• Fast design turnaround
• A single large block of programmable interconnect
• A matrix of logic macrocells that usually consist of
programmable array logic followed by a flip-flop or latch.
• The simplest type of programmable IC is a read-only
memory (ROM). The most common types of ROM use a
metal fuse that can be blown permanently (a programmable
ROM or PROM). An electrically programmable ROM, or
EPROM

Depending on how the PLD is programmed, we can have an erasable PLD (EPLD), or mask-
programmed PLD (sometimes called a masked PLD but usually just PLD). The first PALs, PLAs,
and PLDs were based on bipolar technology and used programmable fuses or links. CMOS PLDs
usually employ floating-gate transistors.
 Field-Programmable Gate Arrays
A step above the PLD in complexity is the field-
programmable gale array (FPGA). There is very
little difference between an FPGA and a PLD. An
FPGA is usually just larger and more complex than
a PLD. FPGAs are the newest member of the ASIC
family and are rapidly growing in importance,
replacing TTL in microelectronic systems. Even
though an FPGA is a type of gate array, we do
not consider the term gate-array-based ASICs.

Figure 1.9 illustrates the essential characteristics of an FPGA:

• None of the mask layers are customized.

• A method for programming the basic logic cells and the interconnect.
• The core is a regular array of programmable basic logic cells that can implement combinational
as well as sequential logic (flip-flops).
• A matrix of programmable interconnect surrounds the basic logic cells.
• Programmable I/O cells surround the core.
• Design turnaround is a few hours.
 ASIC Cell Libraries

You can:
(1) use a design kit from the ASIC vendor along with
libraries
(2) buy an library from a library vendor which is compatible
to design kit.
(3) you can build your own cell library
 ASIC Cell Libraries

GPDK: Generic Process Design Kit. US based company called

Sky Water (180nm, 90nm, 45nm)
PDK: Process Design Kit. US based company called Sky Water
(180nm, 90nm, 45nm)
Cannot fabricate the chip
TSMC : Taiwan Semiconductor Manufacturing Company
Limited 180nm, 90nm)
Can fabricate the circuit as chip
UMC: Unified microelectronic corporation, Singapore based
company, Can fabricate the circuit as chip
 Summary

In each chapter we shall indicate the key concepts. In this chapter they are
• The difference between full-custom and semicustom ASICs
• The difference between standard-cell, gate-array, and programmable ASICs
• The ASIC design flow
• Design economics including part cost, NRE, and breakeven volume
• The contents and use of an ASIC cell library
CMOS LOGIC
CMOS Transistors
Input and Output characteristics
Input and Output characteristics
Combinational Logic Cells

?
Example
Bubble Pushing
 Datapath Elements

Figure shows some typical datapath symbols for an

adder (people rarely use the IEEE standards in ASIC
datapath libraries.

• Bus A[31:0] denotes a 32-bit bus

• A[31] as most-significant bit or MSB , and A[0] as the least-
significant bit or L SB
• Notice that if we have an n -bit bus and L SB = 0, then MSB =
n -1
Datapath layout automatically takes care of most of the interconnect
between the cells with the following advantages:
• Regular layout produces predictable and equal delay for each bit.
• Interconnect between cells can be built into each cell.
There are some disadvantages of using a datapath:
• The overhead (buffering and routing the control signals, for example) can
make a narrow (small number of bits) datapath larger and slower than a
standard-cell (or even gate-array) implementation.
• Datapath cells have to be predesigned (otherwise we are using full-
custom design) for use in a wide range of datapath sizes. Datapath cell
design can be harder than designing gate-array macros or standard cells.
• Software to assemble a datapath is more complex and not as widely
used as software for assembling standard cells or gate arrays.
FIGURE 2.20 A datapath adder, (a) A full-adder (FA) cell with inputs (A and
B), a carry in, CIN, sum output, S, and cany out, COUT. (b) A 4-bit adder,
(c) The layout, using two-level metal, with data in m1 and control in m2. In
this example the wiring is completed outside the cell; it is also possible to
design the datapath cells to contain the wiring. Using three levels of metal,
it is possible to wire over the top of the datapath cells, (d) The datapath
layout.
Carry Skip Adder or Carry Bypass Adder
BP= P0.P1.P2.P3
Carry Save Adder
Carry Select Adder
multiplier

• symmetric 6-bit array multiplier