5 4 3 2 1

[4]
LP_D0_P_RX
R1
[2] 50
[4]
DPHY_D0_P_RX
D HS_D0_P_RX D
[2]
[4]
DPHY_D0_N_RX
HS_D0_N_RX
R2
50
[4]
LP_D0_N_RX

[4]
LP_D1_P_RX
[4]
R3
LP_CLK0_P_RX
[2] 50
R4 [4]
50 DPHY_D1_P_RX
[2] HS_D1_P_RX
[4] [2]
DPHY_CLK0_P_RX
HS_CLK0_P_RX [4]
DPHY_D1_N_RX
[2] HS_D1_N_RX
[4]
DPHY_CLK0_N_RX R5
HS_CLK0_N_RX
50
R6 [4]
C 50 LP_D1_N_RX C
[4]
LP_CLK0_N_RX [4]
LP_D2_P_RX
[4]
R7
LP_CLK1_P_RX
[2] 50
R8 [4]
50 DPHY_D2_P_RX
[2] HS_D2_P_RX
[4] [2]
DPHY_CLK1_P_RX
HS_CLK1_P_RX [4]
DPHY_D2_N_RX
[2] HS_D2_N_RX
[4]
DPHY_CLK1_N_RX R9
HS_CLK1_N_RX
50
R10 [4]
50 LP_D2_N_RX
[4]
LP_CLK1_N_RX [4]
LP_D3_P_RX
R11
[2] 50
[4]
B DPHY_D3_P_RX B
HS_D3_P_RX
[2]
[4]
DPHY_D3_N_RX
HS_D3_N_RX
R12
50
[4]
LP_D3_N_RX

Place resistor networks as close to Bank 0 pins as possible and trace match all diff signals between P and N as well as between pairs

LP_* Signals are only needed if you intend on monitoring LP signals from within the FPGA. If monitoring LP signals from within the
FPGA is not needed 100 ohm parallel termination can be used in place of the resistor network for those pairs. It is recommended to
use the 50 ohm resistor network on at least the clock lanes and data lane 0 for DSI. For CSI-2 100ohm termination is sufficient
A
for all data and clock lanes in most cases. A

Title
XO2 DPHY RX Resistor Networks MIPI XO2 Schematic Example

Size Document Number Rev

B <Doc> 1

Date: Friday, September 20, 2013 Sheet 1 of 5

5 4 3 2 1
 5 4 3 2 1

[5]
LP_D0_P_TX

R13
[5] 50
HS_D0_P_TX R14 320
DPHY_D0_P_TX [7]

D [5] D
HS_D0_N_TX
R15 320 [7]
DPHY_D0_N_TX
R16
[5] 50
LP_D0_N_TX
[5] [5]
LP_CLK0_P_TX LP_D1_P_TX

R17 R18
[5] 50 [5] 50
HS_CLK0_P_TX R19 320 HS_D1_P_TX R20 320
DPHY_CLK0_P_TX [7] DPHY_D1_P_TX [7]

[5] [5]
HS_CLK0_N_TX R21 320 HS_D1_N_TX R22 320
DPHY_CLK0_N_TX [7] DPHY_D1_N_TX [7]
R23 R24
[5] 50 [5] 50
C C
LP_CLK0_N_TX LP_D1_N_TX
[5] [5]
LP_CLK1_P_TX LP_D2_P_TX

R25 R26
[5] 50 [5] 50
HS_CLK1_P_TX R27 320 HS_D2_P_TX R28 320
DPHY_CLK1_P_TX [7] DPHY_D2_P_TX [7]

[5] [5]
HS_CLK1_N_TX R29 320 HS_D2_N_TX R30 320
DPHY_CLK1_N_TX [7] DPHY_D2_N_TX [7]
R31 R32
[5] 50 [5] 50
LP_CLK1_N_TX LP_D2_N_TX
[5]
LP_D3_P_TX

B R33 B
[5] 50
HS_D3_P_TX R34 320
DPHY_D3_P_TX [7]

[5]
HS_D3_N_TX R35 320
DPHY_D3_N_TX [7]
R36
[5] 50
LP_D3_N_TX

Place resistor networks as close to Bank 0 pins as possible and trace match all diff signals between P and N as well as between pairs
If LP mode is not needed the LP_* signals can be removed with the 50ohm resistors connected to ground
A A

Title
XO2 DSI TX Resistor Networks MIPI XO2 Schematic Example

Size Document Number Rev

B <Doc> 1

Date: Friday, September 20, 2013 Sheet 2 of 5

5 4 3 2 1
 5 4 3 2 1

V2P5
V2P5

C1 C2 C3 C4
C5 C6 C7 C8

1UF

100NF

100NF

100NF

1UF

100NF

100NF

100NF
D D

U1C U1A

10V

10V

10V

10V

10V

10V

10V

10V
V2P5 V2P5
MACHX02-4000 MACHX02-4000
GND BANK 2 BANK 0
M6 GND A8
N11 VCCIO2_1 B10 VCCIO0_1
P1 VCCIO2_2 C5 VCCIO0_2
VCCIO2_3 VCCIO0_3
[3]
HS_D2_P_RX P2 A2
[3] PB3A_T [6] HS_D1_P_TX PT9A_T_LVDS
HS_D2_N_RX N2 B3
PB3B_C [6] HS_D1_N_TX PT9B_C_LVDS
P3 [6] HS_CLK1_P_TX A3
M3 CSSPIN_PB4A_T C4 PT11A_T_LVDS
PB4B_C [6] HS_CLK1_N_TX PT11B_C_LVDS
[3]
HS_D3_P_RX N3 B5
[3] PB7A_T [6] HS_D0_P_TX PT14A_T_LVDS
HS_D3_N_RX P4 C6
PB7B_C [6] HS_D0_N_TX PT14B_C_LVDS
M4 [6] HS_CLK0_P_TX A7
N4 MCLK_CCLK_PB9A_T B7 PT18A_PCLKT0_1_T_LVDS
SO_SPISO_PB9B_C [6] HS_CLK0_N_TX PT18B_PCLKC0_1_C_LVDS
N5 C9
C PB10A_T PT21A_T_LVDS C
M5 A9
PB10B_C PT21B_C_LVDS
[3]
HS_CLK0_P_RX N6 A10
[3] PB13A_PCLKT2_0_T [6] HS_D2_P_TX PT24A_T_LVDS
HS_CLK0_N_RX P6 C11
PB13B_PCLKC2_0_C [6] HS_D2_N_TX PT24B_C_LVDS
P7 A11
N7 PB15A_T B12 PT25A_T_LVDS
PB15B_C PT25B_C_LVDS
[3]
HS_CLK1_P_RX M7 C12
[3] PB20A_PCLKT2_1_T [6] HS_D3_P_TX PT27A_T_LVDS
HS_CLK1_N_RX N8 A12
PB20B_PCLKC2_1_C [6] HS_D3_N_TX PT27B_C_LVDS
[3]
HS_D1_P_RX P8
[3] PB21A_T
HS_D1_N_RX M8 B9
PB21B_C C10 JTAGENB_PT23C_T
P9 PROGRAMN_PT23D_C
N9 PB23A_T B13
PB23B_C A13 INITN_PT28C_T
M9 DONE_PT28D_C
N10 PB24A_T C8
PB24B_C B8 SCL_PCLKT0_0_PT20C_T
M10 SDA_PCLKC0_0_PT20D_C
P11 PB27A_T
PB27B_C
[3]
B HS_D0_P_RX M11 MachXO2-4000 HE 132csbga B
[3] PB29A_T
HS_D0_N_RX P12
PB29B_C
N12
P13 SN_PB30A_T
SI_SISPI_PB30B_C HS_* signals must be trace length matched
MachXO2-4000 HE 132csbga
between P and N of a pair as well as
between the individual pairs
HS_* signals must be trace length matched
between P and N of a pair as well as
between the individual pairs

XO2 MIPI HS TX Signals

A A

XO2 MIPI HS RX Signals Title

MIPI XO2 Schematic Example

Size Document Number Rev

B <Doc> 1

Date: Friday, September 20, 2013 Sheet 3 of 5

5 4 3 2 1
 5 4 3 2 1

V1P2
V1P8 U1D
D D
MACHX02-4000
V1P8 C13 C14 C15 C16
C9 C10 C11 C12
BANK 3
U1B

1UF

100NF

100NF

100NF
L1
VCCIO3
1UF

100NF

100NF

100NF
V1P2
J3 MACHX02-4000
K2 PL16A_T
PL16B_C BANK 1
D14
VCCIO1_1

10V

10V

10V

10V
K1 H14
PL17A_PCLKT3_0_T VCCIO1_2
10V

10V

10V

10V
K3 L12
PL17B_PCLKC3_0_C VCCIO1_3
L3 GND B14
GND PL19B_C C13 PR2A_R_GPLLT_FB_DQ0_T
M1 PR2B_R_GPLLC_FB_DQ0_C
M2 PL20A_T C14
PL20B_C [6] LP_CLK1_P_TX PR3A_R_GPLLT_IN_DQ0_T
V1P8 [6] LP_CLK1_N_TX D12
PR3B_R_GPLLC_IN_DQ0_C
MachXO2-4000 HE 132csbga [6] LP_CLK0_P_TX E12
E14 PR5A_DQ0_T
U1E [6] LP_CLK0_N_TX PR5B_DQ0_C
C17 C18 C19 C20
E13
MACHX02-4000 [6] LP_D0_P_TX PR6A_DQ0_T
1UF

100NF

100NF

100NF

V1P8 [6] LP_D0_N_TX F12

PR6B_DQ0_C
C BANK 4 C
G1 [6] LP_D1_P_TX F13
VCCIO4 F14 PR8A_DQ0_T
[6] LP_D1_N_TX PR8B_DQ0_C
F1
PL9A_T
10V

10V

10V

10V

F3 [6] LP_D2_P_TX G12

PL9B_C G14 PR9A_DQS0_T
[6] LP_D2_N_TX PR9B_DQS0N_C
G3
GND H2 PL10C_PCLKT4_0_T G13
PL10D_PCLKC4_0_C [6] LP_D3_P_TX PR10A_PCLKT1_0_DQ0_T
[6] LP_D3_N_TX H12
V1P8 H1 PR10B_PCLKC1_0_DQ0_C
H3 PL13A_T J12
PL13B_C [3] LP_CLK1_P_RX PR13A_DQS1_T
[3] LP_CLK1_N_RX J14
J1 PR13B_DQS1N_C
C21 C22 C23 C24 J2 PL14A_T J13
PL14B_C [3] LP_CLK0_P_RX PR14A_DQ1_T
[3] LP_CLK0_N_RX K12
PR14B_DQ1_C
1UF

100NF

100NF

100NF

MachXO2-4000 HE 132csbga [3] LP_D0_P_RX K13

K14 PR15A_DQ1_T
U1F [3] LP_D0_N_RX PR15B_DQ1_C
[3] LP_D1_P_RX L14
MACHX02-4000 PR16A_DQ1_T
10V

10V

10V

10V

V1P8 [3] LP_D1_N_RX M13

PR16B_DQ1_C
BANK 5
D3 [3] LP_D2_P_RX M12
GND VCCIO5 M14 PR18A_DQ1_T
[3] LP_D2_N_RX PR18B_DQ1_C
B B1 B
B2 PL3A_L_GPLLT_FB_T N13
PL3B_L_GPLLC_FB_C [3] LP_D3_P_RX PR19A_DQ1_T
[3] LP_D3_N_RX N14
C1 PR19B_DQ1_C
C3 PL4A_L_GPLLT_IN_T
PL4B_L_GPLLC_IN_C
C2 MachXO2-4000 HE 132csbga
D1 PL6A_PCLKT5_0_T
PL6B_PCLKC5_0_C
E1
E2 PL7A_T
PL7B_C
E3
F2 PL8A_T
PL8B_C

MachXO2-4000 HE 132csbga

For XO2-1200 compatibility, VCCIO3 = VCCIO4 = VCCIO5 XO2 MIPI LP RX and TX Signals
A A

Extra Banks
Title
MIPI XO2 Schematic Example

Size Document Number Rev

B <Doc> 1

Date: Friday, September 20, 2013 Sheet 4 of 5

5 4 3 2 1
 5 4 3 2 1

V2P5 TP1 V2P5 V1P8

V1P2

2
R37 1
LED1 LED2
1R TP_LOOP_RED PART_NUMBER = HSMG-C190 PART_NUMBER = HSMH-C190
LED Manufacturer = AVAGO LED Manufacturer = AVAGO
D D
C25 C26 U2 LTC3025

1
1
LTC3025 V1P2
100nF 3 4

BIAS
IN OUT R40 R41
10uF/6V3/X7R C27 R39 180 180
GND GND R38 R0603 R0603
20K 10uF/6V3/X7R DNI 1% 1%

PWP
GND
V1P8 R42 6 5 R0402
EN ADJ GND GND
100K GND GND

2
7
C28 R43
1ms RC 10_0K
0.01uF R0402

GND GND V1P2

GND
U1G
Vout = 0.4*(1+R44/R46) = 1.200V
MACHX02-4000 V1P2 C29 C30 C31 C32
Power

1UF

100NF

100NF

100NF
A5 A1
B11 GND1 VCC1 A14
D2 GND2 VCC2 N1
C GND3 VCC3 C
D13 P14
G2 GND4 VCC4
GND5

10V

10V

10V

10V
H13
L2 GND6
L13 GND7
P5 GND8 GND
P10 GND9 C7
GND10 NC

GND
MachXO2-4000 HE 132csbga

Core Voltage

V1P8 U1H
B B
MACHX02-4000
R44 R45 R46 JTAG
4.7k 4.7k 4.7k
J1 B6
V1P8 TCK_TEST_CLK_PT15C_T
1 2 B4
VCC TDO
3 TDI_PT13D_C
TDI
4 A4
ispEN_N
5 TDO_PT13C_T
NC
C33 6 A6
100nF
TMS
8 TMS_PT15D_C
TCK
DONE
9
7 10
GND INITN

DNI
GND MachXO2-4000 HE 132csbga
JTAG Header R47
1k

GND
A A

JTAG Title
MIPI XO2 Schematic Example

Size Document Number Rev

B <Doc> 1

Date: Friday, September 20, 2013 Sheet 5 of 5

5 4 3 2 1