MODULE 4 : FAULTS
Prepared By
Dr. Aswathy Madhu
Contents
◦ Faults
◦ Fault table method
◦ Path sensitization method
◦ Boolean difference method
◦ Kohavi algorithm
◦ Automatic test pattern generation
◦ Built in Self Test (BIST)
2
Faults
◦ A fault is defined as the physical defect of one or more
components of a circuit.
◦ For example, a short between two signal lines in the
circuit or a break in a signal line is a physical defect
(fault).
◦ An error is usually the manifestation of a fault in the
circuit; thus, a fault may change the value of a signal in a
circuit from 0 (correct) to 1 (erroneous) or vice versa.
◦ However, a fault does not always cause an error; in that
case, the fault is considered to be latent.
3
Contd…
◦ A fault is characterized by its nature, value, extent, and
duration.
◦ The nature of a fault can be classified as logical or
nonlogical.
◦ A logical fault causes the logic value at a point in a circuit
to become opposite to the specified value.
◦ Nonlogical faults include the rest of the faults such as
the malfunction of the clock signal, power failure, etc.
4
Contd…
◦ The value of a logical fault at a point in the circuit
indicates whether the fault creates fixed or varying
erroneous logical values.
◦ The extent of a fault specifies whether the
effect of the fault is localized or distributed.
◦ A local fault affects only a single variable, whereas a
distributed fault affects more than one.
◦ A logical fault, for example, is a local fault, whereas the
malfunction of the clock is a distributed fault.
5
Contd…
◦ The duration of a fault refers to whether the fault is
permanent or temporary.
◦ Permanent fault changes the functional behaviour of the
circuit permanently.
◦ It happens mostly due to physical fault (eg. wrong
connection in ICs, PCB heating.
◦ Temporary fault happens at random moments and affects
the circuit behaviour for a random period of time.
◦ It is comparatively difficult to detect.
6
Contd…
◦ Temporary faults are of two types:
◦ Transient faults: It is caused by environmental conditions
such as humidity, pressure, vibrations etc.
◦ Intermittent faults: It is caused by non environmental
conditions such as loose connections, ageing of
components etc.
7
Fault Models
◦ To combat the challenges of faults, and to ensure the
reliability of digital circuits, fault models are used.
◦ These models are critical for simulating potential defects
and creating test patterns to detect and address faulty
circuits efficiently.
◦ A fault model is used to describe the change in the logic
function of a device caused by the defect.
◦ Fault models can be constructed at various levels of
abstraction.
8
Contd…
9
Contd…
◦ High level fault models have no knowledge about the
actual gate-level representation of the circuit. Hence,
they are not very effective in detecting manufacturing
defects.
◦ Transistor level fault models are more accurate than logic
level fault models. But, the complexity of handling all
transistor-level faults can be huge.
◦ Hence, logic level (structural) fault models are commonly
used.
10
Stuck-at Fault model
◦ The most fundamental and widely used fault model is the
stuck-at fault.
◦ This model assumes a single fault in a circuit that forces
a particular net (wire) to be stuck at either a logic 0 or a
logic 1, regardless of the intended signal.
◦ The single stuck-at fault model is often referred to as
the classical fault model and offers a good
representation for the most common types of
defects [e.g., shorts and opens in complementary
metal oxide semiconductor (CMOS) technology].
11
Contd…
◦ Stuck-at faults can be further categorized as:
◦ Stuck-at-0 (SA0): The net is permanently stuck at logic 0.
◦ Stuck-at-1 (SA1): The net is permanently stuck at logic 1.
◦ An input or output can be stuck at 0 or stuck at 1.
◦ Stuck-at faults are popular because they are relatively
simple to model and test for.
◦ To detect stuck at faults, we generate specific test
vectors (combinations of input signals).
12
Contd…
◦ Example: Assume that in Fig, the A input of the NAND
gate is s-a-1.
◦ i.e., The NAND gate perceives the A input as a logic 1
irrespective of the logic value placed on the input.
13
Contd…
◦ We have to generate a test vector that can successfully
identify the fault.
◦ For the simple NAND gate, test vector can be generated
by inspection.
◦ Consider AB=01, for a fault-free NAND, the output is 1.
But, with SA1 fault at A, if we give AB=01, the output will
be 0.
◦ Thus, AB=01 can be considered as the test for the A
input SA1, since there is a difference between the output
of the fault-free and faulty gate.
14
Methods for Fault Detection
◦ There are four systematic methods for stuck-at fault
detection.
◦ Fault table method
◦ Path sensitization method
◦ Boolean Difference
◦ Kohavi algorithm
15
Fault table method
◦ Consider the circuit shown in figure.
◦ Step 1: Name the terminals A, B, C, D
16
Contd…
◦ Step 2: Make the table
17
Contd…
◦ Step 3: Identify equivalent faults
◦ Here, a, b, and c stuck at 0 yields same output for all
input combinations. So, they are indistinguishable or
equivalent faults.
◦ Similarly, c and d stuck at 1 yields same output for all
input combinations. So, they are equivalent faults.
◦ Dominant and weak fault: When SA0 fault occurs at the
input of the AND gate, it forces the output of the AND
gate to zero irrespective of the other input. Hence SA0
fault at the input of the AND gate is a dominant (strong)
fault. 18
Contd…
◦ However, SA1 fault at one of the inputs of AND gate
alone cannot force the output of AND gate to 1. Hence,
SA1 fault at the input of AND gate is a weak fault.
◦ For the OR gate, SA0 fault is the weak fault and SA1
fault is the strong fault.
◦ Step 4: Make fault cover table from the fault table.
◦ By observing the first row of the fault table, we can see
that, SA1 fault on b, c, and d produces an output that is
different from the fault free output. Hence these faults
can be identified by giving 000 as a test vector.
19
Contd…
20
Contd…
◦ Step 5: Identify essential test vectors.
◦ Essential test vectors: If a fault is detected by one and
only one test vector, it is an essential test vector.
◦ Identify the columns with single ‘x’ in the fault cover
table. The input combination corresponding to that ‘x’ is
an essential test vector.
◦ In the above example, 000, 010, and 110 are essential test
vectors (ETV).
21
Contd…
◦ Selective test vectors: In this problem, 001, or 101, or 111
are the selective test vectors (STV). Here, only d0 needs
to be covered.
◦ Redundant test vectors: The faults covered by this test
vector is covered by other ETVs. In this problem, 100 is a
redundant test vector (RTV) since it covers c1d1 fault
which is already covered by 000.
◦ Step 6: Identify the minimum test set.
◦ Here, the minimum test set is {000, 010, 110, (001, or 101,
or 111)}
22
Contd…
◦ Selective test vectors: In this problem, 001, or 101, or 111
are the selective test vectors (STV). Here, only d0 needs
to be covered.
◦ Redundant test vectors: The faults covered by this test
vector is covered by other ETVs. In this problem, 100 is a
redundant test vector (RTV) since it covers c1d1 fault
which is already covered by 000.
◦ Step 6: Identify the minimum test set.
◦ Here, the minimum test set is {000, 010, 110, (001, or 101,
or 111)}
23
Fault Table Method - Homework
◦ Illustrate the principles involved in test vector generation
by fault table method using the following circuit.
24
Path Sensitization
◦ The basic principle of path sensitization method is to
choose some path from the origin of the fault to the
circuit output.
◦ A path is sensitized if the inputs to the gates along the
path are assigned values such that the effect of the fault
can be propagated to the output.
◦ To illustrate this, consider the following digital circuit
with line α stuck at 1.
25
Contd…
◦ To test for α both G3 and C must be set to 1. In addition,
D and G6 must be set to 1 so that G7 = 1 if the fault is
absent.
◦ To propagate fault to the circuit output f through G8, G4
must be 1.
◦ The process of propagating the effect of the fault from
its original location to the circuit output is known as the
forward trace. 26
Contd…
◦ The next phase of the method is the backward trace , in
which the necessary signal values at the gate outputs
specified in the forward trace phase are established.
◦ For example, to set G3 at 1, A must be 0, which also sets
G4. In order for G6 to be at 1, B must be set at 0. This is
because C has been set to 1 in the forward trace.
◦ Therefore, the test ABCD = 0011 detects the fault SA1
at α, since the output f will be 0 for the fault-free circuit
and 1 in the presence of the fault. 27
Path Sensitization - Example
◦ Using path sensitization, find the test set for the fault
SA1 at g in the following circuit.
28
Contd…
◦ Forward Trace: To test for SA1 at g, c must be set to 1.
Also, f must be set to 0 so that i = 0 in the fault free
condition.
◦ To propagate the fault to j, h should be set to 1.
◦ Backward Trace: To set f at 0, a and b can be 00, 01, or
10. To set h at 1, d and e must be set to 0.
◦ Test vectors: (00100), or (01100), or (10100)
29
Contd…
◦ From this example, it is clear that the test pattern
generated by the path sensitization method may not be
unique.
◦ However, the main drawback of the path sensitization
method is that only one path is sensitized at a time. This
does not guarantee that a test will be found for a fault
even if one exists.
◦ To illustrate this, consider the following digital circuit
with a fault SA0 at G1.
30
Contd…
◦ Fault Activation: To test for SA0 at G1, set a=b=1.
◦ Fault Propagation: The fault at G1 can propagate through
either G3-G6 or G4-G6. In single path sensitization, it is
assumed that fault propagates through a single path at a
time.
◦ Choose path G3-G6. So, the fault at G1 affects only the
input of G3, not G4.
31
Contd…
◦ Hence, G4=1 means e=0. But this will make G5=0 Fault
cannot propagate.
◦ Choose another path G4-G6; G2=G3=G5=1 for fault
propagation. G3=1c=0G2=0 Fault cannot propagate.
◦ Similarly, G2-G6 and G5-G6 also cannot be sensitized.
◦ Thus, single path sensitization may fail to generate a test
pattern.
32
Path Sensitization - Homework
Using path sensitization technique, find the test set
for the following faults.
(i) SA0 at x3 (ii) SA1 at x3 (iii) SA0 at g (iv) SA1 at g
33
Boolean Difference Method
◦ It is a deterministic method to find the test vectors.
◦ It gives all possible test vectors.
◦ The Boolean difference of a function f with respect to a
variable x, denoted as ∂f , represents the change in f
∂x
when x changes from 0 to 1.
∂f
◦ Mathematically, it is defined as: =f(x=1)⊕f(x=0).
∂x
34
Contd…
◦ To detect a stuck-at-0 fault at a node y, we compute the
Boolean difference of the fault-free circuit's output f
with respect to y.
◦ If the result is 1, it indicates that a change in y from 0 to
1 will alter the output, making the fault detectable.
◦ For example, Consider a simple function f=x⋅y+z. To
detect a stuck-at-0 fault at node y:
35
Contd…
◦ Step 1: Compute the Boolean difference
∂f
=(x⋅1+z)⊕(x⋅0+z)=(x+z)⊕z=x⊕z
∂y
∂f
◦ Step 2: Generate test vectors y. =1 i.e., y.(x⊕z) =1
∂y
◦ Test set: T = x’ y z + x y z’ = {011,110}
36
Boolean Difference – Example 1
◦ Find the test vector to test faults (i) SA0 at node y and
(ii) SA1 at node y using Boolean difference method.
f = x y + y’ z
37
Contd…
◦ Step 1: Compute the Boolean difference
∂f
=(x⋅1+0.z)⊕(x⋅0+1.z)=x⊕z
∂y
◦ Step 2: Generate test vectors to detect SA0 at y by
∂f
setting y. =1. i.e., y x’ z + y x z’ = 1
∂y
◦ Test set for detecting SA0 at y: T = {011, 110}
38
Contd…
◦ Step 3: Generate test vectors to detect SA1 at y by
setting y’. ∂f =1. i.e., y’ x’ z + y’ x z’ = 1
∂y
◦ Test set for detecting SA0 at y: T = {001, 100}
39
Boolean Difference – Example 2
◦ A circuit realizes the function z=x1’x4+x2’x3+x1x4’. Using
the Boolean difference method, find the test vectors for
SA0 faults and SA1 faults on the input line x1 of the
circuit.
◦ Step 1: Compute the Boolean difference
∂f
=(0.x4+x2’x3+1.x4’) ⊕ (1.x4+x2’x3+0.x4’)
∂x1
= (x2’x3+x4’) ⊕ (x4+x2’x3) = x2+x3’
40
Contd…
Step 2: Generate test vectors to detect SA0 at y by
setting x1. ∂f =1. i.e., x1 x2 + x1 x3’ = 1
∂x1
◦ Test set for detecting SA0 at y: T = {1 1 x3 x4, 1 x2 0 x4}
Step 3: Generate test vectors to detect SA1 at y by
setting x1’. ∂f =1. i.e., x1’ x2 + x1’ x3’ = 1
∂x1
◦ Test set for detecting SA1 at y: T = {0 1 x3 x4, 0 x2 0 x4}
41
Boolean Difference – Example 3
◦ Find the Test Vector to test the fault s-a-0 at node Z
using Boolean Difference Method.
42
Contd…
◦ Step 1: Output Expression f = x y + x y z
◦ Step 2: Compute the Boolean difference
∂f
=(x y + x y.1) ⊕ (x y + x y.0)
∂z
= (x y) ⊕ (x y) = 0
∂f
◦ Step 3: Condition to detect s-a-0, z. = 1. But this
∂z
condition cannot be satisfied Fault is undetectable
(Reason: redundancy in the circuit)
43
Kohavi Algorithm
◦ The path sensitization and Boolean difference methods
are used for detecting single faults. They are not
practically feasible for systems with multiple faults.
◦ The Kohavi algorithm can be used for detecting multiple
faults in two level networks.
◦ This technique consists of two sets of tests: a-tests
(SA0 faults) and b-tests (SA1 faults).
◦ For effective implementation of this algorithm, three
restrictions are imposed.
44
Contd…
◦ They are:
◦ The network must be a two level AND-OR or OR-
AND network.
◦ Each AND gate must realize a prime cube (a term in
the function that cannot be simplified further by
combining with other terms).
◦ The AND-OR network must implement a Boolean
function which is a sum of irredundant prime
implicants.
45
Example 1
◦ Consider the two-level AND-OR circuit.
◦ f= x1x2’ + x3x4.
◦ Here, each AND gate realizes prime cubes. Hence, the
output can be expressed as a sum of irredundant prime
implicants.
◦ The set of minterms that test each AND gate for SA0
faults is called the set of a-tests.
◦ A SA0 fault on any input of an AND gate results in the
elimination of the prime implicant realized by that AND
gate.
46
Contd… x 1x 2
x 3x 4
00 01 11
x3x4(2211)
10
00 1
Minterms Cubes
01 1 x 1x 2 ’
x 1x 2 ’ 1022 (1022)
11 1
x 3x 4 2211
10 1 1 1 1
Table for a-tests Corresponding K-map
o To derive the a-tests, consider each cube and mark a
minterm that belongs to only that cube.
o For cube 1022, minterm 8 or 9 or 10 can be used.
o For cube 2211, minterm 3 or 7 or 15 can be used.
o a-test vectors={1000 or 1001 or 1010, 0011 or 0111 or
1111} 47
Contd…
◦ The set of minterms that test each AND gate for SA1
faults is called the set of b-tests.
◦ Suppose there is SA1 fault in the input line x2’, then the
effect of this fault is to change the prime implicant x1x2’
to x1.
◦ To derive the b-tests, consider each cube and mark all
the adjacent cubes.
◦ Choose a set of minterms that will cover all these
subcubes but not present in the function.
48
x 3x 4
Contd…
x 1x 2 00 01 11 10
00
01
Cubes Adjacent
11
1022 1122
10
1022 0022
2211 2201 Corresponding map
2211 2210 Minterm Cubes covered
Table for b-tests 1 0022,2201
◦ Test set={0001,1110} 14 1122,2210
◦ For OR-AND circuits, a-test for SA1 faults and b-
test for SA0 faults.
49
Example 2
◦ Find the test vectors for all SA0 and SA1 faults of the
circuit whose Boolean function is x1x2+x1x3’x4’ +x2x4 using
Kohavi algorithm.
50
a-test
o * denotes the minterms that belong to only one group.
o Test set: {1000, 1110, 0101 or 0111}
51
b-test
o Test set: {0100, 1001, 1010}
52
Automatic Test Pattern Generation
◦ Automatic Test Pattern Generation (ATPG) is a crucial
technique in digital circuit testing, particularly in ensuring
the correctness and functionality of digital systems.
◦ ATPG is the process of automatically generating a set of
input test patterns that are applied to a circuit under
test (CUT) to detect faults or defects within the circuit.
◦ The ultimate goal of ATPG is to verify the functionality
of the design, identify faults, and ensure that the circuit
operates as expected.
53
Steps involved in ATPG
◦ Fault Modeling: Define the fault models that need to be
tested (e.g., stuck-at faults).
◦ Test Pattern Generation: Automatically generate the test
vectors (input patterns) that will expose the faults in the
circuit. The primary goal is to create a minimal set of test
patterns that provide high fault coverage. Initially, test
vectors are generated randomly (Random ATPG) and
their effectiveness in detecting faults is evaluated. This
method may not guarantee high fault coverage, but it is
computationally faster.
54
Contd…
◦ Fault Simulation and Dropping: Fault simulation is the
process of simulating the behavior of the circuit under
different fault conditions. During this phase, various
faults (such as stuck-at faults) are injected into the
circuit, and the simulation helps to determine which faults
are detectable by the test patterns. The detected faults
are dropped.
◦ Analysis and Refinement: For the undetected faults,
deterministic ATPG is used. It attempts to generate a
test vector for each fault, ensuring high fault coverage.
55
Contd…
56
Types of ATPG
◦ In Automatic Test Pattern Generation (ATPG), different
strategies can be used to generate the test vectors
(input patterns) that are applied to a digital circuit for
fault detection.
◦ The three primary approaches for ATPG are
◦ Pseudorandom ATPG
◦ Ad-hoc ATPG
◦ Algorithmic ATPG
57
Contd…
◦ In pseudorandom ATPG, test patterns are generated
using algorithms that produce random numbers in a
controlled, repeatable manner.
◦ Pseudorandom ATPG is fast and simple, but it may not
achieve high fault coverage.
◦ Adhoc ATPG uses domain-specific knowledge to craft test
vectors that are expected to detect certain types of
faults.
58
Contd…
◦ The term "adhoc" refers to the fact that the test
generation process is often not systematic; instead, it
may be tailored to a specific circuit or application.
◦ Adhoc ATPG results in a small number of test patterns
that are highly effective for specific fault types; but it
can be time-consuming and error-prone.
◦ Algorithmic ATPG relies on sophisticated algorithms to
systematically generate test patterns that are optimized
to detect specific faults in the circuit.
59
Contd…
◦ Fault table, Path sensitization, Boolean difference, and
Kohavi algorithm are examples of algorithmic ATPG
techniques.
◦ Algorithmic ATPG offers high fault coverage, often
achieving better detection rates than pseudorandom
methods. It is more systematic and scalable for large
circuits.
◦ But it can be computationally expensive and can be slower
compared to pseudorandom ATPG.
60
Built-in Self Test (BIST)
◦ BIST (Built-In Self-Test) is a method used to allow a
digital circuit to test itself.
◦ It involves integrating test generation and evaluation
capabilities directly within the circuit under test (CUT),
rather than relying on external test equipment.
◦ This approach is widely used in the testing of integrated
circuits (ICs) and systems, as it allows for efficient,
autonomous, and often in-field testing.
61
Components of BIST
◦ BIST contains a test pattern generator (TPG), CUT, and
response analyzer (RA).
◦ The TPG generates test sequences and applies them to
the CUT.
◦ The RA compresses the output response of the CUT and
compares it with the compressed output response of the
fault-free circuit to detect the fault.
62
Test Pattern Generation Approaches
1. Exhaustive Pattern generation
◦ All possible input patterns are applied to the circuit
under test.
◦ Thus, for an n-input combinational circuit, 2n
patterns need to be applied.
◦ Exhaustive testing is feasible for circuits with a
limited number of inputs.
◦ Advantage: All irredundant faults can be detected.
◦ Disadvantage: When n is large, the approach is time
consuming.
63
Contd…
2. Pseudo-exhaustive Pattern generation
◦ Pseudo-exhaustive testing retains the advantage of
exhaustive testing while significantly reducing the
number of test patterns to be applied.
◦ Here, the circuit under test is partitioned into
several subcircuits such that subcircuits have fewer
inputs for exhaustive testing to be feasible for it.
◦ For example, the circuit shown in fig. (a) with 8
inputs can be partitioned into two subcircuits C1 and
C2 with 4 inputs as shown in fig (b).
64
Contd…
◦ Two control inputs MC1 and MC2 are added. When MC1=0,
and MC2=1 the subcircuit C2 is disabled and C1 can be
tested by applying all input combinations at a, b, c, and d.
◦ Similarly, when MC1=1, and MC2=0 the subcircuit C1 is
disabled and C2 can be tested by applying all input
combinations at c, d, e, and f.
65
Contd…
3. Pseudo Random Pattern Generation (most common)
◦ Usually, pseudo random patterns are generated by an
LFSR because LFSR is easy to implement.
◦ The TPG usually comprises a linear feedback shift
register (LFSR). An LFSR consists of D flip-flops and
XOR gates.
66
Contd…
◦ A k-stage LFSR is shown in Figure.
◦ The output y1 of the last flip-flop is fed back to a subset
of the flip-flops determined by whether the
corresponding bj, 1 ≤j ≤k, is 0 or 1. The presence (absence)
of the feedback is indicated by bj=1 (bj = 0).
◦ The initial state of the LFSR is called the seed.
◦ Clocking of the LFSR causes it to transition from the
seed to the next state, and so on.
◦ These patterns can be fed to a k-input CUT in order to
test it.
67
Contd…
◦ A major problem associated with pseudo random testing is
that the number of patterns needed to detect a fault may
be too large.
◦ For example, consider a 10-input AND gate with SA1 fault
at α.
68
Contd…
◦ It is clear that, only test pattern abcdefghij=1111110111
can detect the fault.
◦ The probability of an LFSR generating this particular
pattern is 2-10.
◦ Thus, a large number of pseudo random patterns need to
be applied to the CUT to improve fault coverage.
◦ An alternate way of generating pseudo random patterns is
to use Cellular Automation (CA).
◦ A CA consists of a number of identical cells
interconnected spatially in a regular manner.
69
Contd…
◦ Each cell consists of a D-flipflop and a combinational logic
to generate the next state of the cell.
◦ The main advantage of CA over LFSR is their inherent
scalability and ability to generate complex, non-linear
patterns due to the interaction between neighboring cells.
◦ Also, CAs do not require long feedback, which results in
smaller delays and efficient layouts.
70
Contd…
4. Deterministic Pattern Generation
◦ In this method, a fault list is generated for the
digital circuit, which includes all possible faults that
can occur based on the fault model.
◦ Then, a deterministic algorithm (Path sensitization
or Boolean Difference) systematically generates test
patterns to detect faults from the fault list. This
step aims to minimize the number of test vectors
while maximizing fault coverage.
◦ The generated patterns and expected outputs are
stored in a ROM.
71
Contd…
◦ At the time of testing, these test patterns are applied to
the circuit, and the outputs are compared to the
expected correct outputs.
◦ If the output for a given input pattern does not match
the expected output, it indicates that a fault has been
detected at the corresponding location.
◦ When the exact fault causing the failure is identified, the
corresponding test pattern is refined if necessary.
◦ This method is rarely used due to the high overhead
associated with storing the test patterns and their
responses.
72
Response Analyzer
◦ For a k-output CUT to which ν test patterns have been
applied by the TPG, we need to analyze the kν output bits
to see if any bit is erroneous, thus indicating the
presence of a fault in the CUT.
◦ To do this, we would need to store the fault-free values
of these bits and do a bit-by-bit comparison with the
response obtained from the CUT.
◦ Since this can be quite expensive in terms of space and
time, output responses are usually compressed.
73
Compression Techniques in RA
1. Transition Count
◦ The transition count is defined as the total number
of transitions from 10 and 01 in the response
sequence for a particular input pattern.
◦ Instead of recording the entire response sequence,
the transition count is recorded.
◦ The transition count is then compared with the
expected one and if they differ, the CUT is faulty.
◦ Adv: neither the correct output nor the actual
output needs to be stored at any test point
Reduction in data storage.
◦ Disadv: fault masking errors 74
Contd…
2. Syndrome Checking
◦ The syndrome of a Boolean function is defined as
S=K/2n where K is the number of minterms realized
by the function and n is the number of input lines.
◦ For example, syndrome of a three input AND gate is
1/8.
◦ Instead of recording the response, syndrome is
recorded.
◦ The syndrome of the faulty circuit is compared with
that of the fault-free circuit. If they differ, the
CUT is assumed to be faulty.
75
Contd…
3. Signature Analysis (most common)
◦ Signatures can be created from the data streams by
feeding the data into an n-bit LFSR.
◦ The feedback mechanism consists of XORing
selected taps of the shift register with the input
serial data.
◦ After the data stream has been clocked through, a
residue of the serial data is left in the shift
register.
◦ This residue is unique to the data stream and is
called the signature.
76
Contd…
◦ When the CUT is being tested, the signature is compared
with the golden signature (signature of the fault-free
circuit) to detect the fault.
◦ To form the signature of a data stream, the LFSR is
initialized to a known state (normally all zeros).
77
Contd…
◦ An n-stage signature generator generates 2n signatures.
◦ However, many input sequences can map into one
signature.
◦ For example, if the length of the input sequence is m, and
no: of stages in the signature generator is n, then 2m input
sequences map to 2n signatures. In other words, 2m-n input
sequences map to each signature.
◦ Only one out of 2m input sequences is error free and
produces the correct signature. However, any one of the
2m-n-1 inputs may also produce the same signature. This
gives rise to Aliasing.
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Contd…
◦ A signature corresponding to the output sequence is
generated usually by feeding the input serially to the
feedback line of an LFSR via an additional XOR gate.
◦ The signature can also be obtained by feeding a subset of
the output sequence in parallel to a modified LFSR that is
called multiple-input signature register (MISR).
◦ When the CUT is being tested, in each cycle a k-bit
response is fed to the MISR, leading it to a new state.
When the final k-bit response is fed to the MISR, the
state it enters is the signature.
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