8

COUNTERS

CHAPTER CONTENT OBJECTIVES OF THE CHAPTER

■ Describe the difference between an asynchronous counter

8.1 Operation of the asynchronous counter
8.2 Operation of the synchronous counter not and a synchronous counter.
8.3 Up/Down Synchronous Counter ■ Analyze the timing diagrams of the counters
pains.
8.4 Design of Synchronous Counters
■ Analyze the counting circuits.
8.5 Cascading counters
■ Explain how propagation delay affects.
8.6 Decoding of counters
to the functioning of a counter.
8.7 Applications of counters
■ Determine the modulus of a counter.
8.8 Logical symbols with notation of
■ Modify the module of a counter.
dependency
■ Establish the differences between binary counters
8.9 Fault localization
4-bit registers and decade counters.
■ ■ ■ Application to digital systems
■ Use an ascending/descending counter INTRODUCTION
to generate direct and inverted binary sequences
sas. As already seen in Chapter 8, the flip-flops
they can connect to each other to perform functions of
■ Determine the sequence of a counter.
count. This combination of flip-flops is called
■ Use integrated circuit counters in diver- denominates counter. The number of flip-flops that is
these applications. they use and the way they connect determine the
■ Design a counter that can have any number of states (referred to as mode-
specified sequence of states. and also the specific sequence of states by
■ Connect several counters in cascade to the ones the counter goes through during a complete cycle.
follow major modules. Depending on how the signal is applied
of clock, counters are classified into two broad
■ Use logic gates to decode which-
categories: asynchronous and synchronous. In the counted-
status of a counter.
asynchronous networks, usually referred to as spot
■ Eliminate the glitches in the decoding of con- res with propagation (ripple counters), it is applied a
tadores. external clock signal to the clock input of the first
■ Explain how a digital clock works. flip-flop and then the following flip-flops are given
■ Interpret the logical symbols of the counters apply the clock signal through the flip-flop output
that use dependency notation. anterior flop. In synchronous counters, the input
the clock connects to all the flip-flops, in such a way
■ Locate faults in the meters and resolve them
that the clock signal is applied to them simultaneously.
different types of failures.
Within each of these two categories, the with-
KEYWORDS Traders are classified by the type of sequence, the
number of states or the number of flip-flops of the con-
■ Asynchronous tador.
■ New cycle (recycle) FIXEDFUNCTIONDEVICES
■ Module
■ Decade 74XX93 74XX161 74XX162
74XX163 74XX190 74XX47
■ Synchronous
■ In the end ■ ■ ■ APPLICATION OF SYSTEMS
■ State machine DIGITAL
■ State diagram This application to digital systems illustrates the
■ Cascading connection concepts that are addressed in the chapter. It continues
with the traffic light control system of the latest
two chapters. This chapter deals with logic
sequential of the system that produces the sequence of
lights based on the inputs of the tem- circuits
porization and vehicle sensor. The parts of-
developed in Chapters 6 and 7 are combined with the
sequential logic to complete the system.
476 ■ COUNTERS

8.1 OPERATION OF THE ASYNCHRONOUS COUNTER

The term asynchronous refers to events that do not have a fixed temporal relationship between them.
which generally do not occur at the same time. An asynchronous counter is one in which the flip-
The flip-flops (FF) of the counter do not change state exactly at the same time, since they do not share
the same clockwork impulse.
By the end of this section, the reader should be able to:
■ Describe the operation of a 2-bit asynchronous binary counter. ■ Describe how it works
counting of a 3-bit asynchronous binary counter. ■ Define the propagation in asynchronous counters
nos.■ Describir el funcionamiento de un contador de décadas asíncrono. ■ Develop the diagrams
from the times of the accountants.■ Describe the 4-bit binary asynchronous counter 74LS93.

2-bit asynchronous binary counter

The entrance of Figure 8.1 shows a 2-bit counter configured to operate in mode
counter watch asynchronous. Note that the clock (CLK) is connected only to the input of
always asynchronous clock (C) of the first flip-flop, FF0. The second flip-flop, FF1, is triggered by the
is only connected exit Q0 FF0 changes state during the positive edge of each pulse
the flip-flop LSB. of the clock, but FF1 only changes when triggered by a positive transition of the
FF0 Q0output. Due to the inherent propagation delay of signal passing.
for a flip-flop, the transitions of the clock input pulses and the output Q0they cannot occupy from FF0
never trigger at the same time. Therefore, the two flip-flops never trigger simultaneously, so the
the operating mode of this counter is asynchronous.

HIGH
FF0 FF1

J0 Q0 J1 Q1
CLK
C C
Q0
K0 K1

FIGURE 8.1 2-bit asynchronous binary counter.

Time [Link] are going to examine the basic operation of the asynchronous counter in Figure 8.1.
applying four clock pulses to FF0 and observing the output Q of each flip-flop. Figure 8.2 illustrates the
state changes in the outputs of the flip-flop in response to clock impulses. Both flip-flops are
connected in toggle mode (J= 1, K= 1) and it is assumed that, initially, they are in RESET state
(At a LOW level).
The positive edge of CLK1 (clock pulse 1) causes the output Q0from FF0 pass to HIGH level, like
Figure 8.2 is shown. At the same time, the output Q0 it goes to a LOW level, but this does not affect FF1, since
It has to be a positive transition that triggers it. After the previous flank of CLK1, Q0= 1 yQ1= 0.
The accountants The positive flank of CLK2 causes Q0low level pass. The output Q0 is set to
asynchronous ones are known high level and shoot FF1, making Q 1 high level pass. After the front flank
also as told- Prior to CLK2,Q0 = 0 yQ11. The positive flank of CLK3 causes Q0pass level
res with propagation. STOP again. The exit Q0 it is set to LOW and does not affect the state of FF1.
Therefore, after the previous flank of CLK3,Q0= 1 yQ11. The positive flank of
 ■ 477
OPERATION OF THE ASYNCHRONOUS COUNTER

CLK4 causes Q0passed at a LOW level, while Q0 it is set to HIGH and triggers FF1, causing that
Q1low level rate. After the front flank of CLK4, Q0= 0 yQ1. The counter has returned to its esta-
do original (the two flip-flops are in RESET state).

CLK 1 2 3 4

Q0

Outputs Q0(LSB)

Q1(MSB)

FIGURE 8.2 Timing diagram of the counter in Figure 8.1. As in previous chapters,
The output waveforms are shown in black.

In the time diagram, the waveforms of the outputs Q0 yQ1are shown based on the impulses
clock source, as illustrated in Figure 8.2. To simplify, the transitions of Q0,Q1and the clock pulses
they show as simultaneous, even though it is an asynchronous counter. There is, of course, a slight delay-
between the CLK transitions and Q0and the transitions of Q0 yQ1.
In digital logic Observe in Figure 8.2 that the 2-bit counter has four different states.
tal, Q0is always the rents, as one would expect from two flip-flops (22= 4). In addition, please note that
a bit less significant, siQ0represents the least significant bit (LSB) and Q1represents the most significant bit
(LSB), unless it is captive (MSB), the sequence of the counter states represents a sequence of
indicate the opposite. binary numbers, as shown in Table 8.1.
Since it passes through a binary sequence, the counter in Figure 8.1 is a
binary counter. In reality, it counts the number of clock pulses up to the third one, and on the fourth pulse,
starts a new cycle from its original state (Q0 = 0,Q1= 0). The start of a new cycle (recycle, term-
The term commonly applied to the operation of counters refers to the transition of the counter.
from its final state to its original state.
Synchronous binary counter of 3 bitsThe
state sequence of a 3-bit binary counter is presented in the
Table 8.2 and Figure 8.3(a) show a 3-bit asynchronous binary counter. Its basic operation
it is the same as the 2-bit counter, except that the 3-bit counter has eight states, since it is
formed by three flip-flops. Figure 8.3(b) presents a timing diagram for eight pulses of
watch. Note that the counter in Figure 8.3 advances through a binary sequence from zero to seven,
starting a new cycle from its zero state. This counter can be easily expanded to a con
or larger, connecting additional flip-flops.

Clock impulse Q1Q2

Initially 0 0
1 0 1
2 1 0
3 1 1
4 (new cycle) 0 0

TABLE 8.1 Sequence of binary states for the counter in Figure 8.1.
478 ■ COUNTERS

Clock pulse Q2 Q1 Q0
Initially 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 (new cycle) 0 0 0

TABLE 8.2 Sequence of states of a three-bit binary counter.

HIGH
FF0 FF1 FF2

J0 Q0 J1 Q1 J2 Q2

CLK C C C
Q0 Q1
K0 K1 K2

(a)

CLK 1 2 3 4 5 6 7 8

Q0(LSB) 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 0 1

Q2(MSB) 0 0 0 0 1 1 1 0 1

(b) New cycle to

starting from state 0

FIGURE 8.3 Three-bit asynchronous binary counter and its timing diagram for one cycle.

Propagation delayAsynchronous counters are also referred to as propagation counters.

for the following reason: the effect of a pulse on the clock input is first 'felt' by FF0. This effect does not
it arrives immediately at FF1, due to the propagation delay through FF0. In the same way, it occurs
a propagation delay through FF1, before FF2 can be triggered. Therefore, the effect of a
the pulse at the clock input "propagates" through the counter, taking a certain amount of time to reach the
last of the flip-flops, due to propagation delays.
As an illustration, observe that all the flip-flops of the counter in Figure 8.3 change state at
anterior flank of CLK4. This clock signal propagation effect is shown in Figure 8.4 for the
 OPERATION OF THE ASYNCHRONOUS COUNTER
■ 479

four first clock pulses, indicating the propagation delays. The transition from HIGH level to level
UNDER deQ0 it occurs after a certain delay (tPHLafter the positive transition of the drive
Clock. The transition from HIGH level to LOW level ofQ1a time occurs (tPLH) after the transition
Q transition from LOW level to HIGH level of Q2occurs after another unit of challenge-
positive of0The
Q see, FF2 does not trigger until they have elapsed-
do (tPLHafter the positive transition of1As you can
Delay units after the positive edge of the clock pulse, CLK4. Therefore, they are needed
three delay units for the CLK4 clock pulse effect to propagate through the counter and Q2
move from LOW level to HIGH level.

CLK 1 2 3 4

Q0

Q1

Q2

tPHL(CLK a Q0 ) tPHL(CLK a Q0)

tPLH tPLH(Q0aQ1) tPHL(Q0aQ1)
tPLH(Q1aQ2)
(CLK a Q0 )

FIGURE 8.4 Propagation delays in a 3-bit asynchronous binary counter (with clock propagation).

This cumulative delay of an asynchronous counter is one of its greatest disadvantages for many ap-
cations, as it limits the speed at which the counter can be synchronized, and it may lead to problems-
more than decoding. The maximum cumulative delay in a counter must be less than the period of
the clock signal.

EXAMPLE8.1
Figure 8.5(a) shows a 4-bit asynchronous binary counter. Each flip-flop is triggered by
negative edge and has a propagation delay of 10 nanoseconds (ns). Draw a timing diagram.
show the output of each of the flip-flops and determine the total propagation delay
from the firing flank of a clock pulse until the corresponding change can occur
in the state of Q3Also determine the maximum clock frequency at which the counter can operate.
door.
Solution Figure 8.5(b) shows the timing diagram, having omitted the
delays. As for the total delay, the effect of CLK8 or CLK16 is
it must propagate through four flip-flops before Q 3I changed, from
form that:
t p(tot) = 4 ×10 nanoseconds= 40ns

The maximum clock frequency is:

1 1
fmax = = = 25MHz
t p(tot ) 40ns
480 ■ COUNTERS

HIGH
FF0 FF1 FF2 FF3
Q0 Q1 Q2 Q3
J0 J1 J2 J3

CLK C C C C

K0 K1 K2 K3

(a)

CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Q0

Q1

Q2

Q3

(b)

FIGURE 8.5 4-bit asynchronous binary counter and its timing diagram.

Problem related* Draw the timing diagram if all the flip-flops in Figure 8.5(a) were
they ran hastily along the positive flank.

The answers can be found at the end of the chapter.

Asynchronous decade counter

The modulus of a counter is the number of distinct states that the counter goes through.
A counter
it can happen sequentially. The maximum number of possible states (module
can have 2n
maximum) of a counter is 2n, where represents the number of flip-flops of the
states, being n the
counter. Counters can also be designed to have a number of states in their
number of flip-flops.
sequence that is less than the maximum of 2nThe resulting sequence is called
truncated sequence.
A typical module in counters with truncated sequence is ten (called MOD10). The counted-
those that have ten states in their sequence are called decade counters. A decade counter,
whose counting sequence goes from zero (0000) to nine (1001), is a BCD decade counter, since its
A sequence of ten states corresponds to the BCD code. This type of counter is very useful in applications.
Display sections, where BCD codes are needed for conversion to decimal code.
To obtain a truncated sequence, it is necessary to force the counter to start a new cycle before
having passed through all normal states. For example, the decade BCD counter has to start
 ■ 481
OPERATION OF THE SYNCHRONOUS COUNTER

again in state 0000 after passing through state 1001. A decade counter requires four flip-
flops (three would be insufficient, since 23=8).
To illustrate the principle of truncated counters, we will use a 4-bit asynchronous counter.
like in Example 8.1, in which we will modify its sequence. One way to make a counter start
A new cycle after reaching nine (1001) consists of decoding ten (1010) with a child-
connect the output of the NAND gate to the erase inputs (CLR) of the flip-flops, how to
shown in Figure 8.6(a).

10 Decoder
CLR

HIGH
FF0 FF1 FF2 FF3
Q0 Q1 Q2 Q3
J0 J1 J2 J3

CLK C C C C

K0 K1 K2 K3
CLR CLR CLR CLR

(a)

CLK 1 2 3 4 5 6 7 8 9 10

Q0

Glitch
Q1

Q2

Q3

CLR
Glitch
(b)

FIGURE 8.6 Asynchronous decade counter with asynchronous reset.

Partial decodingNote in Figure 8.6(a) that only Q1yQ3they are connected to the inputs of
the NAND gate. This arrangement is an example of partial decoding, through which two unique states...
two (Q1= 1 yQ31) are sufficient to decode the value ten, since none of the other states (of
zero to nine) haveQ1yQ3at a HIGH level at the same time. When the counter reaches the number ten (1010),
the output of the decoder door goes to LOW and asynchronously resets all flip-flops to zero.
482 ■ COUNTERS

The resulting timing diagram is shown in Figure 8.6(b). Note that there is a glitch in the shape.
of waveQ1The reason for these glitches is1It has to go through the HIGH level first before the number.
At ten it can be decoded. Up to a few nanoseconds after the counter reaches the number ten, the
the output of the decoder does not go to LOW level (both inputs are at HIGH level). Therefore,
the counter is in state 1010 for a short period of time before being reset to
0000, producing, therefore, theglitchenQ1and in the line (CLR) that serves to reset the counter to zero.
As shown in Example 8.2, other truncated sequences can be implemented in a similar way.

EXAMPLE8.2
Explain how to implement an asynchronous counter with a modulus of twelve using a sequence.
direct binary from 0000 to 1011.

Decoder of 12

HIGH
FF0 FF1 FF2 FF3
Q0 Q1 Q2 Q3
J0 J1 J2 J3

CLK C C C C

K0 K1 K2 K3
CLR CLR CLR CLR
CLR

(a)

CLK 1 2 3 4 5 6 7 8 9 10 11 12

Q0

Q1
Glitch
Q2

Q3

Output of
decoder
(CLR) Glitch
(b)

FIGURE 8.7 Module 12 counter with asynchronous timing and reset.

 OPERATION OF ASYNCHRONOUS COUNTER
■ 483

Solution Since three flip-flops can generate a maximum of eight states, it is necessary to
we have four flip-flops to produce any module greater than eight and
less than or equal to sixteen.
When the counter reaches the final state 1011 it has to start a new one.
cycle starting from 0000, instead of transitioning to the next natural state, 1100, as
illustrate the following sequence:
Q3Q2 Q1 Q0
0 0 0 0
. . . .
. . . . New cycle
. . . .
1 0 1 1
1 1 0 0 Next normal state

Note that, in any case, both Q0howQ1they take the value 0, while-
after that aQ2yQ3they must be forced to take the value 0 in the twelfth
my clock pulse. Figure 8.7(a) shows the modulo 12 counter. The
NAND gate partially decodes the number twelve (1100) and sets to zero the
flip-flops 2 and 3. Therefore, on the twelfth clock pulse, the ...
tador a iniciar un nuevo ciclo, pasando de once a cero, como se muestra en el
time diagram of Figure 8.7(b). It remains at number twelve only
for a few nanoseconds before it goes to zero due to the glitch
(CLR).

Related problem. How can the counter in Figure 8.7(a) be modified to make it a
module 13 counter?

4-BIT ASYNCHRONOUS BINARY COUNTER 74LS93

The 74LS93 is an example of an asynchronous counter integrated circuit. As shown the day-
Logical grammar of Figure 8.8, this device is made up of a flip-flop and a counter.
3-bit asynchronous door. This arrangement provides you with great flexibility. If you
use only the flip-flop, it can be used as a divide by 2 device; and if it
using only the 3-bit counter, it can be used as a modulo 8 counter.
This device also provides reset inputs (RESET) RO(1) and RO(2).
When these two inputs are HIGH, the counter resets to the state 0000
by means ofCLR .
Additionally, the 74LS93A can be used as a 4-bit counter with modulus 16.
(count from zero to 15), connecting the output Q0at input CLK B, as shown the
Figure 8.9(a). It can also be configured as a decade counter (counting from 0 to 9)
with asynchronous reinitialization, using the reset inputs to decode
partially the number ten, as shown in Figure 8.9(b).
484 ■ COUNTERS

(1)
CLK B

J0 J1 J2 J3
(14)
CLK A C C C C

K0 K1 K2 K3
CLR CLR CLR CLR
(2)
RO(1)
(3)
RO(2) CLR
(12) (9) (8) (11)

Q0 Q1 Q2 Q3
(LSB) (MSB)

FIGURE 8.8 Logical diagram of the 4-bit asynchronous binary counter 74LS93. The pin numbers
They are indicated in parentheses. All the JyK entries are internally connected at a HIGH level.

CLK A C CTR DIV 16 CLK A C CTR DIV 10

CLK B C CLK B C
RO(1) RO(1)
RO(2) RO(2)

Q0Q1Q2Q3 Q0Q1Q2Q3

(a) 74LS93 connected as a modulo 16 counter (b) 74LS93 connected as a decade counter

FIGURE 8.9 Two configurations of the asynchronous counter 74LS93.

The CTR DIVn label indicates a counter of states.

EXAMPLE8.3
Explain how a 74LS93A can be used as a modulo 12 counter.
SolutionUse the reset inputs RO(1) and RO(2) to partially decode
mind the number 12 (remember that there is an associated internal NAND gate)
these entries). The decoding of number 12 is carried out by connecting Q3
aRO(1)yQ2aRO(2), as shown in Figure 8.10. The output Q0himself
connect CLK B to achieve a 4-bit counter.
Immediately after the counter reaches state 12 (1100), it will-
go to the initial state 0000. The start of a new cycle, however, originates a
glitchenQ2due to the fact that the counter has to remain in state 1100
for a few nanoseconds before starting another cycle.
 FUNCTIONING OF THE SYNCHRONOUS COUNTER
■ 485

CLK A C CTR DIV 12

CLK B C
RO(1)
RO(2)

Q0Q1Q2Q3

FIGURE 8.10 74LS93 connected as a modulus 12 counter.

Related problem Explain how a 74LS93 could be connected as a modulo 13 counter.

What does the term asynchronous mean in relation to counters?

REVIEW OF
SECTION 8.1 2. How many states does a modulo 14 counter have? What is the minimum number
the required flip-flops?
The answers are
found at the end
of the chapter

8.2 OPERATION OF THE SYNCHRONOUS COUNTER

The term 'synchronous' refers to events that have a fixed temporal relationship with each other.
synchronous counters are those in which all the flip-flops of the counter receive the signal at the same instant
of clock.
Al finalizar esta sección, el lector deberá ser capaz de:
■ Describe the operation of a 2-bit synchronous binary counter.■ Describe the functioning
to a 3-bit synchronous binary counter. ■ Describe the operation of a synchronous counter
4-bit binary.■ Describe the operation of a synchronous decade counter.■ Develop the
timing diagrams of the counters.■ Use the 4-bit binary counter 74HC163 and the count-
dor BCD de décadas 74F162.

2-bit synchronous binary counter

Figure 8.11 shows a 2-bit synchronous binary counter. Note that a configuration must be used.
different from that of the asynchronous counter for the inputs J1yK1from FF1, in order to be able to obtain a sequence-
binary clock.
On a counter The operation of this synchronous counter is as follows: first of all, it
synchronous, the input suppose that the counter is initially in binary state 0; that is, the
the clock reaches Two flip-flops are in the RESET state. When the positive edge is applied
each flip-flop. from the first clock impulse, FF0 swings, so Q0It is set to HIGH. What
What happens to FF1 on the positive edge of CLK1? To find out, let's take a look.
in the entry conditions of FF1. The inputsJ1yK1both are at a LOW level, as they are connected-
the aQ0, and this has not been set to HIGH yet. Remember that there is a propagation delay from
486 ■ COUNTERS

HIGH
FF0 FF1
Q0
J0 J1 Q1

C C

K0 K1 Q1

CLK

FIGURE 8.11 Two-bit synchronous binary counter.

the firing flank of the clock pulse until the transition at the output Q actually occurs. Therefore,
J = 0 and K = 0 when the leading edge of the first clock pulse is applied. This is a no change condition.
bio y, and therefore, FF1 does not change state. Figure 8.12(a) shows part of the timing diagram.
of this phase of the counter's operation.
After CLK1,Q0= 1 yQ1= 0 (which corresponds to the binary state 1). When the edge occurs
front of CLK2, FF0 swings yQ0 it is set to LOW. Since FF1 has a HIGH level (Q0= 1) in
your entries1yK1during the firing flank of the clock pulse, the flip-flop swings and Q 1pass to level
HIGH. Therefore, after CLK2,Q0= 0 yQ1= 1 (which corresponds to the binary state 2). In Figure
Section 8.12(b) shows this part of the timing diagram in detail for this condition.
When the leading edge of CLK3 occurs, FF0 toggles back to the SET state (Q0= 1) y FF1 per-
remains in SET state (Q1= 1), since its inputsJ1yK1both are at a LOW level (Q0= 0). After this
attack flank,Q0= 1 yQ1= 1 (which corresponds to binary state 3). Figure 8.12(c) shows it.
detail the timing diagram for this condition.
Finally, during the front flank of CLK4,Q0yQ1they are set to LOW level, since both flip-
flops are in toggle mode due to the present value in their inputs JyK. In Figure 8.12(d) there
show in detail the timing diagram for this condition. The counter has just started a new cycle at
starting from its original state, binary 0.

CLK1 CLK2

1 1
Q0 Propagation delay Q0 Propagation delay through FF0
0 0
through FF0
Q1 Q1 1 Propagation delay through FF1
0 0
(a) (b)

CLK3 CLK4

Q0 1 Propagation delay Q0 1 Propagation delay through FF0

0 through FF0 0
1 1
Q1 Q1 Propagation delay through FF1
0
(c) (d)

FIGURE 8.12 Timing diagrams for a 2-bit synchronous counter (the propagation delays
both flip-flops are considered equal).
 ■ 487
OPERATION OF THE SYNCHRONOUS COUNTER

The complete timing diagram of the counter in Figure 8.11 is shown in Figure 8.13. Note that
All signal transitions coincide; that is, propagation delays are not indicated.
Although delays are an important factor in the operation of a synchronous counter, they are often overlooked.
to simplify the general time diagrams. If the small delays and the differences are not shown
Timing circuits can better correlate the resulting signals of a logic circuit. Without
embargo, in high-speed digital circuits, these small delays are an important consideration
in the design and location of faults.

CLK 1 2 3 4

Q0

Q1

FIGURE 8.13 Timing diagram of the counter in Figure 8.11.

3-bit binary synchronous counter

Figure 8.14 shows a 3-bit synchronous binary counter and Figure 8.15 shows its timing diagram.
In order to understand the operation of this type of counter, its sequence must be carefully examined.
of states, which is shown in Table 8.3.

HIGH
FF0 FF1 Q0 Q1 FF2
Q0 Q1
J0 J1 J2 Q2

C C C

K0 K1 K2

CLK

FIGURE 8.14 3-bit synchronous binary counter.

CLK 1 2 3 4 5 6 7 8

Q0

Q1

Q2

FIGURE 8.15 Timing diagram of the counter in Figure 8.14.

First of all, let's take a look at Q0. Note that, Q0 changes with each clock pulse as
the counter progresses from its original state to its final state, and then begins a new cycle from the
488 ■ COUNTERS

Clock pulse Q2 Q1 Q0
Initially 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 (new cycle) 0 0 0

TABLE 8.3 Sequence of states of the three-bit binary counter.

COMPUTER NOTES
The TSC (Time Stamp Counter) in the Pentium is used to monitor the function.
operation, which allows for the exact determination of a series of important parameters within the
global operation of a Pentium system. Reading the TSC before and after the execution of a proce-
Therefore, the precise time required for the procedure can be determined based on the frequency.
of the processor cycle. In this way, the TSC is the basis for determining all the related timings
you swim with the optimization of the system's performance. For example, it can be determined precisely
sa cuál de dos o más secuencias de programación es la más eficiente. Ésta es una herramienta muy útil para
the compiler developers and system programmers, when generating the most efficient code
for the Pentium.

original state. To achieve this operation, FF0 must remain in toggling mode, ap
constantly achieving high levels in their entries0yK0Please note that1pass to the counter state
I laugh every time I0it is at 1. This change occurs in CLK2, CLK4, CLK6, and CLK8. The CLK8 pulse makes
that the counter starts a new cycle. To achieve this mode of operation, it connects0to the entriesJ1
yK1from FF1. WhenQ0It is at 1 and a clock pulse is produced, FF1 is in toggle mode.
and therefore, changes state. The rest of the time, whenQ0it's 0, FF1 is in no change mode, remaining
in its current state.
Next, we will see how to get FF2 to change state at the right moments of
according to the binary sequence. Note that the two times that Q2change of state, the only one must be fulfilled
condition that bothQ0as how Q1are at a HIGH level. This condition is detected by the AND gate,
whose output is applied to the inputs J2yK2from FF2. Whenever Q0yQ1they are at a HIGH level, the output of the
door AND makes the entries2yK2set FF2 to HIGH, and FF2 oscillates in the following
clock pulse. The rest of the time, the inputsJ2yK2the FF2 remain at a LOW level, just like the
output of the AND gate, and FF2 does not change state.

4-bit synchronous binary counter

Figure 8.16(a) presents a 4-bit synchronous binary counter and Figure 8.16(b) shows its diagram of
times. This particular counter is implemented with negative edge-triggered flip-flops. The reasoning-
to control the inputs JyK the first three flip-flops is the same as that of the 3-bit counter,
previously studied. The fourth stage, FF3, varies only twice in the sequence. Note that these two trans-
decisions happen just whenQ0,Q1yQ2they are at a HIGH level. This condition is decoded through the puer-
 ■ 489
FUNCTIONING OF THE SYNCHRONOUS COUNTER

HIGH

FF0 FF1 Q0Q1 FF2 Q0Q1Q2 FF3

Q0 Q1 G1 G2
J0 J1 J2 J3 Q3
Q2

C C C C

K0 K1 K2 K3

CLK
(a)

Q0Q1 Q0Q1Q2 Q0Q1 Q0Q1Q2

CLK

Q0

Q1

Q2

Q3

(b)

FIGURE 8.16 4-bit synchronous binary counter and timing diagram. The moments when the outputs
The doors AND are at HIGH level are indicated with shaded areas.

ta ANDG2 so that when a clock pulse occurs, FF3 changes state. In the other cases,
the tickets3yK3The FF3 are at a LOW level and the condition of no change occurs.

4-bit synchronous decade counter

As we know, a BCD decade counter has a truncated binary sequence that goes from 0000.
to state 1001. Instead of moving to state 1010, it starts a new cycle from state 0000. In the
Figure 8.17 shows a synchronous BCD decade counter. Figure 8.18 displays the diagram of
times for this decade counter.
The operation of this counter can be understood by examining the state sequence of Table 8.4.
and following the implementation of Figure 8.17. First, note that FF0 (Q0scale on each
clock pulse, thus the logical equation for its inputs J0yK0es:
J0=K0= 1
This equation is implemented by connecting J0yK0at a constant HIGH level.
490 ■ COUNTERS

HIGH

FF0 Q0 FF1 FF2 FF3

J0 J1 J2 J3
Q1 Q2 Q3

C C C C

Q3
K0 K1 K2 K3

CLK

FIGURE 8.17 Synchronous BCD decade counter.

CLK 1 2 3 4 5 6 7 8 9 10

Q0 0 1 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0 0 0

Q2 0 0 0 0 1 1 1 1 0 0 0

Q3 0 0 0 0 0 0 0 0 1 1 0

FIGURE 8.18 Timing diagram of the BCD decade counter (Q0it is the LSB).

Next, observe in Table 8.4 that FF1 (Q1changes on the next clock pulse every time it
Q0= 1 yQ3= 0, so the logical equation for the inputs J1yK1es:

J1= K1= Q0Q3

This equation is implemented by applying the AND operation to the outputs Qy,
0
and
Q3 connecting the output of
the door to the entrances1yK1the FF1.
The flip-flop 2 (Q2Change state on the next clock pulse every time Q0 = 1 yQ11. Then
the input logic equation is:

J 2= K 2= Q0Q1
This equation is implemented by applying Q.0yQ1to the inputs of an AND gate, and connecting the output
from the door to the entrances2yK2of FF2.
Finally, FF3 (Q3) changes state on the next clock pulse each time Q0= 1,Q1= 1 y
Q2= 1 (state 7), or when Q0= 1 yQ3= 1 (state 9). The equation that governs this is the following:

J 3= K 3= Q0Q1Q2+ Q0Q3
This function is implemented through the AND/OR logic connected to the inputs J.3yK3from FF3, how it
It is shown in the logical diagram of Figure 8.17. Note that the only difference between this decade counter
 FUNCTIONING OF THE SYNCHRONOUS COUNTER
■ 491

Clock impulse Q3 Q2 Q1 Q0
Initially 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 (new cycle) 0 0 0 0

TABLE 8.4 States of the BCD decade counter.

The y and the binary counter modulo 16 of Figure 8.16 are the AND gate with inputs Q0Q3, the door
AND with entriesQ0Q3and the OR gate; this arrangement detects the occurrence of the state 1001 and activates the
Counter start a new cycle correctly on the next clock pulse.

4-BIT SYNCHRONOUS BINARY COUNTER 74HC163

The 74HC163 is an example of a 4-bit synchronous binary counter integrated circuit.
The logical symbol is shown in Figure 8.19, with the pin numbering in parentheses.
thesis. This counter has several additional features compared to the characteristics-
basic characteristics of the general synchronous binary counter previously discussed.

Data entries

D0D1D2D3

(3) (4) (5) (6)

(1)
CLR CTR DIV 16
(9)
LOAD
10 (15)
ENT TC= 15 RCO
(7)
ENP
(2)
CLK C

(14) (13) (12) (11)

Q0Q1Q2Q3

Data outputs

FIGURE 8.19 The 4-bit synchronous binary counter 74HC163. The label CTR DIV 16
indicate a counter with sixteen states.
492 ■ COUNTERS

First of all, the counter can be reset synchronously at any

4-bit binary number, applying the appropriate levels at the data inputs for-
Hello. When a LOW level is applied to the LOAD input, the counter will assume the state
from the data inputs in the next clock pulse. Therefore, the sequence of the con-
The counter can start with any 4-bit binary number.
Additionally, there is an active deletion entry at LOW level. (CLR) that sets to zero
synchronously form the four flip-flops of the counter. There are two enable inputs, ENP
These entries must be at a HIGH level for the counter to advance to
through its sequence of binary states. When at least one of the inputs is
LOW level, the counter is deactivated. The clock ripple output
Output, RCO) is set to HIGH when the counter reaches the end count value
the(Terminal Count, TC) of fifteen (TC= 15). This output, along with the inputs of habi-
bidding allows these counters to be arranged in cascade to achieve
higher account sequences.
Figure 8.20 shows a timing diagram of this counter, which is initialized
in state 12 (1100) and then advances to its final value of account 15 (1111). The
entranceD0corresponds to the least significant input bit yQ0it is the output bit
less significant.
Let'[Link]
the time diagrams that we will find later in this same chapter or

CLR
LOAD

D0

D1
Entries
of data D2

D3

CLK

ENP

ENT
Q0

Q1
Outputs
Q2

Q3

RCO
12 13 14 15 0 1 2

Account Inhibition
Clear Preset

FIGURE 8.20 Example of a timing diagram for a 74HC163.

 ■ 493
FUNCTIONING OF THE SYNCHRONOUS COUNTER

in the manufacturers' specification sheets. To begin with, the push at the level
LOW at the entranceCLR makes all outputs (Q0,Q1,Q2yQ3) get to level
LOW.
Next, the LOW level impulse in the LOAD input introduces in such a way
synchronize the data in the inputs (D0,D1,D2yD3) of the counter. These appear in the
outputsQwhen the first positive clock edge occurs after LOAD
switch to LOW level. This is the initialization operation (PRESET). In this example
particular,Q0is at a LOW level,Q1is at a LOW level,Q2it's at a HIGH level3is
at HIGH level. Of course, this corresponds to the decimal number 12 (Q0it is the least bit
significant).
Now, the counter moves through states 13, 14, and 15 on the next three edges.
clockwise, and then starts a new cycle at 0, 1, 2 with the following impulses
clock SOS. Note that the two ENPyENT inputs are at HIGH level during the
sequence of states. When ENP goes to LOW level, the counter is inhibited and remains
it is in binary state 2.

DECIMAL COUNTER BCD SYNCHRONOUS 74F162

The 74F162 is an example of a decade counter. It can be initialized with any
BCD number using the data inputs with the input PE at a LOW level. A level
LOW at the entrance SR asynchronous resets the counter to RESET state. The inputs of
CEPyCET enablement must be both at a HIGH level for the counter to progress.
that through the sequence of states, in response to a positive transition at the input
from the CLK clock. The enable inputs along with the counting end value, TC
(1001), allows connecting several decade counters in cascade. Figure 8.21
show the logic symbol of the 74F162 counter and Figure 8.22 presents a diagram of
times of the counter initialized in state 7 (0111). The cascading counters are
will be in Section 8.5.

D0D1D2D3

(3) (4) (5) (6)

(1)
SR CTR DIV 10
(9)
PE
(7) (15)
ZIP Code TC= 9 TC
(10)
CET
(2)
CLK C

(14) (13) (12) (11)

Q0Q1Q2Q3

FIGURE 8.21 The synchronous BCD decade counter 74F162. The label CTR DIV 10
indicate a counter with ten states.
494 ■ CONTADORES

SR
PE

D0

EntriesD1
of data
D2

D3

CLK
ZIP code

CET

Q0

Q1
Exits
Q2

Q3

TC
7 8 9 0 1 2 3

Account Inhibition
Clear Preset

FIGURE 8.22 Example of timing diagram of a 74F162.

1. How does a synchronous counter differ from an asynchronous one?

REVIEW OF
SECTION 8.2 2. Explain the operation of the preset function of counters such as the
74HC163.
3. Describe the purpose of the ENPyENT entries and the RCO output for the with-
tador 74HC163.

8.3 UP/DOWN SYNCHRONOUS COUNTER

An up/down counter is one that can progress in either direction.
along a certain sequence. An ascending/descending counter, sometimes also deno-
Bidirectional counter, it can have any specified sequence of states. A counter
3-bit binary that advances in ascending mode through the sequence (0, 1, 2, 3, 4, 5, 6, 7) and that
Then it can be inverted to traverse the sequence in the opposite direction (7, 6, 5, 4, 3, 2, 1, 0) is an ex.
flow of an ascending/descending sequential operation mode.
At the end of this section, the reader should be able to:
■ Explainthe basic functioning of an ascending/descending counter.■ Use the counter of
ascending/descending decades 74HC190.
 ASCENDING/DESCENDING COUNTER ■ 495

In general, most up/down counters can be inverted at any point.

of its sequence. For example, the 3-bit binary counter can be configured to perform the following
sequence:
ASCENDING ASCENDING

0,1,2,3,4,5,4,3,2, 3,4,5,6,7, 6,5, etc. N

DESCENDANT DESCENDANT

Table 8.5 shows the complete up/down sequence of a binary counter

3 bits. The arrows indicate the movements between the states of the counter, both for the ASCENDING mode-
I have like for the Descending mode. An exam ofQ0 for both sequences, ascending and descending,
Show that FF0 toggles with each clock pulse. Then the inputs J0 yK0from FF0 are:
J0=K0=1
For the ascending sequence, Q1changes state on the next clock pulse when Q01. For the
descending sequence,Q1change in the next clock pulse when Q0= 0. Therefore, the inputs1y
K1FF1 must be equal to 1, for the conditions expressed in the following equation:

J1= K1= (Q0⋅ UP+ (Q0⋅ DOWN)

For the ascending sequence, Q2Change state on the next clock pulse when Q0Q1= 1.
For the descending sequence, Q2change on the next clock pulse when Q0=Q1= 0. Therefore, the
entriesJ2yK2The FF2 must be equal to 1, for the conditions expressed in the following equation:

J 2= K 2= (Q0 ⋅Q1⋅ UP)+ (Q0⋅Q1⋅ DOWN

Each of the conditions for the entries JyK where each flip-flop produces a toggling at the point
appropriate to the sequence of the counter.
Figure 8.23 shows a basic implementation of a 3-bit ascending/descending binary counter.
tooth, using the logical equations that we have just developed for the inputs JyK of each flip-flop.
Note that the control input UP/DOWN (ascending/descending) is at HIGH level when it operates.
in ascending mode and at LOW level when operating in descending mode.

UP
Q0UP

HIGH
FF0 FF1 FF2
Q2
J0 J1 J2
Q0 Q1
UP/DOWN
C C C
Q0 Q1 Q2
K0 K1 K2

DOWN
Q0DOWN
CLK

FIGURE 8.23 Up/Down Synchronous Counter

basic of 3 bits.
496 ■ COUNTERS

Clock pulse ASC. Q2 Q1 Q0DESC.

0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

TABLE 8.5 Ascending/descending sequence of a 3-bit binary counter.

EXAMPLE8.4
Draw the timing diagram and determine the sequence of a 4-bit binary synchronous counter ascending.
tooth/descendant, if the clock and the control inputs UP/DOWN these are the signals that are shown in the
Figure 8.24(a). The counter is initialized in the zero state and is of the positive edge triggered type.

UP/DOWN
Peace. Desc. Greetings. Desc.

CLK
(a)

Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 1 1 0 0 1 0 0 1 0 0

Q2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0

Q3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
(b)

FIGURE 8.24

Solution Figure 8.24(b) shows the timing diagram, displaying the outputs
Q. From these waveforms, the sequence of the counter is the one indicated.
as in Table 8.6.
Related problem Draw the timing diagram if the control signal is inverted UP/DOWN
from Figure 8.24(a).
 Synchronous Ascending/Descending Counter ■ 497

Q3 Q2 Q1 Q0

0 0 0 0
0 0 0 1
0 0 1 0 ASCENDING
0 0 1 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1 DESCENDANT
0 0 0 0
1 1 1 1
0 0 0 0
0 0 0 1 ASCENDANT
0 0 1 0
0 0 0 1
DESCENDANT
0 0 0 0

TABLE 8.6

ASCENDING/DESCENDING DECADE COUNTER 74HC190

Figure 8.25 shows the logical diagram of the 74HC190, a good example of a circuit.
integrated ascending/descending counter. The counting direction is determined by
the level of the up/down entry (D/U). When this entry is at HIGH level, the count-
It decrements (descends) from afar; when it is at a LOW level, the counter increments.
(ascends). In addition, this device can be initialized in any BCD digit that is
desire, which is loaded through the data inputs when the inputLOAD is at
low level.

D0D1D2D3

(15) (1) (10) (9)

(4) (12)
CTEN MAX/MIN
(5)
D/U
(11) CTR DIV 10
LOAD
(14) (13)
CLK C RCO

(3) (2) (6) (7)

Q0Q1Q2Q3

FIGURE 8.25 The synchronous up/down decade counter 74HC190.

498 ■ COUNTERS

The MAX/MIN output generates a HIGH impulse when the value is reached
end of account of nine (1001) in ascending order, or when the value is reached
bottom line of zero (0000) in descending mode. The output MAX/MIN, along with
the clock propagation output (RCO) and the count enable input (CTEN)
se usa para conectar contadores en cascada (los contadores en cascada se verán en la
Section 8.5.
Figure 8.26 is a timing diagram, showing a 74HC190 counter.
specialized in seven (0111); the counter then describes an ascending sequence, followed
from a descending sequence. The MAX/MIN output is HIGH when the count-
dor is in state 0 (MIN) or in state 1001 (MAX).

LOAD
D0

D1
Entries
data D2

D3

CLK

D/U
CTEN

Q0

Outputs Q1
of data
Q2

Q3

MAX/MIN

RCO
7 8 9 0 1 2 2 2 1 0 9 8 7

Account Count
ascending Inhibition descendant
Charge

FIGURE 8.26 Example of a timing diagram for a 74HC190.

1. A 4-bit up/down binary counter is in des- mode

REVIEW OF
descending and in state 1010. In the next clock pulse, what state
SECTION 8.3
What happens?
2. What is the end value of a 4-bit binary counter in count-up mode?
Tooth? And in descending mode? What is the next state after the value
final account in descending mode?
 ■ 499
DESIGN OF SYNCHRONOUS COUNTERS

8.4 DESIGN OF SYNCHRONOUS COUNTERS

In this section we will see how sequential circuit design techniques can be applied.
specifically to the design of counters. In general, sequential circuits can be classified into two
types; (1) those in which the output or outputs depend solely on the current internal state (deno-
(1) Moore circuits) and (2) those in which the output or outputs depend both on the state
as well as the input or inputs (known as Mealy circuits). This section is optional and
Can be omitted without affecting the material presented in the rest of the book. The study is recommended
God of this section to those who wish for an introduction to the design of counters or machines of
states in general. It is not necessary to know them to tackle other topics.
At the end of this section, the reader should be able to:
■ Describir un circuito secuencial general en función de sus partes básicas, y de sus entradas y salidas.
■ Develop a state diagram for a given sequence.■ Develop a table of
next state for a specific counter sequence.■ Create a flip transition table
flops.■ Use the Karnaugh map method to obtain the logical requirements of a counter.
asynchronous.■ Implement a counter to generate a specific sequence of states.

General model of a sequential circuit

Before presenting a specific counter design technique, let's start with a general definition
sequential circuit state machine: a sequential circuit is made up of a logic stage
combinational and a memory section (flip-flops), as shown in Figure 8.27. In a circuit
synchronized sequential, there is a clock input in the memory stage, as indicated.

CLK
Lines of excitation
Y0
I0 O0
Logic Y1
I1 combinational O1
Entries Memory Outputs
to enter Yp
Im On

Q0
Q1

Qx
State variable lines

FIGURE 8.27 General synchronized sequential circuit.

For the proper functioning of the circuit, the information stored in the memory stage is required.
ria, as well as the inputs of the combinational logic (I0I1, .....,Im. At any moment in time, the memo-
the RIA is in a state called current state and moves to the next state with a clock pulse.
determined by the conditions of the excitation lines (Y0,Y1, ....,YpThe current state of memory is
represented by the state variables (Q0,Q1, ....,Qx). These state variables, along with the inputs (I0,I1,
...,Im), determine the outputs of the system (O0,O1, ....,On).
500 ■ COUNTERS

Not all sequential circuits have input and output variables as in the general model that is
has just presented. However, they all have excitation variables and state variables. The counters
they are a particular case of synchronized sequential circuits. In this section, a procedure is applied
to the general design of sequential circuits to synchronous counters through a series of steps.

Step 1: state diagram

The first step in designing a counter is to create a state diagram. A diagram of this-
It shows the progression of states through which the counter advances when a clock signal is applied. As
For example, in Figure 8.28, a state diagram of a basic 3-bit Gray code counter is shown.
This particular circuit has no inputs other than the clock input, and no other outputs apart from those that
They are taken in each flip-flop of the counter. If you wish, you can review the Gray code described in Chapter 2.

000
100 001

101 011

111 010
110

FIGURE 8.28 State diagram for a 3-bit Gray code counter.

Step 2: next state table

Once the sequential circuit is defined through a state diagram, the second step consists of
to obtain a table of the following state, which enumerates each state of the counter (current state) along with the
corresponding next state. The next state is the state to which the counter transitions from its state
actual, when applying a clock pulse. The following state table is obtained from the diagram of this-
two, and it is shown in Table 8.7 for the 3-bit Gray code counter.0it is the least significant bit.

Current state Next state

Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
1 1 0 1 1 1
1 1 1 1 0 1
1 0 1 1 0 0
1 0 0 0 0 0

TABLE 8.7 Table of the next state for the 3-bit Gray code counter.
 DESIGNOFCLOCKSYNCHRONOUS■ 501

Step 3: transition table of the flip-flops

Table 8.8 is a transition table for the J-K flip-flop. All possible output transitions are listed.
Yes, showing how the output of the flip-flop evolves when moving from the current states to the following states.
[Link] is the state present in the flip-flop (before a clock pulse) and Q N+1 it is the following state (des-
after a clock pulse). For each output transition, the inputs JyK are indicated that lead to the
transition. The “X” indicates indifferent conditions (the input can be a 1 or a 0).
When designing the counter, the transition table is applied to each flip-flop of the counter, which is based on
in the following state table (Table 8.7). For example, for the current state 000,Q0 pass from the current state
0 to the next state 1. For this to happen, J0It has to be 1 and the value that K takes is indifferent.0(J0= 1,
K0= X), as indicated in the transition table (Table 8.8). Next, the current state of Q1is 0 and
remains at 0 in the next state. For this transition, J1= 0 yK1= X. Finally, the current state of Q2
is 0 and remains at 0 in the next state. Therefore, J2= 0 yK2= X. This analysis is repeated for each this-
actual defined in Table 8.7.

Exit transitions Flip-flop inputs

QN QN+ 1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
QNcurrent state
QN+1next state
X: 'indifferent' condition

TABLE 8.8 Transition table for a J-K flip-flop.

Step 4: Karnaugh maps

Karnaugh maps are used to determine the logic required for the entries J and K of each flip-flop.
counter flop. A Karnaugh map must be used for input J and another for input K of each
flip-flop. In this design procedure, each cell of the Karnaugh map represents one of the states.
actual of the sequence of the counter listed in Table 8.7.
From the JyK states in the transition table (Table 8.8), a 1, a 0, or an X is introduced in each
cell of the table corresponding to the current state, depending on the transition of the output Q of each flip-flop
in particular. To illustrate this procedure, two input values are shown in Figure 8.29.
plan for the entries0yK0of the least significant flip-flop (Q0).
The complete Karnaugh maps of the three flip-flops of the counter are shown in Figure 8.30.
cells are grouped as indicated, obtaining the corresponding boolean expressions for each
group.

Step 5: logical expressions for the inputs of the flip-flops

From the Karnaugh maps in Figure 8.30, the following expressions for the inputs are obtained.
JyKde each flip-flop:

J 0= Q2Q1+ Q2Q1= Q2⊕ Q1

502 ■ CONTADORES

map of J0 map of K0
Q0 Q0
Q2Q1 0 1 Q2Q1 0 1

The required values of Jy0 K0 00 1 00 X

for the transition to occur
they are placed on each map
in the current status cell. 01 01

11 11

Jy0 K0 10 X 10 1
The required values of
for the transition to take place
they are placed on each map
in the current status cell.

For the current state

000, Q0 make a
Transitions Entries of Current state Next state transition from 0 to
outgoing flip-flop Q2 Q1 Q0 Q2 Q1 Q0 next state 1.
QN QN+1 J K
0 0 0 0 0 1
0 0 0 X 0 0 1 0 1 1 For the current state
0 1 1 X 0 1 1 0 1 0 101 Q0 carry out a
1 0 X 1 0 1 0 1 1 0 transition from 1 to
1 1 X 0 1 1 0 1 1 1 next state 0.
1 1 1 1 0 1
1 0 1 1 0 0
Flip-flop transition table 1 0 0 0 0 0

Table of the following state

FIGURE 8.29 Examples of the procedure for using Karnaugh maps

for the counter sequence represented in Tables 8.7 and 8.8.

K 0= Q2Q1+ Q2Q1= Q2⊕ Q1

J1= Q2Q0
K1= Q2Q0
J 2= Q1Q0
K 2= Q1Q0

Step 6: implementation of the counter

The final step is to implement the combinational logic based on the expressions of the inputs Jy.
To connect the flip-flops to achieve a 3-bit Gray code counter, as shown in the figure.
8.31.
Below is a summary of the steps taken in the design of this counter. In general, these
steps can be applied to any sequential circuit.
1. Specify the counter sequence and draw a state diagram.
2. Obtain the table of the next state from the state diagram.
 SYNCHRONOUS COUNTER DESIGN■ 503

Q0 Q0 Q0
Q2Q1 0 1 Q2Q1 0 1 Q2Q1 0 1

00 0 0 00 0 1 Q2Q0 00 1 X Q2Q1

01 1 0 01 X X 01 0 X
Q1Q0 X X X X X
11 11 11 1 Q2Q1

10 X X 10 0 0 10 0 X

Mapa deJ2 Map of J1 Map of J0

Q0 Q0 Q0
Q2Q1 0 1 Q2Q1 0 1 Q2Q1 0 1

00 X X 00 X X 00 X 0

01 X X 01 0 0 01 X 1 Q2Q1

11 0 0 11 0 1 Q2Q0 0 11 X

10 1 0 10 X X 10 X 1 Q2Q1

Q1Q0 Map of K2 Map of K1 Map of K0

FIGURE 8.30 Karnaugh maps for the inputs JyK of the current state.

FF0 FF1 FF2

Q0 Q2
J0 J1 J2
Q1
C C C
Q0 Q1 Q2
K0 K1 K2

CLK

FIGURE 8.31 3-bit Gray code counter.

3. Develop a transition table showing the flip-flop inputs required for each transition.
The transition table is always the same for each type of flip-flop.
4. Transfer the JyK states from the transition table to the Karnaugh map. Use a map of
Karnaugh for each input of each flip-flop.
5. Form the product terms from the maps to generate a logical expression for each input.
from the flip-flops.
6. Implement the expression with combinational logic and connect it to the flip-flops to create the counter.
Next, in Examples 8.5 and 8.6, this procedure will be applied to the design of other counting-
synchronous processes.
504 ■ COUNTERS

EXAMPLE8.5
Design a counter that performs the irregular binary counting sequence shown in the diagram.
from states of Figure 8.32. Use J-K flip-flops.

001
(1)

111 010
(7) (2)

101
(5)

FIGURE 8.32

Solution Step 1. The state diagram is the one shown in the figure. Although there are only four-
three states, we need a 3-bit counter to implement this sequence-
Hi, given that the maximum binary number is seven. Since the sequence requires...
does not include all possible binary states, the invalid states (0, 3,
4 and 6) can be considered as indifferent in the design. However,
if the counter inadvertently goes through an invalid state, it must ensure that
then it will return to a valid state.
Paso 2. La tabla del estado siguiente se desarrolla a partir del diagrama de estados y se
shown in Table 8.9.

Current state Next state

Q2 Q1 Q0 Q2 Q1 Q0
0 0 1 0 1 0
0 1 0 1 0 1
1 0 1 1 1 1
1 1 1 0 0 1

TABLE 8.9 Table of the following state.

Exit transitions Flip-flop inputs

QN QN+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

TABLE 8.10 Transition table for a J-K flip-flop.

 SYNCHRONOUS COUNTER DESIGN■ 505

Step 3. Table 8.10 repeats the transition table of the J-K flip-flop.
Step 4. Figure 8.33 shows the entries J and K in the Karnaugh maps.
current state. Indifferent conditions (X) can also be included in the
cells corresponding to the invalid states 000, 011, 100, and 110.

Q0 Q0 Q0
Q2Q1 0 1 Q2Q1 0 1 Q2Q1 0 1

00 X 0 00 X 1 1 00 X X 1

01 1 X Q1 01 X X 01 1 X

11 X X 11 X X 11 X X

10 X X 10 X 1 10 X X

Map of J2 Map of J1 Map of J0

Q0 Q0 Q0
Q2Q1 0 1 Q2Q1 0 1 Q2Q1 0 1
Q2
00 X X 00 X X 1 00 X 1

01 X X Q1 01 1 X 01 X X

11 X 1 11 X 1 11 X 0

10 X 0 10 X X 10 X 0

Map of K2 Map of K1 Map of K0

FIGURE 8.33

Q0 Q1 Q2
HIGH HIGH

J0 J1 J2

C C C

K0 K1 K2 Q2

CLK

FIGURE 8.34

Step 5. Group the 1s, using as many indifferent states as possible to

obtain the maximum simplification, as shown in Figure 8.33. Observe
that when all the cells of a table are grouped, the expression is simple-
1. The expression for each entry JyKa from the maps is the one that
continue
506 ■ ACCOUNTANTS

J 0 = 1,K0= Q2
J1= K1= 1
J 2= K 2= Q1

Step 6. The implementation of the counter can be seen in Figure 8.34.

An analysis shows that if the accountant accidentally falls into one of the
Invalid states (0, 3, 4, 6) will always return a valid state accordingly.
with the following sequences 0→ 3→ 4→ 7 and 6→ 1.
Related problem Verifytheanalysisthatdemonstratesthattheaccountant(intheend)willalwayspass.
from an invalid state to a valid state.

EXAMPLE8.6
Develop a 3-bit synchronous up/down counter with a Gray code sequence.
the counter will work in ascending mode when the control input UP/ DOWN sea 1, and will work in
descending mode when the control input is 0.
Solution Step 1. The state diagram is shown in Figure 8.35. The 1 or 0 next to each
Arrow indicates the status of the control input UP/ DOWN ,Y.

1 000 Y= 1

100 0 001
Y= 0
1
1
0 0

101 011

0 0
1
1
111 0 0 010

1 110 1

FIGURE 8.35 State diagram of an ascending/ descending 3-bit Gray code counter.

Step 2. The following state table is obtained from the state diagram and is
presented in Table 8.11. Note that for each current state there are two positions.
the following states, depending on the variable UP/ DOWN of control, Y.
Step 3. The transition table for the J-K flip-flop is repeated in Table 8.12.
Step 4. The Karnaugh maps for the inputs JyK where the flip-flops are presented.
in Figure 8.36. The control input UP/ DOWN ,Y is considered one of
the state variables along with Q0,Q1yQ2. Using the state table
 Synchronous counter design ■ 507

next, the information in the column 'Flip-Flop Inputs' of the Table

8.12 is transferred to the tables indicated for each current state of the counter.

Next state
Current state Y= 0 (DOWN) Y= 1 (UP)
Q2 Q1 Q0 Q2 Q1 Q0 Q2 Q1 Q0

0 0 0 1 0 0 0 0 1
0 0 1 0 0 0 0 1 1
0 1 1 0 0 1 0 1 0
0 1 0 0 1 1 1 1 0
1 1 0 0 1 0 1 1 1
1 1 1 1 1 0 1 0 1
1 0 1 1 1 1 1 0 0
1 0 0 1 0 1 0 0 0

Y= UP/DOWN control input .

TABLE 8.11 Table of the next state of the 3-bit ascending/descending Gray code counter.

Q2Q0Y Q2Q1Y
Q0Y Q0Y Q0Y
A2Q1 00 01 11 10 Q2Q1 00 01 11 10 Q2Q1 00 01 11 10
Q2Q1Y
00 1 0 0 0 00 0 0 1 0 00 0 1 X X

01 0 1 0 0 01 X X X X 01 1 0 X X
Q1Q0Y Q2Q1Y
11 X X X X 11 X X X X 11 0 1 X X

10 X X X X 10 0 0 0 1 10 1 0 X X

Q1Q0Y Map of J2 Map of J1 Map of J0

Q2Q0Y Q2Q1Y

Q2Q0Y
Q0Y Q0Y Q0Y Q2Q1Y
Q2Q1 00 01 11 10 Q2Q1 00 01 11 10 Q2Q1 00 01 11 10

00 X X X X 00 X X X X 00 X X 0 1
Q2Q1Y
01 X X X X 01 0 0 0 1 01 X X 1 0
Q1Q0Y
11 1 0 0 0 11 0 0 1 0 11 X X 0 1

10 0 1 0 0 10 X X X X 10 X X 1 0 Q2Q1Y

Map of K2 Map of K1 Map of K0

Q1Q0Y Q2Q0Y Q2Q1Y

FIGURE 8.36 Maps for JyK according to Table 8.11. The control entry UP/DOWN,
And it is treated as a fourth variable.
508 ■ COUNTERS

Exit transitions Flip-flop inputs

QN QN+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

TABLE 8.12 J-K flip-flop transition table.

Step 5. The 1s are combined into groups as large as possible.

the indifferent conditions (X) whenever possible. They form the
product terms and the following expressions are obtained for the inputs
JyK:

J 0= Q2Q1Y+ Q2Q1Y+ Q2Q1Y+ Q2Q1Y

J1= Q2Q0Y+ Q2Q0Y
J 2= Q1Q0And+ Q1Q0Y

K 0= Q2Q1Y+ Q2Q1Y+ Q2Q1Y+ Q2Q1Y

K1= Q2Q0Y+ Q2Q0Y
K 2= Q1Q0Y+ Q1Q0Y

Step 6. The equations of JyK are implemented with combinational logic, obtain-
having the complete counter shown in Figure 8.37 on page
next.

Related problem. Check that the logic of Figure 8.37 agrees with the expressions of the step
5.

A J-K flip-flop is currently in RESET state and has to change

REVIEW OF
to the SET state in the next clock pulse. What do the values have to be?
SECTION 8.4 What is deJyK?
A J-K flip-flop is currently in a SET state and must remain
in that state during the next clock pulse. What must be the
values ofJyK?
A binary counter is in the state Q3Q2Q1Q0= 1010.
What is the next state?
(b) What condition must exist at each input of the flip-flops to ensure
What happens to the next correct state with the clock pulse?
 Cascading Counters ■ 509

Q2 Q2 Q1 Q1 Q0 Q0

Q0
J0

Q0
K0

Q1
J1

Q1
K1

Q2
J2

C
Q2
K2

CLK

FIGURE 8.37 Three-bit ascending/descending Gray code counter.

8.5 Cascading Counters

The counters can be connected in cascade to work with larger modules. In this...
Hi, cascading connection means that the output of the last stage of a counter excites the input of the
next counter.
510 ■ COUNTERS

At the end of this section, the reader should be able to:

■ Determine the overall modulus of the cascade counters.■ Analyze the timeline diagram of
a configuration of cascade counters.■ Use cascading counters as frequency dividers
sequence.■ Utilizar contadores en cascada para conseguir secuencias específicas truncadas.

The global module An example of two cascaded counters is shown in Figure 8.38.
of the counters in for the case of two counters with propagation of 2 and 3 bits. The timing diagram-
waterfall is equal to Can be seen in Figure 8.39. Note that in the time diagram, the exit-
product of the from the end of the module 8 counter, Q,4, it occurs once for every 32 pulses of
individual modules. entry clock. The global module of the cascade counters is 32, that is, ac-
They act like a division counter by 32.

J0 J1 J2 J3 J4 Q4

CLK C C C C C

K0 K1 K2 K3 K4
Q0 Q1 Q2 Q3

Counter module 4 Modulo 8 counter

FIGURE 8.38 Two cascade counters (all inputs JyK are HIGH level).

CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Q0

Q1

Q2

Q3

Q4

FIGURE 8.39 Timing diagram for the cascading counter configuration in Figure 8.38.

COMPUTER NOTES
The time-stamp counter (TSC) mentioned in the previous computer note is a 64-bit counter.
It is interesting to note that if this counter (or any 64-bit full modulus counter) is given
Applying a frequency of 100 MHz, it will take 5.849 years to go through all its states and reach its value of
terminal count. On the contrary, a full-modulus 32-bit counter will go through all its states in
approximately 43 seconds when a 100 MHz clock signal is applied. The difference is shown-
brother.
 CASCADING COUNTERS ■ 511

When synchronous counters are connected in a cascading configuration, it is necessary to use the fun-
Account activation and account closure actions to be able to work with larger modules. In some
devices, account activation is simply called CTEN (Count Enable) or any other
designation as G, and the end of count signal (TC, Terminal Count) is analogous to the propagation output
clock (RCO) of some counter integrated circuits.
Figure 8.40 shows two decade counters connected in cascade. The count end value (TC)
counter 1 connects to the account enable input (CTEN) of counter 2. Counter 2 is inhibited
be when its entry CTEN is at a LOW level, until counter 1 reaches its final state and the output of
End account value goes to HIGH level. This HIGH level now activates counter 2, so that, when
the first clock pulse is produced after counter 1 reaches its end count value
(CLK10), counter 2 moves from its initial state to its second state. At the end of the second cycle of the counter-
dor 1 (when counter 1 reaches the end count value for the second time), counter 2 is at
new activated and advances to the next state. This sequence repeats indefinitely. Since this is about
decade counters, counter 1 has to go through ten complete cycles before counter 2 starts
completes its first cycle. In other words, for every ten cycles of counter 1, counter 2 completes one.
cycle. Therefore, counter 2 will complete a cycle after 100 clock pulses. The global module of these
two cascading counters is 10× 10= 100.
If we consider it as a frequency divider, the circuit in Figure 8.40 divides the frequency of
Clock input between 100. Cascading counters are often used to divide a clock signal from
high frequency, and obtain impulses of precise frequencies. The configurations of the counters in cascade
Those used for these purposes are sometimes called division chains. For example, suppose that
we have a basic clock frequency of 1 MHz and we want to obtain 100 kHz, 10 kHz, and 1 kHz. To do this,
a series of decade counters can be used in cascade. If the 1 MHz signal is divided by 10, the
The output will have a frequency of 100 kHz. If we then divide the 100 kHz signal by 10, the output will be a
10 kHz signal. Another division by 10 will give the 1 kHz signal. The implementation of these division chains
is shown in Figure 8.41.
HIGH
Counter 1 ƒin Counter 2
10 ƒin
CTEN CTEN TC
100
CTR DIV 10 TC CTR DIV 10
CLK C Q0Q1Q2Q3 C Q0Q1Q2Q3
ƒin

FIGURE 8.40 Module 100 counter, using two cascaded decade counters.

HIGH 100 kHz 10 kHz 1 kHz

CTEN TC CTEN TC CTEN TC

CTR DIV 10 CTR DIV 10 CTR DIV 10
1 MHz C C C

FIGURE 8.41 Three decade counters in cascade form a frequency divider by 1000,
with intermediate outputs of division by 100 and by 10.
512 ■ COUNTERS

EXAMPLE8.7
Determine the global module of the two cascading counter configurations in Figure 8.42.

Entry CTR DIV 8 CTR DIV 12 CTR DIV 16 Exit

(a)

Entrance CTR DIV 10 CTR DIV 4 CTR DIV 7 CTR DIV 5 Exit

(b)

FIGURE 8.42

Solution In Figure 8.42(a), the global module for the configuration of three counting...
it is
8× 12× 16 = 1536
In Figure 8.42(b), the global module for the configuration of four conta-
pain is:
10× 4× 7× 5 =1400
Related problem How many cascading decade counters are needed to divide a
clock frequency around 100,000?

EXAMPLE8.8
Use 74F162 counters to obtain a 10 kHz signal from a 1 MHz clock signal.
Draw the logical diagram.
Solution

D0D1D2D3 D0D1D2D3
SR
PE
(3) (4) (5) (6) (3) (4) (5) (6)
(1) (1)
CTR DIV 10 CTR DIV 10
9 (9)
(7) (15) (7) (15)
+VCC ZIP Code TC CEP TC 10 kHz
(10) 10
CET CET
(2) (2)
C C
(14) (13) (12) (11) (14) (13) (12) (11)
CLK
1 MHz
Q0Q1Q2Q3 Q0 Q1Q2Q3

FIGURE 8.43 Divisor counter by 100 that uses two decade counters 74F162.
 Cascading Counters ■ 513

To obtain 10 kHz from a 1 MHz clock signal, a divider is required.

For a division of 100, two counters need to be connected in cascade.
74F162, as shown in Figure 8.43. The counter on the left produced
there is one impulse for every 10 clock impulses. The counter on the right pro-
generates one pulse TC for every 100 clock pulses.
Related problem Determine the frequency of the output wave.0from the second counter (the one of
the right) in Figure 8.43.

Cascading counters with truncated sequences

The preceding study has shown how to achieve a global module (division factor) that is equal to pro-
duct of the individual modules of the counters connected in cascade. This is called connection in
full module waterfall.
Often, an application requires a global module smaller than what can be achieved with the con-
full module cascade action. That is to say, a truncated sequence with count has to be implemented.
cascading counters. To illustrate this method, we will use the cascading counter configuration of the
Figure 8.44. This particular circuit uses four synchronous 4-bit binary counters 74HC161. If these
four counters (sixteen bits in total) were arranged in a full cascade connection, the
módulo sería:
216 65.536

LOAD
LSD 016 C16 316 616MSD

0 0 0 0 1 1 0 0 0 0 1 1 0 1 1 0
HIGH

D3D2D1D0 D 3 D 2D 1D 0 D 3D 2D 1D 0 D3D2D1D0
ENP ENP ENP ENP
ENT RCO ENT RCO ENT RCO ENT RCO
C C C C
CTR DIV 16 CTR DIV 16 CTR DIV 16 CTR DIV 16

Exit

CLK

FIGURE 8.44 Divisor counter by 40,000 that uses 4-bit binary counters 74HC161. Note that the inputs
data parallels are displayed in binary order (the bit furthest to the right, D0, it is the LSB of each counter).

Let’s assume that a certain application requires a counter-divisor by 40,000 (module 40,000). The
The difference between 65,536 and 40,000 is 25,536, which is the number of states that need to be eliminated from the
full module sequence. The technique used in the circuit of Figure 8.44 is used to initialize the
cascaded counters in state 25.536 (63C0 in hexadecimal) each time a new cycle starts, from
they count from 25,536 to 65,536 in each complete cycle. Therefore, each complete cycle of the
tador has 40,000 states.
Observe in Figure 8.44 that the RCO output of the rightmost counter is inverted and applied to the
LOAD entry of each 4-bit counter. Each time the counter reaches its end count value of
514 ■ COUNTERS

65.535, which is 11111111111111112RCO is set to HIGH and causes the number that is in its entra-
the data parallels (63C016It is loaded into the synchronous counter with the clock pulse. Therefore, it pro-
It gives a pulse to the rightmost 4-bit counter for every 40,000 clock pulses.
With this technique, any module can be achieved by loading the counter with the initial state.
crying in every cycle.

How many decade counters are needed to implement a counter?

REVIEW OF
divisor by 1000 (modulo 1000)? And one divisor by 10,000?
SECTION 8.5
2. Show through general block diagrams how to achieve each of
the following devices, using a flip-flop, a decade counter, a
4-bit binary counter or any combination of these:
Counter divisor by 20 b) Counter divisor by 32
(c) Divisor counter by 160 Divisor counter by 320

8.6 DECODING OF COUNTERS

In many applications, it is necessary to decode some or all of the counter states.
the specification of a counter implies the use of decoders or logic gates to determine
when the counter is in a certain binary state of its sequence. For example, the fun-
The previously studied end-of-account section is a decoding of a single state (the last one)
from the sequence of the counter.
At the end of this section, the reader should be able to:
■ Implement the decoding logic for any state of a counter sequence.
■ Explain why glitches appear in the decoding logic of a counter.■ Use the method-
of validation (strobing) to eliminate glitches in decoding.
Let's assume that we want to decode the binary state 6 (110) of a 3-bit binary counter. When
Q2= 1,Q1= 1 yQ0= 0, a HIGH level appears at the output of the decoding door, indicating that the

HIGH

Q0 Q1 Q2
J0 J1 J2

C C C
Q0 Q1 Q2
K0 K1 K2

CLK
1 1 1
LSB MSB

6 decoded
Q 2Q 1Q 0

FIGURE 8.45 Decoding of state 6 (110).

 DECODING OF METERS ■ 515

EXAMPLE8.9
Implement the decoding of binary states 2 and 7 of a 3-bit synchronous counter. Draw it.
complete timing diagram and the output waveforms of the decoding gates.
2binary= Q2Q1Q0 y 7 binary= Q2Q1Q0.
Solution See Figure 8.46. The 3-bit counter was explained earlier in the
Section 8.2 (Figure 8.14).

HIGH

FF0 FF1 FF2

LSB MSB
Q1
J0 J1 J2 Q2
Q0

C C C
Q0 Q2
K0 K1 K2

CLK

7
2

CLK 1 2 3 4 5 6 7 8

Q0

Q1

Q2

2
Outputs
decoded
7

FIGURE 8.46 3-bit counter with active HIGH decoding for states 2 and 7.

Related problem Implement the decoding logic for state 5 of a 3-bit counter.
516 ■ COUNTERS

The counter is in state 6. This can be carried out as shown in Figure 8.45. This is denoted-
active decoding at HIGH level. By replacing the AND gate with a NAND gate we obtain
an active decoding at a LOW level.

Glitches in the decoding

A glitch is a In Chapter 6, the problem of glitches produced by the process was introduced.
voltage spike no of decoding. As already seen, the propagation delays due to the effect-
desired. the delay in asynchronous counters causes transient states, in which the
The outputs of the counter are varying at slightly different moments in time.
These transient states produce short-duration voltage spikes (glitches) that appear
in the outputs of the decoder connected to the counter. The glitch problem can also appear in
a certain extent in synchronous counters, since the propagation delays between the clock and the outputs Q of
each flip-flop of the counter may differ slightly.
Figure 8.47 shows a basic asynchronous decade BCD counter connected to a BCD decoder.
decimal. To see what happens, we will examine the timing diagram in Figure 8.48, in which
Propagation delays are taken into account. Note that these delays cause short erroneous states.
duration. The value of the false binary state in each critical transition is indicated in the diagram. The glitches
results can be seen in the outputs of the decoder.

CTR DIV 10 BCD/DEC

0
1
Q0 2
1
Q1 3
2 4
Q2
4 5
Q3
6
8
7
8
CLK C
EN 9

FIGURE 8.47 Basic decade counter (BCD) and decoder.

One way to eliminate the glitches is to activate the decoder outputs after the
noise impulses have had time to disappear. This method is known as validation (strobing) and
in the case of a clock signal active at HIGH level, it can be implemented as shown in Figure 8.49,
using the LOW level of the clock to activate the decoder. The improved timing diagram that is
obtained is presented in Figure 8.50.

1. What are the possible transient states when a 4-bit binary counter?
REVIEW OF
asynchronous bits change from
SECTION 8.6
(a) state 2 to 3?
(b) state 3 to 4?
(c)state 1010at 1110?
(d) state 15 to 0?
 DECODING OF COUNTERS ■ 517

CLK 1 2 3 4 5 6 7 8 9 10

Q0

Q1
Outputs
of the counter Q2

Q3
0100 0100
0000 0010 0110 0000 1000
0000
0

Exits 4
of the decoder
5

FIGURE 8.48 Outputs with glitches from the decoder in Figure 8.47. The widths of the glitches are
exaggerated and generally have a value of a few nanoseconds.

CTR DIV 10 BCD/DEC

0
1
Q0 2
1
Q1 3
2 4
Q2
4 5
Q3
6
8
7
8
C EN 9

CLK/STROBE

FIGURE 8.49 Basic decade counter and decoder with strobe validation to eliminate glitches.
518 ■ COUNTERS

CLK/STROBE 1 2 3 4 5 6 7 8 9 10

4
Outings
remove5
decoder
6

FIGURE 8.50 Decoder outputs with validation for the circuit in Figure 8.49.

8.7 APPLICATIONS OF COUNTERS

Digital counters are very versatile and useful devices that can be found in many
applications. This section presents several representative applications of the counters.
At the end of this section, the reader should be able to:
■ Describe how counters are used in a basic digital clock system.■ Explain how it works
implement a divider-counter by 60 and how it is used in a digital clock.■ Explain how to implement
they keep track of the hours.■ Study how to apply a counter in a control system of a
car parking.■ Describe how a counter is used in a conversion process.
parallel-series data

The digital clock

A typical application of counters is time control systems. Figure 8.51 is a
simplified logical diagram of a digital clock, which displays seconds, minutes, and hours.
my place, a sinusoidal alternating current of 60 Hz is transformed into a pulse train at 60 Hz and, later-
mind, it is divided to obtain a pulse train at 1 Hz, using a counter-divider by 60, formed by
a divisor by 10 followed by a divisor by 6. The calculation of minutes and seconds is also generated
through counters-dividers by 60, an operation that can be seen in detail in Figure 8.52. These count-
counters count from 0 to 59 and then return to state 0; in this particular implementation they are used with-
synchronous decade counters. Note that the stage of the divider by 6 consists of a decade counter.
it gives a truncated sequence, achieved using the decoded state 6 to erase, in asynchronous mode
chrono, the counter. The final account value 59 is also coded to activate the next counter of the
chain.
 APPLICATIONS OF COUNTERS ■ 519

Division by 60
60 Hz AC 60 Hz 1 Hz
Circuit of CTR DIV 10 CTR DIV 6
conform
tion of C EN
wave C

FF Hour counter Minute counter (division by 60) Second counter (division by 60)
A CTR DIV 10 CTR DIV 6 CTR DIV 10 CTR DIV 6 CTR DIV 10 EN
C EN EN EN EN
C C C C C

BCD/7-segment BCD/7-segment BCD/7-seg BCD/7-seg BCD/7-segment BCD/7-segment

(0–1) (0–9) (0–5) (0-9) (0–5) (0–9)

Hours Minutes Seconds

FIGURE 8.51 Simplified logical diagram of a 12-hour digital clock. The details of the logical circuit,
with their specific devices, are shown in Figures 8.52 and 8.53.

SR CTR DIV 10 SR SR CTR DIV 6

ZIP CEP
HIGH CET
TC= 9 CET
C
C
Decoder To the next
CLK counter
of 6

TC= 59
The qualification
Decoder
Q3Q2Q1Q0 Q3Q2Q1Q0 (ENABLE) delete
from 59
next counter
Units Tens

FIGURE 8.52 Logical diagram of a 60-divider counter using synchronous decade counters 74F162.
Note that the outputs are in binary order (the rightmost bit is the least significant, LSB).

The hour counter is implemented using a decade counter and a flip-flop, as shown...
see in Figure 8.53. Suppose that, initially, both the decade counter and the flip-flop are
520 ■ COUNTERS

in RESET state, and the decoding gate of state 12 is at HIGH level. The count of decay-
it advances passing through all its states from zero to nine and, when passing from nine to zero to start a
new cycle, the flip-flop swings to the SET state (J= 1, K= 0). This causes a 1 to light up on the display, which
indicate the digit of the tens of hours. The total account value is now 10 (the decade counter is at
zero state and the flip-flop in SET state.
Next, the total number advances to eleven and then to twelve. In state 12, the outputQ2 from the account-
pain of decades is a HIGH level, the flip-flop remains in SET state and, therefore, the output of gate 12
Decoding is at a LOW level. This activates the PE input of the decade counter. In the next pulse-
of the clock, the decade counter is initialized to state 1 through the data inputs, and the flip-
The flop goes to the RESET state (J=0, K=1). As you can see, this logic ensures that the counter always starts.
a new cycle moving from twelve to one, instead of to zero.

0 0 0 1
D3D2D1D0

PE J
CTR DIV 10 Q
74F162
CLK
K

Q3Q2Q1Q0

G1
Decoder of 9 G2
Decoder
of 12
8 4 2 1 8 4 2 1

BCD/7-seg BCD/7-seg
74LS47 74LS47
g f e d c b a g f e d c b a

To the unit digit To the digit of the tens

of the display hours of the display hours

FIGURE 8.53 Logical diagram of the counter and hour decoders. Note that at the inputs
and outputs of the counter, the rightmost bit is the LSB.

Car park control system

Now let's look at a simple application that illustrates how it can solve an ascending/descending counter.
within a daily problem. The problem consists of conceiving a way to control the available slots.
in a parking lot of 100 spaces and, in case it is full, have a warning light turn on and that
A barrier was lowered at the entrance.
A system that solves this problem consists of: (1) optoelectronic sensors at the entrance and
parking exit, (2) an up/down counter and its associated circuitry, and (3) a circuit of
interface that uses the output of the counter to turn the COMPLETE light on or off, as well as to raise it
or lower the entry barrier. Figure 8.54 presents a general block diagram of this system.
 APPLICATIONS OF COUNTERS ■ 521

Indication
Sensor of completely
entry
On/Off
UP
Valorde
CTR DIV 100 Interface
end of Descent/Ascent
DOWN account
Sensor of
exit Activation
of barrier

FIGURE 8.54 Functional block diagram for parking control.

Figure 8.55 shows a logic diagram of the up/down counter. It is made up of

two ascending/descending decade counters 74HC190 connected in cascade. Its operation
describe in the following paragraphs.
▲Increase a The counter is initialized beforehand in state 0 through the data inputs.
counter is to add one in parallel, which are not shown. Each car that enters the parking lot
to the account value. to interrupt the path of a beam of light, activating a sensor that produces a
electric impulse. This positive impulse activates the S-R latch with its leading edge.
The LOW level at the outputQit makes the counter enter the upward working mode. In addition,
The pulse produced by the sensor goes through the NOR gate and applies the clock signal to the counter during
the transition from LOW level to HIGH level of its rear flank. Every time a car enters the parking lot
As cars enter, the counter moves one position forward (it increases). When one hundred cars have entered, the count-
dor reaches its final state (10010The MAX/MIN output is set to HIGH and activates the interface circuit.
(which is not detailed), that turns on the COMPLETE light and lowers the barrier to prevent further entry
cars.

Of
sensor of S
D/U D/U
entry CTR DIV 10 CTR DIV 10
CTEN 74HC190 RCO CTEN 74HC190 MAX/MIN
Of C C (to the interface)
sensor of R at a HIGH level active
Q
output the indication of
COMPLETE and low
the barrier.

FIGURE 8.55 Logical diagram of an up/down counter with a modulus of 100 for parking control.

Decrement a When a car leaves, an optoelectronic sensor produces a positive impulse,

which resets the S-R latch and makes the counter enter descending mode
the counter is to subtract one
to the account value. tooth. The rear side of the clock decreases the number shown by one unit.
that the counter. If the parking lot is full and a car leaves, the exit
MAX/MIN of the counter goes to LOW level, causing the FULL light to disappear and increasing the
barrier.

Parallel-series data conversion (multiplexing)

In Chapter 6 we already presented a simplified example of data transmission using multi- techniques.
multiplexing and demultiplexing. Essentially, the parallel data bits at the inputs of the multiplexer are
522 ■ COUNTERS

they convert into data bits that are transmitted over a single line. Parallel data is referred to as
group of bits that are presented simultaneously over several parallel lines. They are called serial data.
a group of bits that are presented sequentially by a single line.
Normally, the parallel-to-series conversion is done using a counter that provides a sequence.
binary code for the data selection inputs of a multiplexer/data selector, as shown in the Figure
8.56. The outputs of the modulo 8 counter are connected to the data selection inputs of a multiplexer.
8-bit XOR.

CTR DIV 8 MUX

Q0
Q1 0
Selection
Q2 of data
2
CLK C

D0 0 Exit
D1 1 of data
D2 2 in series
Entries D3 3
of data D4 4
in parallel D5 5
D6 6
D7 7

FIGURE 8.56 Logic of parallel-series data conversion.

Figure 8.57 is a timing diagram that shows the operation of this circuit. The first byte
(eight-bit group) of data in parallel is applied to the inputs of the multiplexer. As the counter
advances along its binary sequence from zero to seven, each bit, starting from D0, it is selected
sequentially and passes through the multiplexer to the output line. After eight clock pulses,
the data byte has been converted to serial format and sent over the transmission line. When the
the counter starts a new cycle returning to 0, the next byte is applied to the data inputs and is converted-
sequentially in series format as the counter goes through its eight states. This process continues-
Repeatedly convert each byte from parallel to serial.

COMPUTER NOTES
Computers have an internal counter that can be programmed for different frequencies and lasts
tones, producing 'music'. To select a specific tone, the programmed instruction selects
Set a divisor value that is sent to the counter. The divisor configures the counter so that it divides the frequency.
basic clock sequence of the peripheral, to generate an audio tone. The duration of a tone can also be
define through a program instruction; therefore, a basic counter is used to generate melodies.
controlling the frequency and duration of the tones.

1. Explain the purpose of each NAND gate in Figure 8.53.

REVIEW OF
SECTION 8.7 2. Identify the two conditions to start a new cycle in the hour counter
from Figure 8.51, and explain what they are used for.
 Symbolic connotation of dependency ■ 523

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
CLK

Q0

Selection A1
of data

Q2

D0 1 0

D1 0 0

D2 0 1

D3 1 0
Entrance
of data
D4 1 1

D5 1 0

D6 0 1

D7 1 0

Exit 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0
of data
1hebyte 2nd byte

FIGURE 8.57 Timing diagram of the parallel-to-series conversion of the circuit in Figure 8.56.

8.8 LOGICAL SYMBOLS WITH DEPENDENCY NOTATION

Until now, logical symbols have been introduced in a limited way with notation of
dependencies specified in the ANSI/IEEE Standard 91-1984. In many cases, the new
symbols do not deviate significantly from the traditional ones. However, there are differences with-
considerable on some devices, including meters and other more complex devices, with
regarding what we are used to seeing. Although we will continue to primarily use
the most traditional and familiar symbols throughout the book are provided with a brief description
of the logical symbols with notation of dependence. An integrated circuit is used as an example.
specific counter.
524 ■ COUNTERS

At the end of this section, the reader should be able to:

■ Interpret the logical symbols that include dependency notation.■ Interpret the block
common and the individual elements of the symbol of a counter.■ Interpret the qualifying symbol
action.■ Explain the control dependency.■ Explain the dependency of mode.■ Explain the depen-
Dencia AND.

The dependency notation is fundamental in the ANSI/IEEE standard. The dependency notation is used
liza along with the logical symbols to specify the relationships between inputs and outputs, so that the
The logical functioning of a specific device can be determined entirely from its symbol.
the logical, without any prior knowledge of the details of its internal structure and without the need for any
detailed logical diagram as a reference. This explanation of a specific logical symbol with notation of
dependency aims to assist in the interpretation of other symbols of this kind with which one can
find in the future.
The 4-bit synchronous binary counter 74HC163 is used as an example. To compare, Figure
8.58 shows the traditional block symbol and the ANSI/IEEE symbol with dependency notation. The des-
The basic description of the symbol and the notation of dependence is as follows:

Block
CTR DIV 16 of control
(1) common
CLR 5CT = 0
(9)
D0D1D2D3 LOAD M1
(15)
M2 3CT = 15 RCO
(3) (4) (5) (6) (10)
ENT G3
7
(1) ENP G4
CLR (2)
(9) CLK C5/2,3,4+
LOAD
(10) (15)
ENT CTR DIV 16 RCO
(7) (3) (14)
ENP D0 1, 5 D [1] Q0
(2) (4) 13
CLK C [2] Q1
D1
5 (12)
(14) (13) (12) (11) D2 [4] Q2
(6) (11)
D3 8 Q3
Q0Q1Q2Q3
Traditional symbol (b) Standard logical symbol ANSI/IEEE 91-1984

FIGURE 8.58 The 4-bit synchronous counter 74HC163.

Common control blockThe upper block with the cut corners of Figure 8.58(b) has several entrances.
they are an output that is considered common to all the elements of the device and is not exclusive to any
for element.
Individual elementsThe lower block of Figure 8.58(b), which is divided into four sections, borders
Yes, it represents the four storage elements (D flip-flops) of the counter, whose inputs are D.0,D1,
D2yD3, and whose outputs areQ0,Q1,Q2,yQ3.
Qualification symbolThe label "CTR DIV 16" in Figure 8.58(b) identifies the device as a con-
tador (CTR) with sixteen states (DIV 16).
Control Dependency (C)As shown in Figure 8.58(b), the letter C denotes control dependence.
Control inputs usually activate or deactivate the data inputs (D, J, K, SyR) of an element.
 FAULT LOCATION ■ 525

to storage. The input is usually the clock input. In this case, the digit 5 that follows C
(C5/2,3,4+) indicates that the entries labeled with a prefix 5 depend on the clock (they are synchronized with
the clock). For example, 5CT = 0 in the inputCLR it indicates that the erase function depends on the clock; that is,
it is a synchronous clear input. When the clear input is LOW (0), the counter is set to zero
(CT= 0) on the rising edge of the clock pulse. In addition, the 5D label at the input of the element
Storage [1] indicates that data storage depends on the clock (it is synchronized with the clock).
All the labels in the storage element [1] also apply to elements [2], [4], and [8] that
they are situated below, as no different notation is indicated on them.
DependencyMode(M)As shown in Figure 8.58(b), the letter Mindica mode dependency. It
used to indicate how the functions corresponding to several inputs or outputs depend on the way in which
the device is functioning. In this case, the device has two operating modes. When the
entryLOAD is at LOW level (0), as indicated by the entry triangle, the counter is at
loading mode (M1) in which the input data (D0,D1,D2yD3they are introduced synchronously into the
four flip-flops. The digit 1 behind M(M1) and the 1 on label 1, 5 D show a relationship of dependence.
And they indicate that the input data is only stored when the device is in charging mode.
(M1), in which LOAD= 0. When the LOAD input is HIGH (1), the counter advances through
su secuencia binaria normal, como se indica mediante M2 y el 2 en C5/2,3,4+.
DependencyAND(G)As shown in Figure 8.58(b), the letter G denotes AND dependence, which indicates that
an AND operation is performed between an input, designated with the letter G followed by a digit, on one side,
and any other input or output that has the same digit as a prefix in its label. In this example in
particular, G3 at the entrance ENT and 3CT= 15 in the output RCO are related, as indicated by the digit 3, and
this relationship is an AND dependency, as indicated by G. This tells us that ENThas to be a HIGH level
(no triangle at the entrance) and that the counter state must be fifteen (CT)= 15) so that the outputRCO
be a HIGH level.
In addition, the digits 2, 3, and 4 in the label C5/2,3,4+ indicate that the counter advances through its th
until when LOAD= 1, as indicated by the M2 mode dependency label, and when ENT= 1
yENP= 1, as indicated by the dependency labels AND G3 and G4. The plus sign (+) indicates that the
the counter increases when this condition exists.
This description of a logical symbol with specific dependency notation aims to assist in the inter-
interpretation of other similar symbols that may be encountered in the future.

1. In the dependency notation, what do the letters C, MyG mean?

REVIEW OF
SECTION 8.8 2. Which letter indicates data storage?

8.9 FAULT LOCATION

The location of faults in the meters can be simple or very complicated, depending on the type.
of the counter and the type of failure. This section will provide us with some practice in problem-solving
of problems in sequential circuits.
At the end of this section, the reader should be able to:
■ Detecting faults in a meter.■ Isolate the failures in the maximum modulus cascade counters.
■ Isolatethe failures in the cascading counters with truncated sequence.■ Determine the failures in the
counters implemented with individual flip-flops.
526 ■ COUNTERS

Counters
In a counter that has a sequence that is not controlled by any external logic, the only thing that
it can be verified (apart from VCCand land) is the possibility of having inputs or outputs in an open circuit or
short-circuited. A CI counter almost never alters its sequence of states due to an internal failure, so
that the activity of the pulses at the outputs Q should only be checked to detect the existence of cir-
open circuits or short circuits. The absence of pulse activity in one of the outputs indicates that there is
an open circuit or an internal short circuit. The absence of pulse activity at all outputs.
that the clock input is failing or the clear input remains in its active state.
To verify the erase input, a constant active level is applied to it while the signal ...
of clock. If a LOW level is obtained at each of the outputs Q, the operation is correct.
The parallel load capacity of a counter can be checked by activating the parallel load input.
and testing each of the states in the following way: low levels are applied to the data inputs in
parallel, impulses at the clock input and it is checked that there are low levels at all outputs.
continuation, high levels are applied to the parallel data inputs, pulses are introduced into the input of
watch and check that there are high levels at all outputs.

Cascading counters with maximum module

A failure in one of the counters in a cascade of counters can affect all the others.
accountants that follow him. For example, if the account activation entry of an accountant is in circuit
open, acts as if it were a HIGH level (in TTL) and the counter will always be active. This type of failure
in one of the counters will make that counter work at maximum clock speed and also that all
the other counters that follow it operate at speeds greater than normal. This is illustrated in the
Figure 8.59 for a cascade counter-divider by 1000, where a counting enable input
(CTEN) in open circuit acts as a HIGH TTL level and continuously activates the second counter. Another
the faults that can affect the "secondary stages" of counters can be clock inputs or
open circuit or short-circuited end-of-account value outputs. In some of these situations, there

100 kHz 10 kHz

1 kHz

HIGH CTEN TC CTEN TC CTEN TC

CTR DIV 10 CTR DIV 10 CTR DIV 10
C C C

1 MHz
Normal operation

100 kHz OPEN (acts as 100 kHz

10 kHz
a HIGH level)

HIGH CTEN TC CTEN TC CTEN TC

CTR DIV 10 CTR DIV 10 CTR DIV 10
C C C

1 MHz
The account enabling input (CTEN) of the second counter is in open circuit.

FIGURE 8.59 Example of failure affecting successive counters in a cascading configuration.

 FAULT LOCATION ■ 527

You can observe impulse activity, but at incorrect frequencies. In this case, measurements will need to be taken.
the exact frequencies.

Cascading counters with truncated sequences

The sequence of numbers from a cascading counter with a truncated sequence, like that in Figure 8.60,
it can lead to other types of failures, in addition to those mentioned for cascade counters of mod-
the maximum. For example, a failure in one of the parallel data inputs, the LOAD input or the inverter
they can alter the initialization value and thus change the counter module.

OPEN
LOAD
016 C16 316 616
0 0 0 0 1 1 0 0 0 0 1 1 0 1 1 0

HIGH
D3D2D1D0 D3D2D1D0 D3D2D1D0 D3D2D1D0
CTEN TC CTEN TC CTEN TC CTEN TC
CTR DIV 16 CTR DIV 16 CTR DIV 16 CTR DIV 16
C C C C

1 MHz Less significant More significant

138.3 Hz

FIGURE 8.60 Example of failure in a cascading counter with truncated sequence.

For example, let's assume that the inputD3the most significant counter in Figure 8.60 is in cir-
open circuit and acts as a HIGH level. So, instead of performing the reset in state 616
(0110), will take place in state E16In this way, instead of starting at 63C016(25.53610), every time
that the counter starts a new cycle, the sequence will begin at E3C016(58.30410This causes the variation of the
counter module from 40,000 to 65,536− 58.304 = 7232.
To check this counter, a known clock frequency is applied, for example, 1 MHz, and it is measured.
the output frequency at the terminal of the account ending value. If the counter is functioning properly.
mind, the output frequency will be:

fin 1MHz
fout = = = 25Hz
module 40,000

In this case, the specific fault described in the previous paragraph will cause the output frequency to be:

fin 1MHz
fout = = = 138.3Hz
module 7232

EXAMPLE8.10
Frequency measurements are made on the truncated counter in Figure 8.61 as indicated.
Determine if the counter is functioning properly and, if not, identify what the failure is.
528 ■ COUNTERS

LOAD
016 C16 216 816

0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0

D3D2D1D0 D 3D 2D 1D 0 D3D2D1D0 D3D2D1D0

HIGH CTEN TC CTEN TC CTEN TC CTEN TC
CTR DIV 16 CTR DIV 16 CTR DIV 16 CTR DIV 16
C C C C

CTR1 CTR2 CTR3 CTR4

TC 4

MHz Hz

FIGURE 8.61

Solution It is verified that the frequency measured in TC 4 is correct. If so, the

The counter is working perfectly.

truncated module= complete module− initialization value

= 164− 82C016
= 65.536− 33.472= 32.064

The correct frequency in TC 4 is

10MHz
f 4= = 311.88 Hz
32.064

However, when measuring, we detected that there is a problem. The frequency medi-
the 637.76 Hz does not match the correctly calculated frequency of 311.88
Hz.
To check the failing counter, the real truncated modulus of the
next way:

fin 10MHz
module= = = 15.680
fout637,76Hz

Since the truncated module has to be 32.064, it is most likely that

the initialization of the counter is being done with an incorrect value when it
a new cycle begins. The actual initialization value is determined in the way-
the following:

truncated module= complete module− initialization value

initialization value= complete module− truncated module
= 65.536−15.680
= 49.856
= C2C016
 FAULT LOCATION ■ 529

This shows that the initialization value of the counter is, every time it is ini-
there is a new cycle, C2C016instead of 82C016
The loading of counters 1, 2 and 3 is done correctly, but not that of the con-
tador 4. Given that C16equals 11002the entranceD2the counter 4 is at HIGH level
when it should be at LOW level. It is most likely that this failure is caused
suffered due to an open circuit entry. You must also check a circuit.
external open circuit caused by a bad soldering in the connections, a
broken conductor or a bent pin of the integrated circuit. If no one is detected
In case of these failures, the CI must be replaced and the counter will function correctly.
mind.
Related problem Determine what the output frequency would be in TC 4 if the input is D3the with-
Tador 3 would be in open circuit.

Counters implemented with individual flip-flops

The counters implemented with individual flip-flops and gate integrated circuits are, some
times, harder to verify in case of failure, since there are many more inputs and outputs with connection-
external nets, which in a CI counter. The sequence of a counter can be altered by the presence of a unique
open circuit or a short circuit at an input or output, as shown in Example 8.11.

Cuando se observa la relación temporal entre dos señales digitales en un osciloscopio de

ADVICE
dual trace, the proper way to trigger the oscilloscope is using the slowest signal
PRACTICALS from the two. The reason for this is that the slower signal has fewer points of dis-
I stop when the signal is fastest, so there will be no ambiguity at the start of the sweep.
The shot in vertical mode uses a signal composed of both channels and never does
should be used to determine absolute temporal information. Given that, generally-
The clock signals are the fastest in a digital system, they should not be used.
for the shot.

EXAMPLE8.11
Suppose that the output waveforms shown are observed for the counter in the Figure
8.62. Determine if there is a problem with the meter.
Solution The waveformQ2It is incorrect. The correct waveform is indicated
through a dashed line. You can observe that the waveformQ2has
exactly the same way as Q1This indicates that the same signal that is
making FF1 tilt also controls FF2.
If we check the entries JyK of FF2, we find a signal that
it has the same shape as Q0This result indicates that Q0pass of some
way through the AND gate. This can only occur if the input Q1of
the AND door is always at HIGH level. But we just saw thatQ1has
a correct waveform. This observation leads us to the conclusion that
that the lower input of the AND door must be, internally, in cir-
open cavity, so it acts as a HIGH level. It is necessary then
replace the AND gate and recheck the circuit.
530 ■ COUNTIES

CLK

Q0

Q1

Q2

HIGH
FF0 FF1 FF2
Q0 Q2
J0 J1 J2
Q1
C C C

K0 K1 K2

CLK

FIGURE 8.62

Related problem Describe the output2of the counter in Figure 8.62 if the output Q1from FF1 is
in open circuit.

1. What are the failures that can cause the counter in Figure 8.59 not to work?
REVIEW OF
Is there any pulse activity on any of the TC outputs?
SECTION 8.9
2. What happens if the inverter in Figure 8.61 has an open circuit output?

In Chapter 7, the circuits have been developed

timing.
This chapter addresses sequential logic and
they connect all the blocks to generate the system of con-
complete control of the traffic lights. Again, the
global block diagram of the system is shown in the
Figure 8.63.

Requirements of
sequential logic
APPLICATION TO THE
DIGITAL SYSTEMS Sequential logic controls the sequencing of the
traffic light lights based on the inputs proce-
El sistema de control de luces de los semáforos que se ha teeth of the timing circuits and of the sensor of
started in Chapter 6 and with which it has continued in vehicles. The sequential logic will generate a sequence of
Chapter 7 is completed in this chapter. In Chapter 2-bit Gray code for the four states of the system
6 combinational logic has been developed. indicated in Figure 8.64.
 APPLICATION OF DIGITAL SYSTEMS■ 531

Traffic light control logic Traffic light and

interface unit
Combinational logic
MR
Sequential logic
MY
Entry S0
from the sensor Code
Gray MG
of vehicles S1
SR

SY

SG
Temp. Temp. Clock
short long
Long shot
Circuits of
timing Short shot

It is completed in It is completed on the It is completed in

Chapter 6. Chapter 7. this chapter.

FIGURE 8.63 Block diagram of the traffic light control system.

Princ. Sec. Principal. Sec. Princ. Sec. Princ. Sec.

Red Red Red Red

Amber Amber

Green Green

First state Second state Third state Fourth state

FIGURE 8.64 Sequence of states of the traffic lights.

Block diagram The sequential logic consists of a counter is the 10 kHz signal produced by the oscillator
2-bit Gray code counter and the input logic of the timing circuits.
associated, as shown in Figure 8.65. State diagram The system's state diagram
The counter generates a sequence of four states. it has been introduced in Chapter 6 and is shown again
The transitions from one state to the next are determined in Figure 8.66. Based on this state diagram,
mined by the 4 s timer, by the timer of the functioning of the logic is described below
25 seconds and for the vehicle sensor entrance. The clock of the sequential.
532 ■ COUNTERS

TS S0
Logic of Counter code To the decoder
TL
input 2-bit Gray
Vs S1 of states

CLK
TS: Temporizador corto (4 s)
TLLong timer (25 s)
VsVehicle sensor of the secondary street

FIGURE 8.65 Block diagram of sequential logic.

TL+Vs

First
state 00
Princ.: verde
TS Section: red TLVs

Fourth Second
state 10 state 01
TS TS
Princ.: red Amber
amber red

Third
TL+V s TS
state 11
Princ.: red
Section: green

TLVs

FIGURE 8.66 State diagram of the traffic light control system.

First state The Gray code for this state is 00. Second state The Gray code for this state is 01.
the traffic light on the main street is green and the one for The traffic light on the main street is amber and the
the secondary street is in red. The system remains in The secondary street is in red. The system remains
this state for at least 25 s when the timer in this state for 4 s when the short timer
long is active while there are no vehicles in the is activated (TS) and moves to the next state when this
secondary street. This is expressed as TL+ VS The system same timer deactivates (TS).
switch to the next state when the long timer is
disabled and there is a vehicle on the secondary street. This Third state The Gray code for this state is 11.
is expressed as (TLVS ). the traffic light on the main street is red and the one on the
 APPLICATION OF DIGITAL SYSTEMS■ 533

The secondary street is green. The system remains in oscillator. The input logic has five variables of
this state when the long timer is activated and Entry: Q0,Q1,TL,TSyVS.
There is a vehicle on the side street. This is expressed. Table 8.13 shows the transition table of
howLVSThe system moves to the next state when it flip-flop D. From the state diagram, it can be ...
disable the long timer or when there are no vehicles roll up the state table as shown in
on the secondary street, what is indicated as TL+ VS Table 8.14. The entry conditions for TL,TSyVS
for each combination of current state/next state
Fourth state The Gray code for this state is 10. they are listed in the table.
the traffic light on the main street is red and the one of the
The secondary street is in amber. The system remains in
this state for 4 s when the short timer is Exit transitions Flip-flop inputs
activated(TS) and returns to the initial state when the timer- QN QN+1 D
short zador is deactivated(TS). 0 0 0
Implementation of sequential logic The diagram of 0 1 1
Figure 8.67 shows that two D flip-flops are used.
1 0 0
to implement the Gray counter. The outputs of the logic-
As input they provide the entries Give the flip-flops 1 1 1
and the counter is synchronized by the 10 kHz clock of the
TABLE 8.13 D flip-flop transition table.

Current status Next state FF Entry Conditions

Q1 Q0 Q1 Q0 to start with D1 D0

0 0 0 0 TL+ Vs 0 0
0 0 0 1 TLVS 0 1
0 1 0 1 TS 0 1
0 1 1 1 TS 1 1
1 1 1 1 TLVs 1 1
1 1 1 0 TL+ Vs 1 0
1 0 1 0 TS 1 0
1 0 0 0 TS 0 0

TABLE 8.14 Table of the next state for the transitions of sequential logic.

S0
To the decoder
TS
TL
Logic of S1 of states
entry
Vs D0 D1
Q0 Q1
C C

Clock at 10 kHz

FIGURE 8.67 Diagram of sequential logic.

534 ■ COUNTERS

From Tables 8.13 and 8.14 it can be determined A Karnaugh map can be used to further reduce
the logical conditions required for each flip-flop more the expression of D1
I passed to state 1. For example, Q0it goes from 0 to 1 when the
the current state is 00 and the input condition is TLVS , D1= Q0TS+ Q1TS
as indicated in the second row of Table 8.13.D0must
be at 1 to make that0pass to 1 or remain at 1 in D0yD1they are implemented as shown in Figure
the next clock pulse. For thatD0be a 1, can 8.68.
write a logical expression based on Table 8.14: Combining the input logic with the 2 counter
bits, the complete sequential logic diagram is obtained
D0= Q1Q0TLVs+ Q1Q0TS shown in Figure 8.69.

+Q1Q0TS+ Q1Q0TLVs
= Q1Q0TLVs + Q1Q0+ Q1Q0TLVs Complete control system of
the traffic lights
A Karnaugh map can be used to further simplify
more the expression ofD0 Now that we have the three blocks (combi logic-
national, timing circuits and sequential logic
D0= Q1TLVs+ Q1Q0+ Q0TLVs let's combine them to form the complete system,
whose block diagram is shown in Figure 8.70.
We can also develop the expression of D.1from
from Table 8.14, Interface circuits are necessary
rivers because logic cannot directly control the
D1= Q1Q0TS+ Q1Q0TLVs lights due to current and voltage requirements.
+Q1Q0TL+ Q1Q0Vs+ Q1Q0TS There are several ways to provide an interface and
They provide two possible designs in Appendix B.
= Q1Q0TS+ Q1Q0(TLVs+ TL)
+Q1Q0Vs+ Q1Q0TS
= Q1Q0TS+ Q1Q0(Vs + TL)
Systems practice
+Q1Q0Vs+ Q1Q0TS ■ Activity 1 Use a Karnaugh map to con-
= Q1Q0TS+ Q1Q0(Vs+ TL+ Vs ) to state that the simplified expression of D0It is correct.
+Q1Q0TS ■ Activity 2 Use a Karnaugh map to
= Q1Q0TS+ Q1Q0+ Q1Q0TS to affirm that the simplified expression of D1it is correct.

Q1

TL
Vs
D0
Q0

TS
D1

FIGURE 8.68 Input logic for the 2-bit Gray code counter.
 SUMMARY■ 535

TL
Vs
D0Q0 S0

C
Code
Gray

TS
D1Q1 S1

Watch

FIGURE 8.69 The sequential logic.

Traffic light control logic Traffic light and

interface unit
Combinational logic
MR
Sequential Logic
MY
Entry S0
from the sensor Code
Gray MG
of vehicles S1
SR

SY

SG
Temp. Temp. Clock
short long
Long shot
Circuits of
timing Short shot

FIGURE 8.70 Block diagram of the traffic light control system.

SUMMARY

■ As shown in Figure 8.71, synchronous and asynchronous counters only differ

they are applied to the clock signal. Synchronous counters can operate at
Clock frequencies higher than asynchronous counters.
536 ■ COUNTERS

HIGH HIGH HIGH

Q Q
J J Q J J Q

CLK C C CLK C C

K K K K

Asynchronous Synchronous

FIGURE 8.71 Comparison of synchronous and asynchronous counters.

■ Figure 8.72 shows the connections of the presented counter integrated circuits.
in this chapter.

14 13 12 11 10 9 8 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9

Q0 Q3 Q1 TC Q0Q1Q2Q3 CET RCO Q0 Q1Q2Q3 ENT

C
CTR DIV 16 Q2 SR CTR DIV 10 PE CLR CTR DIV 16 LOAD
C
RO(1)RO(2) C D0 D1D2D3 ZIP code C D0 D1D2D3 ENP

1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

Asynchronous binary counter Synchronous BCD decade counter with 4-bit synchronous binary counter with
4-bit 74LS93 asynchronous erase input 74F162 asynchronous clear input 74HC161

16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9

RCO Q0 Q1Q2Q3 ENT D0 C RCO MAX/LOAD D2

MIN

CLR CTR DIV 16 LOAD D1 CTR DIV 10 D3

C D0 D1D2D3 ENP Q1Q0 G DN/UP Q2 Q3

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

4-bit synchronous binary counter with Ascending/Descending Decade Counter

synchronous clear input 74HC163 synchronous 74HC190
(Account activation)

FIGURE 8.72 Note that the labels (names of the inputs and outputs) are consistent with the text.
but they may differ from the manufacturer's catalog you are using. The devices shown are
functionally identical and pin compatible with devices of the same type
available in other CMOS and TTL families of integrated circuits.

■ The maximum module of a counter is the maximum number of possible states and is a function of
number of stages (flip-flops). Therefore,
Maximum module = 2n

give the number of stages of the counter. The modulus of a counter is the real number of this
Two of the sequence, and it can be equal to or less than the maximum module.