IA/DSC/T/101

DIGITAL ELECTRONICS
MODULE III

Basic combinational logic circuits

Implementing combinational logic
NAND and NOR
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and NOR
 Combinational Logic Analysis

Combinational Logic Circuits

In Sum-of-Products (SOP) form, basic combinational circuits

can be directly implemented with AND-OR combinations if
the necessary complement terms are available.

Product terms
A
AB
B
C CD
D AB + CD + . . . + JK
Sum-of-products
J
JK
K
Product term

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Slide 5
 Combinational Logic Analysis

Combinational Logic Circuits

An example of an SOP implementation is shown. The SOP

expression is an AND-OR combination of the input variables
and the appropriate complements.

A
B ABC
C X = ABC + DE SOP

D
DE
E

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Slide 6
 Combinational Logic Analysis

Combinational Logic Circuits

When the output of a SOP form is inverted, the circuit is called

an AND-OR-Invert (AOI) circuit. The AOI configuration lends
itself to product-of-sums (POS) implementation.
An example of an AOI implementation is shown. The output
expression can be changed to a POS expression by applying
DeMorgan’s theorem twice.
A
B ABC
C X = ABC + DE X = ABC + DE AOI

D X = (ABC)(DE) DeMorgan
E DE X = (A + B + C)(D + E) POS

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Slide 7
 Combinational Logic Analysis

Exclusive-OR Logic
Inputs Output
The truth table for an exclusive-OR gate is A B X
Notice that the output is HIGH whenever 0 0 0
0 1 1
A and B disagree. 1 0 1
1 1 0
The Boolean expression is X = AB + AB
The circuit can be drawn as
A
Symbols:
X =1

Distinctive shape Rectangular outline

B

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Slide 8
 Combinational Logic Analysis

Exclusive-NOR Logic
Inputs Output
The truth table for an exclusive-NOR gate is A B X
0 0 1
Notice that the output is HIGH whenever 0 1 0
A and B agree. 1 0 0
1 1 1
The Boolean expression is X = AB + AB
The circuit can be drawn as
A Symbols:
X
B
=1

Distinctive shape Rectangular outline

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Slide 9
 Combinational Logic Analysis

For each circuit, determine if the LED should be on or off.

+5.0 V
+5.0 V
+5.0 V +5.0 V
+5.0 V +5.0 V
330 W
330 W
330 W
B LED
LED B LED
B
A
A A

(a) (b) (c)

Circuit (a): XOR, inputs agree, output is LOW, LED is ON.

Circuit (b): XNOR, inputs disagree, output is LOW, LED is ON.
Circuit (c): XOR, inputs disagree, output is HIGH, LED is OFF.

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Slide 10
 Implementing Combinational Logic

Implementing Combinational Logic

Implementing a SOP expression is done by first forming the
AND terms; then the terms are ORed together.
Show the circuit that will implement the Boolean expression
X = ABC + ABD + BDE. (Assume that the variables and
their complements are available.)
Start by forming the terms using three 3-input AND gates.
Then combine the three terms using a 3-input OR gate.
A
B
C
A X = ABC + ABD + BDE
B
D
B
D
E
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Slide 11
 Implementing Combinational Logic

Karnaugh Map Implementation

For basic combinational logic circuits, the Karnaugh map
can be read and the circuit drawn as a minimum SOP.
A Karnaugh map is drawn from a truth table. Read the
minimum SOP expression and draw the circuit.

C C
1. Group the 1’s into two overlapping
AB 1
B changes groups as indicated.
across this AB 1 1 2. Read each group by eliminating any
boundary variable that changes across a boundary.
AB 3. The vertical group is read A C.
C changes 4. The horizontal group is read AB.
AB
across this
boundary The circuit is on the next slide:
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Slide 12
 Implementing Combinational Logic

continued…
Circuit: A
C X= AC + AB
A
B

The result is shown as a sum of products.

It is a simple matter to implement this form using only
NAND gates as shown in the text and following example.

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Slide 13
 The Universal Property
of NAND and NOR Gates

NAND and NOR gates are “universal” because they

can used to produce any of the other logic functions.

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Slide 14
 Combinational Logic Analysis
Inputs Output
Universal Gates A B X
0 0 1
NAND gates are sometimes called universal 0 1 1
gates because they can be used to produce 1 0 1
the other basic Boolean functions. 1 1 0

A A A AB
B
Inverter AND gate

A A
A+B A+B
B B

OR gate NOR gate

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 Combinational Logic Analysis
Inputs Output
Universal Gates A B X

NOR gates are also universal gates 0 0 1

0 1 0
and can form all of the basic gates. 1 0 0
1 1 0

A A+ B
A A
B
Inverter OR gate

A A
AB AB
B B

AND gate NAND gate

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Slide 16
 Combinational Logic Analysis
continued…Slide 12
Circuit:
C C A

1 C X= AC + AB
AB
B changes
across this A
AB 1 1
boundary B

AB
A
C changes
AB C
across this X= AC + AB
boundary A
B
Recall from Boolean algebra that double inversion cancels. By adding
inverting bubbles to above circuit, it is easily converted to NAND gates.
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Slide 17
 Combinational Logic Analysis

NAND Logic
Recall from DeMorgan’s theorem that AB = A + B.
By using equivalent symbols, it is simpler to read the logic of
SOP forms. The earlier example shows the idea:
A
C Inputs Output
X= AC + AB
A B AB A + B
A
0 0 1 1
B 0 1 1 1
1 0 1 1
The logic is easy to read if you (mentally) 1 1 0 0
cancel the two connected bubbles on a line.
A A
AB A+B
B B

NAND Negative-OR
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Slide 18
 Combinational Logic Analysis

NOR Logic
Alternatively, DeMorgan’s theorem can be written as A + B = AB.
By using equivalent symbols, it is simpler to read the logic of POS
forms. For example,
A Inputs Output
B A B A + B AB
X = (A + B)(A + C)
0 0 1 1
A 0 1 0 0
C 1 0 0 0
1 1 0 0
Again, the logic is easy to read if you
cancel the two connected bubbles on a line.
A A
A+B AB
B B

NOR Negative-AND
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Slide 19
 Combinational Logic Analysis

Pulsed Waveforms
For combinational circuits with pulsed inputs, the output
can be predicted by developing intermediate outputs and
combining the result. For example, the circuit shown can
be analyzed at the outputs of the OR gates:

A
A
G1
B B
G3
C
C
G2
D D
G1
G2
G3

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Slide 20
 Combinational Logic Analysis

Pulsed Waveforms
Inputs Output
Alternatively, you can develop the truth table for
A B C D X
the circuit and enter 0’s and 1’s on the waveforms.
Then read the output from the table. 0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
A
G1 0 0 1 1 1
B 0 1 0 0 0
G3 1
0 1 0 1
C 0 1 1 0 1
G2
D 0 1 1 1 1
1 0 0 0 0
A 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0
1 0 1 0 0
B 0 1 1 0 0 1 1 0 0 0 1 0 1 1 0
1 1 0 0 0
C 0 0 0 1 1 1 1 0 0 0
1 1 0 1 1
D 0 0 0 0 0 0 0 1 1 0 1 1 1 0 1
1 1 1 1 1
G3 0 0 0 0 1 1 1 0 1 0
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Slide 21
 Combinational Logic Analysis

Universal gate Either a NAND or a NOR gate. The term universal

refers to a property of a gate that permits any logic
function to be implemented by that gate or by a
combination of gates of that kind.
Negative-OR The dual operation of a NAND gate when the
inputs are active-LOW.

Negative-AND The dual operation of a NOR gate when the inputs

are active-LOW.

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Slide 22
 QUIZ
Analyze the Output of the shown Circuit Using timing
diagram and truth tables for the input waveforms.

A
A
G1
B B
G3
C
C
G2
D D

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Slide 23
 IA/DSC/T/101

DIGITAL ELECTRONICS
MODULE III

Basic adder
Encoder Decoder
Multiplexer
Demultiplexer
[Link] INDUSTRIAL AUTOMATION Page 21 of 111
 Combinational Logic - Basic Adders

Half-Adder
Inputs Outputs
Simple Binary Addition A B Cout S
0 0 0 0
0+0=0 Zero plus zero equals zero 0 1 0 1
1 0 0 1
1 1 1 0
0+1=1 Zero plus one equals one
1+0=1 One plus zero equals one
1 + 1 = 10 One plus one equals zero with a carry of one

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Slide 3
 Combinational Logic - Basic Adders

Half-Adder

Basic rules of binary addition are performed by a half adder,

which has two binary inputs (A and B) and two binary outputs
(Carry out and Sum).

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Slide 4
 Combinational Logic - Basic Adders

Full-Adder
By contrast, a full adder has three binary inputs (A, B, and Carry
in) and two binary outputs (Carry out and Sum).

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Slide 5
 Combinational Logic - Basic Adders

Full-Adder

A full-adder can be constructed from two half adders as shown:

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Slide 6
 Combinational Logic - Basic Adders

Full-Adder S S 0 Sum
1 A S 1 A S

1
0 B Cout 0 B Cout

1 Cout
1
For the given inputs, determine the
intermediate and final outputs of the full adder.

The first half-adder has inputs of 1 and 0;

therefore the Sum =1 and the Carry out = 0.
The second half-adder has inputs of 1 and 1; therefore the
Sum = 0 and the Carry out = 1.
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Slide 7
 Combinational Logic - Basic Adders

Full-Adder

Notice that the result from the previous example can be

read directly on the truth table for a full adder.

Inputs Outputs
S S 0 Sum
A B Cin Cout S 1 A S 1 A S
0 0 0 0 0
1
0 0 1 0 1
0 B Cout 0 B Cout
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1 1 Cout
1 0 1 1 0
1 1 0 1 0 1
1 1 1 1 1

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Slide 8
 Combinational Logic - Parallel Binary Adders

Parallel Adders

Full adders are combined into parallel adders that can add binary
numbers with multiple bits. A 2-bit adder is shown.

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Slide 9
 Combinational Logic - Parallel Binary Adders

Parallel Adders

Full adders are combined into parallel adders that can add binary
numbers with multiple bits. A 4-bit adder is shown.
A 4 B4 A3 B3 A2 B2 A1 B1

C0

A B Cin A B Cin A B Cin A B Cin

Cout S Cout S Cout S Cout S

C4
C3 C2 C1
S4 S3 S2 S1

The output carry (C4) is not ready until it propagates through

all of the full adders. This is called ripple carry, delaying the
addition process.
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Slide 10
 Combinational Logic - Parallel Binary Adders

Parallel Adders
The logic symbol for a 4-bit parallel adder is shown. This 4-bit
adder includes a carry in (labeled (C0) and a Carry out (labeled C4)
S
1 1
Binary 2 2 4-bit
number A 3 3 sum
4 4
1
Binary 2
number B 3
4
Input Output
C0 C4
carry carry

The 74LS283 is an example. It features look-ahead carry, which

adds logic to minimize the output carry delay. For the 74LS283,
the maximum delay to the output carry is 17 ns.
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Slide 11
 Combinational Logic - Comparators

Comparators
The function of a comparator is to compare the magnitudes of
two binary numbers to determine the relationship between them.
In the simplest form, a comparator can test for equality using
XNOR gates.

The output is 1 when the inputs are equal

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Slide 12
 Combinational Logic - Comparators

Comparators
2-bit Comparator

The output is 1 when A0 = B0 AND A1 = B1

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Slide 13
 Combinational Logic - Comparators

Comparators

How could you test two 4-bit numbers for equality?

AND the outputs of four XNOR gates.

A1
B1
A2
B2 Output
A3
B3
A4
B4

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Slide 14
 Combinational Logic - Comparators

Comparators
IC comparators provide outputs to indicate which of the numbers
is larger or if they are equal. The bits are numbered starting at 0,
rather than 1 as in the case of adders. Cascading inputs are
provided to expand the comparator to larger numbers.
COMP
A0 0
A1 A
A2
A3 3
Cascading A>B A>B
A=B A=B Outputs
inputs
A<B A<B
B0 0
B1 A
B2
B3 3
The IC shown is the 4-bit 74LS85.
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Slide 15
 Combinational Logic - Comparators

Comparators
IC comparators can be expanded using the cascading inputs as
shown. The lowest order comparator has a HIGH on the A = B.
LSBs MSBs

A0 COMP A4 COMP
A1 0 A5 0
A2 A A6 A
A3 A7
3 3
A>B A>B A>B A>B
+5.0 V A=B A=B A=B A=B Outputs
A<B A<B A<B A<B
B0 0 B4 0
B1 A B5 A
B2 B6
B3 3 B7 3

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Slide 16
 Combinational Logic - Decoders

Decoders
A decoder is a logic circuit that detects the presence of a specific
combination of bits at its input. Two simple decoders that detect
the presence of the binary code 0011 are shown.
The first has an active HIGH output; the second has an active
LOW output.
A0 A0
A1 X A1 X

A2 A2

A3 A3

Active HIGH decoder for 0011 Active LOW decoder for 0011
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Slide 17
 QUIZ
Assume the output of the decoder shown is a
logic 1. What are the inputs to the decoder?

A0 = 0
A1 = 1
1
A2 = 0
A3 = 1

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Slide 18
 Combinational Logic - Decoders

Decoders
IC decoders have multiple outputs to decode any combination of
inputs. For example the binary-to-decimal decoder shown here
has 16 outputs – one for each combination of binary inputs.
Bin/Dec
0 1
For the input shown, what is the output? 1 1
2 1
3 1
4 1
1 A0 5 1
6 1
4-bit binary 1 A1 7 1 Decimal
input 0 A2 8 1 outputs
9 1
1 A3 10 1
11 0
12 1
13 1
14 1
15 1

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Slide 19
 Combinational Logic - Decoders

Decoders

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Slide 20
 Combinational Logic - Decoders
X/Y
Decoders 0
1
A specific integrated circuit decoder 2
is the 74HC154 (shown as a 4-to-16 3
4
decoder). 5
A0
1 6
It includes two active LOW chip A1 2 7
A2
select lines which must be at the A3
4
8
8
9
active level to enable the outputs. 10
11
12
13
14
CS1
& 15
CS2 EN
74HC154

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Slide 21
 Combinational Logic - Decoders
Decoders
The 74LS138 is a 3-to-8 decoder with three chip select inputs (two active
LOW, one active HIGH).
In this Multisim circuit, the word generator (XWG1) is set up as an up counter.
The logic analyzer (XLA1) compares the input and outputs of the decoder.

Inputs are blue, outputs are red.

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Slide 22
 Combinational Logic - Decoders

Decoders
BCD-to-decimal decoders accept a binary coded decimal input
and activate one of ten possible decimal digit indications.

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Slide 23
 Combinational Logic - Decoders
BCD/DEC
Decoders 0
(1)
(2)
1
(3)
2
(15) (4)
A0 1 3
(14) (5)
A1 2 4
A2 (13) (6)
4 5
Assume the inputs to the 74HC42 A3
(12)
8 6
(7)
(9)
decoder are the sequence 0101, 0110, 7
(10)
8
0011, and 0010. Describe the output. 9
(11)

74HC42

All lines are HIGH except for one active output, which is
LOW. The active outputs are 5, 6, 3, and 2 in that order.

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Slide 24
 Combinational Logic - Decoders

BCD Decoder/Driver
Another useful decoder is the 74LS47. This is a BCD-to-seven
segment display with active LOW outputs. V CC

(16)
BCD/7-seg
(4) BI/RBO
BI/RBO
The a-g outputs are designed (13)
(7) a
for much higher current than 1
b
(12)
(1)
most devices (hence the BCD
inputs (2)
2
c
(11) Outputs
4 (10) to seven
word driver in the name). (6)
8
d
(9) segment
e device
LT (3) LT (15)
f
(5) (14)
RBI RBI g

74LS47 (8)

GND
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Slide 25
 Combinational Logic - Decoders

BCD Decoder/Driver
Here the 7447A is an connected to an LED seven segment
display. Notice the current limiting resistors, required to
prevent overdriving the LED display.
+5.0 V
1.0 kW
+5.0 V
74LS47 16
R's = MAN72
BCD/7-seg
3 VCC 330 W 3, 9, 14
LT a 13 1 a
4
BI/RBO b 12 13 b
5 RBI 11 10
c c
6 A 10 8
d d
2 B e 9 7 e
BCD
input 1 C f 15 2 f
g 14 11 g
7
D
GND
8

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Slide 26
 Combinational Logic - Encoders

Encoders
An encoder accepts an active logic level on one of its inputs and
converts it to a coded output, such as BCD or binary.

The decimal to BCD is an

encoder with an input for each 1
A0
of the ten decimal digits and 2

four outputs that represent the 3

A1
BCD code for the active digit. 4
5
The basic logic diagram is 6 A2
7
shown. 8
A3
There is no zero input because 9
the outputs are all LOW when
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Slide 27
 Combinational Logic - Encoders

Encoders
Show how the decimal-to-BCD encoder converts the
decimal number 3 into a BCD 0011.
The top two OR gates have ones as indicated with the
red lines. Thus the output is 0111.

1 0 1
A0
2 0
1
3 1
A1

4 0
5 0 0
6
0
0 A2
7
8 0 0
A3
0
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Slide 28
 Combinational Logic - Encoders

Encoders
The 74HC147 is an example of an IC encoder. It is has ten active-
LOW inputs and converts the active input to an active-LOW
BCD output. V CC

(16)
This device is offers additional (11)
HPRI/BCD
1
flexibility in that it is a priority (12)
2
(13)
encoder. (1)
3
1 (9)
4 (7)
Decimal input (2) 2 BCD
5
This means that if more than one (3) 6
4 (6)
(14)
output
8
input is active, the one with the (4)
7
(5) 8
highest order decimal digit will (10) 9
be active. (8)
74HC147
GND
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Slide 29
 Combinational Logic - Encoders
VCC
Encoders
R7 R8 R9

Keyboard
7 8 9
encoder HPRI/BCD
1
R4 R5 R6 2
3 1
4 2
5 4
BCD complement of
6 8 key press
4 5 6 7
8
9

R1 R2 R3 74HC147

1 2 3

R0 The zero line is not needed by the

encoder, but may be used by other
0
circuits to detect a key press.
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Slide 30
 Combinational Logic - Decoder/Encoders

HIGH
9 Encoder
8
Keypad Encoder 7
6 Binary code
5 for 9 used for
4 storage and/or
3 computation
2
7 8 9 1
4 5 6 0
1 2 3
0 . +/–
Calculator keypad

Seven Segment Decoder Decoder

Binary input

7-segment display

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Slide 31
 Combinational Logic – Code Converter

Code Converters
There are various code converters that change one code to another.
Two examples are the four bit binary-to-Gray converter and the
Gray-to-binary converter.
Show the conversion of binary 0111 to Gray and back.
0 1 LSB
1 0
LSB
0 1
1 0

1 1 1 1

0 0
0 MSB 0 MSB
Binary-to-Gray Gray-to-Binary
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Slide 32
 Combinational Logic – Code Converter

Code converters

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Slide 33
 Combinational Logic – Multiplexer

Multiplexers
A multiplexer (MUX) selects one data line from two or more
input lines and routes data from the selected line to the output.
The particular data line that is selected is determined by the
select inputs.
MUX
0
S0 0
Data
1
select S1 1
Which data line is
selected if S1S0 = 10? D0 Data
0
D1 output
Data 1
D2 inputs
D2
2
D3
3

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Slide 34
 Combinational Logic – Multiplexer

Multiplexers

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Slide 35
 Combinational Logic – Multiplexer

Demultiplexers
A demultiplexer (DEMUX) performs the opposite function
from a MUX. It switches data from one input line to two or
more data lines depending on the select inputs.

The 74LS138 was introduced DEMUX

Y0
previously as a decoder but can also Data select A0
Y1
serve as a DEMUX. When connected lines A1
Y2
as a DEMUX, data is applied to one A2 Data
Y3
of the enable inputs, and routed to the outputs
Y4
selected output line depending on the Enable G1
Y5
select variables. Note that the outputs inputs G2A
Y6
are active-LOW as illustrated in the G2B
Y7
following example…
74LS138
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Slide 36
 Combinational Logic – DeMultiplexer

Demultiplexers

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Slide 37
 Combinational Logic – DeMultiplexer
A0
Demultiplexers A1
Determine the outputs, given the A2
inputs shown.
G1
G2A LOW
The output logic is opposite to the input G2B LOW
because of the active-LOW convention. (Red
shows the selected line). Y0
DEMUX Y1
Y0
Data A0 Y2
Y1
select A1
lines A2
Y2
Data
Y3
Y3
Y4
outputs Y4
Enable G1
Y5
G2A Y5
inputs Y6
G2B Y6
Y7
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Slide 38
 Combinational Logic – Multiplexer/DeMultiplexer

Multiplexer Demultiplexer
A D
Data from Data from Data from Data from
A to D B to E C to F A to D
∆t1 ∆t1
∆ t1 ∆ t2 ∆ t3 ∆t 1
B E
∆t2 ∆t2
∆t3 ∆t3
C F

Switching Switching
sequence sequence
control input control input

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Slide 39
 IA/DSC/T/101

DIGITAL ELECTRONICS
MODULE III

Latches
Flip-Flops

[Link] INDUSTRIAL AUTOMATION Page 59 of 111

 Latches

• S-R (Set-Reset) latch

• Gated S-R latch
• Gated D latch

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Slide 3
 Latches

Latches

A latch is a temporary storage device that has two stable states

(bistable). It is a basic form of memory.
The S-R (Set-Reset) latch is the most basic type. It can be
constructed from NOR gates or NAND gates.
With NOR gates, the latch responds to active-HIGH inputs.
With NAND gates, the latch responds to active-LOW inputs.
R S
Q Q

Q Q
S R
NOR Active-HIGH Latch NAND Active-LOW Latch

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Slide 4
 Latches
Active-HIGH S-R Latch
The active-HIGH S-R latch is in a stable (latched) condition
when both inputs are LOW.
Assume the latch is initially
0 R 0 1
RESET (Q = 0) and the inputs Q
are at their inactive level (0). Latch
initially
To SET the latch (Q = 1), a
RESET
momentary HIGH signal is 1 0
Q
applied to the S input while the 1 S
R remains LOW.
1 R 1 0
Q
To RESET the latch (Q = 0), a
momentary HIGH signal is Latch
applied to the R input while the initially
SET
S remains LOW. 0 1
Q
Never apply an active set and 0 S
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Slide 5
 Latches

Active-HIGH S-R Latch

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Slide 6
 Latches
Active-LOW S-R Latch
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH.
Assume the latch is initially
0 S 0 1
RESET (Q = 0) and the inputs Q
are at their inactive level (1). Latch
To SET the latch (Q = 1), a initially
1 0 RESET
momentary LOW signal is Q
applied to the S input while the 1 R
R remains HIGH. 1 S 1 0
Q
To RESET the latch (Q = 0) a
Latch
momentary LOW is applied to
initially
the R input while S is HIGH. SET
0 1
Never apply an active set and 0 R Q
reset at the same time (invalid).
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Slide 7
 Latches

Active-LOW S-R Latch

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Slide 8
 Latches

Latches

The active-LOW S-R latch is available as the 74LS279A IC.

(2)
1S1
(3) (4) 1Q
1S2
S-R latches are frequently used (1)
1R
for switch debounce circuits as (6)
shown: 2S (7) 2Q
(5)
2R
VCC (11)
3S1
(12) (9) 3Q
3S2
(10)
3R
(15)
2 S Q 4S (13)
S 4Q
(14)
4R
R R Position Position
1 1 to 2 2 to 1
74LS279A

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Slide 9
 Latches

Latches
1
A gated latch is a variation on the basic latch. S
Q
The gated latch has an additional 0
input, called enable (EN) that must EN
be HIGH in order for the latch to
1 Q
respond to the S and R inputs. R

Show the Q output with relation to the input signals.

Assume Q starts LOW.
Keep in mind that S and R are only active when EN is HIGH.
S
R

EN
Q
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Slide 10
 Latches

Latches

The D latch is an variation of the S-R latch but combines the S and R
inputs into a single D input as shown:

D D Q
Q

EN EN

Q
Q

A simple rule for the D latch is:

Q follows D when the Enable is active.

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Slide 11
 Latches

Latches

The truth table for the D latch summarizes its operation.

If EN is LOW, then there is no change in the output and it is latched.

Inputs Outputs
D EN Q Q Comments
0 1 0 1 RESET
1 1 1 0 SET
X 0 Q0 Q0 No change

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Slide 12
 Latches

Latches

Determine the Q output for the D latch,

given the inputs shown.

EN

Notice that the Enable is not active during these times, so the output
is latched.

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Slide 13
 Edge-Triggered Flip-Flops

• Edge-triggered D flip-flop
• Edge-triggered J-K flip-flop

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Slide 14
 Edge-Triggered Flip-Flops

Flip-flops
A flip-flop differs from a latch in the manner it changes states.
A flip-flop is a clocked device, in which only the clock edge
determines when a new bit is entered.
The active edge can be positive or negative.

D Q D Q

C C

Dynamic Q Q
input
indicator (a) Positive edge-triggered (b) Negative edge-triggered

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Slide 15
 Edge-Triggered Flip-Flops

Flip-flops

The truth table for a positive-edge triggered D flip-flop shows

an up arrow to remind you that it is sensitive to its D input
only on the rising edge of the clock; otherwise it is latched.
The truth table for a negative-edge triggered D flip-flop is
identical except for the direction of the arrow.

Inputs Outputs Inputs Outputs

D CLK Q Q Comments D CLK Q Q Comments
1 1 0 SET 1 1 0 SET
0 0 1 RESET 0 0 1 RESET

(a) Positive-edge triggered (b) Negative-edge triggered

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Slide 16
 Edge-Triggered Flip-Flops

Edge-triggered D flip-flop

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Slide 17
 Edge-Triggered Flip-Flops

Flip-flops

The J-K flip-flop is more versatile than the D flip flop.

In addition to the clock input, it has two inputs, labeled J and
K. When both J and K = 1, the output changes states (toggles)
on the active clock edge (in this case, the rising edge).

Inputs Outputs
J K CLK Q Q Comments
0 0 Q0 Q0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q0 Q0 Toggle

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Slide 18
 Edge-Triggered Flip-Flops

Edge-triggered J-K flip-flop Q

J

CLK
Determine the Q output for the J-K
flip-flop, given the inputs shown. K Q

Notice that the outputs change on the leading edge of the clock.

Set Toggle Set Latch

CLK

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Slide 19
 Edge-Triggered Flip-Flops

Flip-flops
A D-flip-flop does not have a toggle mode like the J-K flip-
flop, but you can hardwire a toggle mode by connecting Q
back to D as shown. This is useful in some counters as you
will see in Chapter 8.
For example, if Q is LOW, Q is HIGH D Q
and the flip-flop will toggle on the next
CLK CLK
clock edge. Because the flip-flop only
changes on the active edge, the output
Q
will only change once for each clock
pulse.
Inputs Outputs Inputs Outputs
D CLK Q Q Comments CLK Q
D Dflip-flop Q Comments
hardwired for
1 1 0 SET a toggle
1 mode
1 0 SET
0 0 1 RESET 0 0 1 RESET
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Slide 20
 Edge-Triggered Flip-Flops

Flip-flop Applications

Principal flip-flop applications are for temporary data

storage, as frequency dividers, and in Counters (which are
covered in detail in Chapter 8).

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Slide 21
 Edge-Triggered Flip-Flops

Flip-flop Applications

Typically, for data storage applications,

a group of flip-flops are connected to
parallel data lines and clocked together.
Data is stored until the next clock pulse.

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Slide 22
 Edge-Triggered Flip-Flops

Flip-flop Applications

For frequency division, it is simple to use a flip-flop in

the toggle mode or to chain a series of toggle flip flops to
continue to divide by two. HIGH HIGH

One flip-flop will divide fin

QA QB fout
by 2, two flip-flops will J J

divide fin by 4 (and so on). fin CLK CLK

A side benefit of frequency
division is that the output K K
has an exact 50% duty
fin
cycle.
Waveforms:
fout
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Slide 23
 Multivibrator

• Monostable (One-Shot)
• Astable.

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Slide 24
 Multivibrator

Monostable
The monostable or one-shot multivibrator is a device with
only one stable state. When triggered, it goes to its unstable
state for a predetermined length of time, then returns to its
stable state. +V

For most one-shots, the length of time REXT CEXT

in the unstable state (tW) is determined Q
CX
by an external RC circuit. RX/CX
Trigger

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Slide 25
 Multivibrator

Astable

An astable multivibrator is a device that has no stable states;

it changes back and forth (oscillates) between two unstable
states without any external triggering. The resulting output
is typically a square wave that is used as a clock signal in
many types of sequential logic circuits.

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Slide 26
 Multivibrator

The 555 timer

The 555 timer can be configured in various ways. A basic

monostable is shown. The pulse width is determined by R1C1
and is approximately tW = 1.1R1C1.
+VCC

(4) (8)
R1
(7) RESET VCC
DISCH
(6) (3)
The trigger is a THRES OUT
negative-going (2) (5) tW = 1.1R1C1
TRIG CONT
pulse. GND
C1 (1)

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Slide 27
 Multivibrator

The 555 timer

The 555 can be configured as a basic astable multivibrator
with the circuit shown. In this circuit C1 charges through R1
and R2 and discharges through only R2. +V CC

The output frequency is given by:

1.44 R1
(4) (8)
f =
( R1 + 2 R2 ) C1 (7)
RESET
DISCH
VCC

(6) (3)
R2 THRES OUT
(2) (5)
TRIG CONT
C1 GND
(1)

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Slide 28
 Multivibrator

The 555 timer

Given the components, you can read the frequency from
the chart. Alternatively, you can use the chart to pick
components for a desired frequency.
+VCC
100

10 (4) (8)
R1
RESET VCC
1.0 (7)
DISCH
C1 (mF)

10

1
1M

10

10

kW
0k
MW

kW

(6) (3)
W

R2 THRES
W

0.1 OUT
(2) (5)
TRIG CONT
0.01
C1 GND
(1)
0.001
0.1 1.0 10 100 1.0k 10k 100k

f (Hz)
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Slide 29
 Timer 555 Applications

Flasher

Tone Generator

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Slide 30
 IA/DSC/T/101

DIGITAL ELECTRONICS
MODULE III

Counters

[Link] INDUSTRIAL AUTOMATION Page 88 of 111

 Counters

Counting in Binary
As you know, the binary count sequence follows a
familiar pattern of 0’s and 1’s.

000 LSB changes on every

001 number.
010
The next bit changes
011 on every other number.
100
The next bit changes on
101
every fourth number.
110
111

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Slide 3
 Counters

Counting in Binary

A counter can form the same pattern of 0’s and 1’s with
logic levels. The first stage in the counter represents the
least significant bit – notice that these waveforms follow
the same pattern as counting in binary.

LSB 0 1 0 1 0 1 0 1 0

0 0 1 1 0 0 1 1 0

MSB 0 0 0 0 1 1 1 1 0

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Slide 4
 Asynchronous binary counter

In an asynchronous counter, the clock is applied only to the

first stage.
Subsequent stages derive the clock from the previous stage.
It uses J-K flip-flops in the toggle mode.
Notice that the Q0 output is triggered on the leading edge of
the clock signal. The following stage is triggered from Q0.

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Slide 5
 Inputs Outputs
Edge-Triggered Flip-Flops J K CLK Q Q Comments
0 0 Q0 Q0 No change
0 1 0 1 RESET

Edge-triggered J-K flip-flop 1

1
0
1
1
Q0
0
Q0
SET
Toggle

Determine the Q output for the J-K

flip-flop, given the inputs shown.
Notice that the outputs change on the leading edge of the clock.

Set Toggle Set Latch

CLK

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Slide 6
 Asynchronous binary counter

2-bit Asynchronous binary counter

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Slide 7
 Asynchronous binary counter

3-bit Asynchronous binary counter

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Slide 8
 Asynchronous binary counter

4-bit Asynchronous binary counter

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Slide 9
 Asynchronous binary counter

Asynchronous decade counter

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Slide 10
 Asynchronous binary counter

Propagation Delay
Asynchronous counters are sometimes called ripple counters,
because the stages do not all change together. For certain
applications requiring high clock rates, this is a major
disadvantage.
CLK 1 2 3 4
Notice how delays are
cumulative as each Q0
stage in a counter is Q1
clocked later than the
previous stage. Q2

Q0 is delayed by 1 propagation delay, Q2 by 2 delays and Q3 by 3 delays.

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Slide 11
 Synchronous binary counter

Synchronous Counters

In a synchronous counter all flip-flops are clocked

together with a common clock pulse.
Synchronous counters overcome the disadvantage of
accumulated propagation delays, but generally they require
more circuitry to control states changes.

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Slide 12
 Synchronous binary counter
Inputs Outputs
2-bit Synchronous binary counter J K CLK Q Q Comments
0 0 Q0 Q0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q0 Q0 Toggle

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Slide 13
 Synchronous binary counter

3-bit Synchronous binary counter

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Slide 14
 Synchronous binary counter

4-bit Synchronous binary counter

The 4-bit binary counter has

one more AND gate than the
3-bit counter just described.
The shaded areas show where
the AND gate outputs are
HIGH causing the next FF to
toggle.

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Slide 15
 Synchronous binary counter

Synchronous decade counter

This gate detects 1001, and

causes FF3 to toggle on the
next clock pulse. FF0 toggles
on every clock pulse. Thus, the
count starts over at 0000.
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Slide 16
 Synchronous binary counter

Counter Decoding

Show how to decode state 5 with an active LOW output.

HIGH

Q0 Q2
J0 Q0 J1 Q1 J2 Q2

C C C

Q1
K0 Q0 K1 Q1 K2 Q2

CLK
1 1 1
LSB MSB

Decoded 5
Q2Q1Q0
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Slide 17
 Synchronous binary counter

A 4-bit Synchronous Binary Counter

The 74LS163 is a 4-bit IC synchronous counter with additional features over
a basic counter. It has parallel load, a CLR input, two chip enables, and a
ripple count output that signals when the count has reached the terminal count.
Data inputs
D0 D1 D2 D3

(3) (4) (5) (6)

CLR (1)
(9) CTR DIV 16
LOAD
(10) (15)
ENT TC = 15 RCO
(7)
ENP
(2)
CLK C

(14) (13) (12) (11)

Q0 Q1 Q2 Q3

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Slide 18
 A 4-bit Synchronous Binary Counter
CLR
LOAD
D0
D1
Data
inputs D2

D3

CLK
ENP
ENT

Q0
Q1
Data
outputs Q2
Q3

RCO
12 13 14 15 0 1 2

Count Inhibit
Clear Preset
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Slide 19
 Synchronous binary counter

Cascaded counters
Cascading is a method of achieving higher-modulus counters. For
synchronous IC counters, the next counter is enabled only when
the terminal count of the previous stage is reached.
HIGH
ƒin
Counter 1 Counter 2
16 fout ƒin
CTEN TC CTEN TC 256
CTR DIV 16 CTR DIV 16
CLK C Q0 Q1 Q2 Q3 C Q0 Q1 Q2 Q3
fin

a) What is the modulus of the cascaded DIV 16 counters?

b) If fin =100 kHz, what is fout?
a) Each counter divides the frequency by 16. Thus the
modulus is 162 = 256.
b) The output frequency is 100 kHz/256 = 391 Hz
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Slide 20
 Counter Applications – Digital Clock

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Slide 21
 Up counter
Synchronous binary counter
Q1 Q0
0 0
Up/Down Synchronous Counters 0 1
1 0
1 1
Down counter
Q1 Q0 Q0
0 0 1
1 1 0
1 0 1
0 1 0

An up/down counter is capable

of progressing in either direction
depending on a control input.

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Slide 22
 Synchronous binary counter

Synchronous Counter Design

Most requirements for synchronous counters can be met with
available ICs. In cases where a special sequence is needed,
you can apply a step-by-step design process.
Start with the desired sequence and draw a state diagram and next-
state table. The gray code sequence from the text is illustrated:

State diagram: Next state table:

000 Present State Next State
100 001 Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
101 011 0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
111 010 1 1 0 1 1 1
1 1 1 1 0 1
110 1 0 1 1 0 0
1 0 0 0 0 0

Floyd Copyright ©2006 by Pearson Education, Inc.

Digital Fundamentals, 9/e Page 109 of 111
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All rights reserved.
Slide 23
 Synchronous binary counter

Synchronous Counter Design

The J-K transition table lists all Output Flip-Flop
combinations of present output (QN) and Transitions
QN Q N+1
Inputs
J K
next output (QN+1) on the left. The inputs 0 0 0 X
that produce that transition are listed on 0
1
1
0
1
X
X
1
1 1 X 0
the right.
Each time a flip-flop is clocked, the J and K inputs required for that
transition are mapped onto a K-map.
Present State Next State
Q0 Q2 Q1 Q0 Q2 Q1 Q0
Q2Q1 0 1
X Q2Q1 0 0 0 0 0 1
00 1
0 0 1 0 1 1
01 0 X 0 1 1 0 1 0
An example of 0 1 0 1 1 0
1 1 0 1 1 1
the J0 map is: 11 1 X Q2Q1
1 1 1 1 0 1
10 0 X 1 0 1 1 0 0
1 0 0 0 0 0
J0 map
Floyd Copyright ©2006 by Pearson Education, Inc.
Digital Fundamentals, 9/e Page 110 of 111
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 24
 Synchronous binary counter

Synchronous Counter Design

FF0 FF1 FF2

Q2
J0 J1 J2
Q0 Q1
C C C
Q0 Q1 Q2
K0 K1 K2

CLK

The logic for each input is read

and the circuit is constructed.
The slide shows the circuit for
the gray code counter…
Floyd Copyright ©2006 by Pearson Education, Inc.
Digital Fundamentals, 9/e Page 111 of 111
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 25