COMPUTER ORGANIZATION
&ARCHITECTURE
(21CSS201T)
ASSIGNMENT-2
SUBMITTED BY:
SUYASH MATHUR
RA2411026030069
AIML-B
Assignment-2
Q1) 8 × -4 and -11 × -6 via Booth Algorithm
Booth’s algorithm is used for signed multiplication using 2’s complement
representation.
It reduces the number of addition/subtraction operations when multiplying binary
numbers.
Example 1: 8 × -4
→ 8 = 1000, -4 = 1100 (4-bit 2’s complement)
Steps:
1. Initialize: A = 0, Q = 1000, M = 1100, Q(-1) = 0
2. Apply Booth’s steps for 4 cycles.
Result = -32 (in decimal).
Example 2: -11 × -6
→ -11 = 0101 (2’s complement of 10101 for 5-bit), -6 = 1010 (2’s complement)
After applying Booth’s algorithm, Result = +66.
Q2) -7 × -8 and 11 × -9 via Flowchart Method
The flowchart method follows the basic multiplication using add-and-shift
operations with signed numbers.
Case 1: (-7) × (-8) = 56
Case 2: (11) × (-9) = -99
The algorithm uses:
1. Sign check.
2. Binary conversion and 2’s complement if needed.
3. Repeated addition and shifting.
Q3) 9 ÷ 4 and 11 ÷ 5 via Restoring Division Method
Restoring Division Algorithm performs binary division step-by-step using shifting
and subtraction.
Example 1: 9 ÷ 4
→ Binary: 1001 ÷ 0100
Quotient = 0010 (2), Remainder = 0001 (1)
Example 2: 11 ÷ 5
→ Binary: 1011 ÷ 0101
Quotient = 0010 (2), Remainder = 0001 (1)
Q4) 38 × 42 and 18 × 26 via Carry Save Addition
Carry Save Addition (CSA) is used in multipliers to reduce carry propagation delay.
Example 1: 38 × 42 = 1596
Example 2: 18 × 26 = 468
The partial products are added simultaneously using CSA which improves speed
over ripple carry adders.
Q5) Role of Vector Processors in Data-Level
Parallelism
Vector processors handle multiple data elements simultaneously using vector
instructions.
They achieve data-level parallelism (DLP) by performing the same operation on
large data sets.
Difference from Scalar Processors:
- Scalar: Operates on one data element per instruction.
- Vector: Operates on multiple elements (array processing).
Example: Matrix operations, graphics, scientific computations.
Q6) Hardwired vs Microprogrammed Control Unit
Hardwired Control Unit:
- Uses fixed logic circuits to control signals.
- Fast but inflexible.
- Example: RISC processors.
Microprogrammed Control Unit:
- Uses control memory (ROM) to store microinstructions.
- Slower but flexible.
- Example: CISC processors like Intel x86.
Q7) When to Prefer Microprogrammed Control Unit
Microprogrammed control is preferred when:
- Complex instruction sets (CISC) are used.
- System requires easier modification and debugging.
Example: In microcontrollers or older Intel CPUs, microprogrammed control
simplifies complex instruction handling.
Q8) ARM Encoding Format and Thumb Instruction
Set
ARM Encoding Format:
- ARM instructions are 32-bit.
- Contain condition field, opcode, operand fields.
Thumb Instruction Set:
- 16-bit compressed instruction format.
- Increases code density.
- Useful for embedded systems with limited memory.
Features:
- Faster execution.
- Reduced power consumption.
- Compatible with ARM instructions.
Q9) Difference Between MUX and DEMUX
Multiplexer (MUX):
- Selects one input out of many and sends it to a single output.
- Example: 8:1 MUX.
Demultiplexer (DEMUX):
- Takes one input and routes it to one of several outputs.
- Example: 1:8 DEMUX.
MUX → Many to One
DEMUX → One to Many
Q10) Dual Processor Execution and Hardware
Parallelism
Dual processors allow two CPUs to execute instructions simultaneously.
This increases performance through parallelism.
Advantages:
- Faster processing.
- Better multitasking.
- Enhanced throughput.
Used in servers, high-performance systems, and AI computation.
Q11) Arithmetic Logic Unit (ALU) Design
ALU performs arithmetic (add, subtract) and logic (AND, OR, NOT) operations.
Design:
- Built using Half Adders and Full Adders.
Half Adder:
- Inputs: A, B → Outputs: Sum, Carry.
Full Adder:
- Inputs: A, B, Carry_in → Outputs: Sum, Carry_out.
ALU integrates these blocks for multi-bit operations and includes control logic for
operation selection.