TSZ901

Datasheet

Very high accuracy (5 μV) high bandwidth (10 MHz) zero-drift 5 V op amp

Features

• AEC-Q100 automotive qualification

• Very high accuracy and stability: offset voltage
– 5 μV max. at 25 °C
– 8 μV over the full temperature range (-40 °C to 125 °C)
• Rail-to-rail input and output
• Low supply voltage: 2.5 - 5.5 V
• Low power consumption: 1.5 mA at 5 V
• Gain-bandwidth product: 10 MHz
• Extended temperature range: -40 °C to 125 °C
• Benefits:
– Higher accuracy without calibration
Maturity status link – Accuracy virtually unaffected by temperature change
TSZ901
Applications
Automotive

• High-accuracy signal conditioning

Channel

Products Package • Automotive current measurement and sensor signal conditioning

TSZ901ILT 1 SOT23-5
Description
TSZ901IYLT 1 • SOT23-5 The TSZ901 is a single operational amplifier featuring very low offset voltages with
virtually zero drift over temperature changes.
The TSZ901 offers rail-to-rail input and output, excellent speed/power consumption
Related products
ratio, and a 10 MHz gain-bandwidth product, while consuming just 1.5 mA at 5 V.
Zero-drift amplifier for lower The device also features an ultra-low input bias current. These features make the
TSZ181 power consumption (3 MHz, TSZ901 ideal for high-accuracy sensor interfaces.
800 µA)
High-accuracy (200 μV) 5 V
TSV771 amplifier with wider bandwidth
(20 MHz)

DS15041 - Rev 2 - December 2025 [Link]

For further information, contact your local STMicroelectronics sales office.
 TSZ901
Pin description

1 Pin description

1.1 TSZ901 single operational amplifier (SOT23-5)

Figure 1. Pin connections (top view)

OUT 1 5 VCC+

VCC- 2

IN+ 3 4 IN-

SOT23-5

Table 1. Pin description

Pin n° Pin name Description

1 OUT Output channel

2 VCC- Negative supply voltage
3 IN+ Non-inverting input channel
4 IN- Inverting input channel
5 VCC+ Positive supply voltage

DS15041 - Rev 2 page 2/22

 TSZ901
Maximum ratings

2 Maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter (1) Value Unit

VCC Supply voltage 6 V

Vid Input voltage differential (VIN+ - VIN-) ±VCC V

Vin Input voltage (2) (VCC-) - 0.2 to (VCC+) + 0.2 V

Iin Input current ±10 mA

Tstg Storage temperature -65 to +150 °C

Tj Maximum junction temperature 150

Thermal resistance junction-to-ambient

Rth-ja (3) °C/W
SOT23-5 250
Tj Maximum junction temperature 150 °C

HBM: human body model (industrial grade) (4) 4 kV

ESD HBM: human body model (automotive grade) (5) 4 kV

CDM: charged device model (6) 1 kV

1. All voltage values are with respect to the VCC- pin, unless otherwise specified.
2. The maximum input voltage differential value may be extended under the condition that the input current is limited to ±10
mA.
3. Rth-ja is a typical value, obtained with PCB according to JEDEC 2s2p without vias.
4. Human body model: HBM test according to the standard ESDA-JS-001-2017.
5. Human body model: HBM test according to the standard AEC-Q100-002.
6. Charged device model: the CDM test is performed according to the standard AEC-Q100-011.

Table 3. Operating conditions

Symbol Parameter Value Unit

VCC Supply voltage 2.5 to 5.5 V

Vicm Common-mode input voltage range VCC- – 0.1 V to VCC+ + 0.1 V V

Toper Operating free-air temperature range -40 to 125 °C

DS15041 - Rev 2 page 3/22

 TSZ901
Electrical characteristics

3 Electrical characteristics

Table 4. Electrical characteristics at VCC = 5 V, Vicm = VOUT = VCC / 2, T = 25 °C, CL = 47 pF and RL = 10 kΩ connected to
VCC / 2 (unless otherwise specified).

Symbol Parameter Conditions Min. Typ. Max. Unit

DC performance
T = 25 °C ±1 ±5
Vio Input offset voltage µV
-40 °C ≤ T ≤ 125 °C ±8
Input offset voltage drift over
ΔVio/ΔT (1) -40 °C ≤ T ≤ 125 °C ±10 ±30 nV/°C
temperature
T = 25 °C 150 600
Iib (2) Input bias current pA
-40 °C ≤ T ≤ 125 °C 300 600
T = 25 °C 300 1200
Iio (2) Input offset current pA
-40 °C ≤ T ≤ 125 °C 300 1200
RL = 2 kΩ, VCC- + 150 mV ≤ VOUT ≤ VCC+- 150 mV,
126 135
AVD Open-loop gain T = 25 °C dB
-40 °C ≤ T ≤ 125 °C 120

Common-mode rejection ratio VCC- ≤ Vicm ≤ VCC+,T = 25 °C 115 122

CMR dB
[Link](ΔVio/ΔVicm) VCC- ≤ Vicm ≤ VCC+, -40 °C ≤ T ≤ 125 °C 115

Supply-voltage rejection ratio 2.5 V ≤ VCC ≤ 5.5 V, T = 25 °C, Vicm = 0 V 115 140
SVR dB
[Link](ΔVio/ΔVCC) 2.5 V ≤ VCC ≤ 5.5 V, -40 °C ≤ T ≤ 125 °C, Vicm = 0 V 115

High-level output voltage drop RL = 2 kΩ, T = 25 °C 50

VOH mV
(VOH = VCC+ - VOUT) RL = 2 kΩ , -40 °C ≤ T ≤ 125 °C 70

Low-level output voltage drop RL = 2 kΩ, T = 25 °C 50

VOL mV
(VOL = VOUT) RL = 2 kΩ , -40 °C ≤ T ≤ 125 °C 70

OUT connected to VCC+, T = 25 °C 35 50

ISINK
OUT connected to VCC+, -40 °C ≤ T ≤ 125 °C 25
IOUT mA
OUT connected to VCC-, T = 25 °C 35 50
ISOURCE
OUT connected to VCC-, -40 °C ≤ T ≤ 125 °C 25

Supply current (per operational T = 25°C 1.5 2.0

ICC mA
amplifier) -40 °C ≤ T ≤ 125 °C 2.0
AC performance

GBP Gain-bandwidth product RL = 10 kΩ 10 MHz

SR Slew rate RL = 10 kΩ, AV = 1V/V, 10% to 90% 3.5 6 V/µs

Φm Phase margin RL = 10 kΩ 60 degrees

f = 1 kHz 9
en Input voltage noise density nV/√Hz
f = 10 kHz 9
en p-p Input noise voltage 0.1 Hz ≤ f ≤ 10 Hz 0.16 µVpp

VIN from (VCC+ + 100 mV) to (VCC+ -1 V) , VOUT

trec Overload recovery time 0.1 µs
measured at (VCC+ - 100 mV), AV = +11

Initialization time, VOUT at

tinit T = 25 °C 40 µs
100 mV from final value

DS15041 - Rev 2 page 4/22

 TSZ901
Electrical characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

ts Settling time VOUT to 0.1%, Vin = 1 Vp-p, AV = - 1V/V 1 µs

VRF = 100 mVp, f = 400 MHz 84

EMI rejection rate = - 20log VRF = 100 mVp, f = 900 MHz 87

EMIRR dB
(VRFpeak/ΔVio) VRF = 100 mVp, f = 1800 MHz 90

VRF = 100 mVp, f = 2400 MHz 91

1. See Section 5.2: Input offset voltage drift over the temperature.
2. Guaranteed by design and characterization on a sample of parts, not tested in production.

DS15041 - Rev 2 page 5/22

 TSZ901
Electrical characteristics

Table 5. Electrical characteristics at VCC = 3.3 V, Vicm = VOUT = VCC / 2, T = 25 °C, CL = 47 pF and RL = 10 kΩ connected
to VCC / 2 (unless otherwise specified).

Symbol Parameter Conditions Min. Typ. Max. Unit

DC performance
T = 25 °C ±1 ±6
Vio Input offset voltage µV
-40 °C ≤ T ≤ 125 °C ±8
Input offset voltage drift over
ΔVio/ΔT (1) -40 °C ≤ T ≤ 125 °C ±10 ±30 nV/°C
temperature
T = 25 °C 75 400
Iib (2) Input bias current pA
-40 °C ≤ T ≤ 125 °C 300 400
T = 25 °C 150 800
Iio (2) Input offset current pA
-40 °C ≤ T ≤ 125 °C 300 800
RL = 2 kΩ, VCC- + 150 mV ≤ VOUT ≤ VCC+- 150
126 135
AVD Open=loop gain mV, T = 25 °C dB
-40 °C ≤ T ≤ 125 °C 120

Common-mode rejection ratio VCC- ≤ Vicm ≤ VCC+,T = 25 °C 115 122

CMR dB
[Link](ΔVio/ΔVicm) VCC- ≤ Vicm ≤ VCC+, -40 °C ≤ T ≤ 125 °C 115

High-level output voltage drop RL = 2 kΩ, T = 25 °C 33

VOH mV
(VOH = VCC+ - VOUT) RL = 2 kΩ , -40 °C ≤ T ≤ 125 °C 49

Low-level output voltage drop RL = 2 kΩ, T = 25 °C 33

VOL mV
(VOL = VOUT) RL = 2 kΩ , -40 °C ≤ T ≤ 125 °C 49

OUT connected to VCC+, T = 25 °C 35 50

ISINK
OUT connected to VCC+, -40 °C ≤ T ≤ 125 °C 25
IOUT mA
OUT connected to VCC-, T = 25 °C 35 50
ISOURCE
OUT connected to VCC-, -40 °C ≤ T ≤ 125 °C 25

Supply current (by operational T = 25°C 1.5 2.0

ICC mA
amplifier) -40 °C ≤ T ≤ 125 °C 2.0
AC performance

GBP Gain-bandwidth product RL = 10 kΩ 10 MHz

SR Slew rate RL = 10 kΩ, AV = 1V/V, 10% to 90% 3.5 6 V/µs

Φm Phase margin RL = 10 kΩ 60 degrees

f = 1 kHz 9
en Input voltage noise density nV/√Hz
f = 10 kHz 9
en p-p Input noise voltage 0.1 Hz ≤ f ≤ 10 Hz 0.16 µVpp

VIN from (VCC+ + 100 mV) to (VCC+ -1 V) , VOUT

trec Overload recovery time 0.1 µs
measured at (VCC+ - 100 mV), Av = +11

Initialization time, VOUT at 100

tinit T = 25 °C 40 µs
mV from final value
ts Settling time VOUT to 0.1%, Vin = 1 Vp-p, AV = - 1V/V 1 µs

1. See Section 5.2: Input offset voltage drift over the temperature.
2. Guaranteed by design and characterization on a sample of parts, not tested in production.

DS15041 - Rev 2 page 6/22

 TSZ901
Electrical characteristics

Table 6. Electrical characteristics at VCC = 2.5 V, Vicm = VOUT = VCC / 2, T = 25 °C, CL = 47 pF and RL = 10 kΩ connected
to VCC / 2 (unless otherwise specified).

Symbol Parameter Conditions Min. Typ. Max. Unit

DC performance
T = 25 °C ±1 ±6
Vio Input offset voltage µV
-40 °C ≤ T ≤ 125 °C ±8
Input offset voltage drift over
ΔVio/ΔT (1) -40 °C ≤ T ≤ 125 °C ±10 ±30 nV/°C
temperature
T = 25 °C 50 300
Iib (2) Input bias current pA
-40 °C ≤ T ≤ 125 °C 300 300
T = 25 °C 100 600
Iio (2) Input offset current pA
-40 °C ≤ T ≤ 125 °C 300 600
RL = 2 kΩ, VCC- + 150 mV ≤ VOUT ≤ VCC+- 150
126 135
AVD Open-loop gain mV, T = 25 °C dB
-40 °C ≤ T ≤ 125 °C 120

Common-mode rejection ratio VCC- ≤ Vicm ≤ VCC+, T = 25 °C 110 122

CMR dB
[Link](ΔVio/ΔVicm) VCC- ≤ Vicm ≤ VCC+, -40 °C ≤ T ≤ 125 °C 110

High-level output voltage drop RL = 2 kΩ, T = 25 °C 25

VOH mV
(VOH = VCC+ - VOUT) RL = 2 kΩ , -40 °C ≤ T ≤ 125 °C 35

Low-level output voltage drop RL = 2 kΩ, T = 25 °C 25

VOL mV
(VOL = VOUT) RL = 2 kΩ , -40 °C ≤ T ≤ 125 °C 35

OUT connected to VCC+, T = 25 °C 35 50

ISINK
OUT connected to VCC+, -40 °C ≤ T ≤ 125 °C 25
IOUT mA
OUT connected to VCC-, T = 25 °C 35 50
ISOURCE
OUT connected to VCC-, -40 °C ≤ T ≤ 125 °C 25

Supply current (by operational T = 25°C 1.5 2.0

ICC mA
amplifier) -40 °C ≤ T ≤ 125 °C 2.0
AC performance

GBP Gain-bandwidth product RL = 10 kΩ 10 MHz

SR Slew rate RL = 10 kΩ, AV = 1V/V, 10% to 90% 3.5 6 V/µs

Φm Phase margin RL = 10 kΩ 60 degrees

f = 1 kHz 9
en Input voltage noise density nV/√Hz
f = 10 kHz 9
en p-pT Input noise voltage 0.1 Hz ≤ f ≤ 10 Hz 0.16 µVpp

VIN from (VCC+ + 100 mV) to (VCC+ -1 V) , VOUT

trec Overload recovery time 0.15 µs
measured at (VCC+ - 100 mV), AV = +11

Initialization time, VOUT at 100

tinit T = 25 °C 40 µs
mV from final value
ts Settling time VOUT to 0.1%, Vin = 1 Vp-p, AV = - 1V/V 1 µs

1. See Section 5.2: Input offset voltage drift over the temperature.
2. Guaranteed by design and characterization on a sample of parts, not tested in production.

DS15041 - Rev 2 page 7/22

 TSZ901
Typical performance characteristics

4 Typical performance characteristics

Figure 2. Supply current vs. supply voltage Figure 3. Input offset voltage distribution at VCC = 5 V

1.5
Vicm=Vcc/2 22
Vcc=2.5V
20 Vicm=1.25V
18
T=25°C
Measured on 13542 parts
Supply Current (mA)

16
1.0

Population (%)
14
T=25°C
12
T=125°C
T=-40°C 10

0.5 8

0.0 0
0 1 2 3 4 5 0 1 2 3 4 5
Supply Voltage (V) Input Offset Voltage (µV)

Figure 5. Input offset voltage vs. temperature at VCC = 5 V

Figure 4. Input offset voltage distribution at VCC = 2.5 V

8
22
6 Vcc=5V
20 Vcc=2.5V
Vicm=2.5V
Vicm=1.25V
18 T=25°C 4
16 Measured on 13542 parts
Input offset (uV)
Population (%)

14 2

12
0
10

0
0 1 2 3 4 5 6
0 20 40 60 80 100 120
Input Offset Voltage (µV)
T (°C)

DS15041 - Rev 2 page 8/22

 TSZ901
Typical performance characteristics

Figure 6. Input offset voltage vs. temperature at

VCC = 2.5 V Figure 7. Input offset voltage temperature drift
distribution at VCC = 5 V

8 70

Vcc=2.5V Vcc=5V
6 60
Vicm=1.25V Vicm=2.5V

4
50
T=-40°C to 25°C
Input offset (µV)

Population (%)
2
40
0
30

20
T=25°C to 125°C

10

0
0 20 40 60 80 100 120 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30

T (°C) ΔVio/ΔT (nV /°C)

Figure 8. Input offset voltage temperature drift

Figure 9. Input offset voltage vs. supply voltage
distribution at VCC = 2.5 V
8
70 Vicm = Vcc/2
6
Vcc=2.5V
60 Vicm=1.25V
Input Offset Voltage (µV)

50
T=-40°C to 25°C 2
Population (%)

40
T=25°C to 125°C 0

T=-40°C T=125°C
30 -2

20 -4

10 -6
T=25°C
0 -8
2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00
-30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30
Supply Voltage (V)
ΔVio/ΔT (nV /°C)

Figure 10. Input offset voltage vs. input common-mode Figure 11. Input offset voltage vs. input common-mode
voltage at VCC = 5 V voltage at VCC = 2.5 V

8 8
Vcc=5V Vcc=5V
6 Vicm from -0.1V to 5.1V 6 Vicm from -0.1V to 2.6V
Input Offset Voltage (µV)

Input Offset Voltage (µV)

4 4

2 2
T=-40°C T=-40°C
T=25°C T=25°C
0 0

-2 -2

-4 -4

T=125°C
-6 -6 T=125°C

-8 -8
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5

Input Common Mode Voltage (V) Input Common Mode Voltage (V)

DS15041 - Rev 2 page 9/22

 TSZ901
Typical performance characteristics

Figure 12. Input bias current vs. input common-mode

Figure 13. Output current vs. output voltage at VCC = 5 V
voltage at VCC = 5 V

80
70 Sink
Vcc=5V Vid=-1V
400 60
50
40

Output Current (mA)

Input Bias Current (pA)

200 30
20 T=125°C
10 T=25°C
0 T=-40°C T=25°C T=125°C 0 T=-40°C
-10
-20
-200 -30
-40
-50
-400 -60 Source
Vid=1V
-70
-80
-600 0 1 2 3 4 5
0 1 2 3 4 5
Vout (V)
Input Common Mode Voltage (V)

Figure 14. Output current vs. output voltage at VCC = 2.5 V Figure 15. Output drop voltage VOH vs. supply voltage

70 34
60 Sink 32 Vid=1V
Vid=-1V 30 Rl=2kΩ to Vcc/2
50 T=125°C
28
40 26
Output Voltage (mV)
Output Current (mA)

30 24
22 T=25°C
20
T=125°C 20
10 18
T=25°C
0 T=-40°C 16
-10 14
12
-20
10
-30 8 T=-40°C
-40 6
Source 4
-50
Vid=1V 2
-60 0
-70 -2
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.5 3.0 3.5 4.0 4.5 5.0
Vout (V) Power Supply Voltage (V)

Figure 16. Output drop voltage VOL vs. supply voltage Figure 17. Positive slew rate at VCC = 5 V

34
32
Vid=-1V
30 Rl=2kΩ to Vcc/2 2
28 T=125°C
T=125°C
Output Voltage (mV)

26
Vin T=25°C
24 1
Voltage (V)

22
20 T=25°C
18 0
16
T=-40°C
14
12
-1 Vout
10
8 T=-40°C Vcc=+/-2.5V
6 Rl=10kΩ to GND
4 -2 Cl=47pF
2
0 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
2.5 3.0 3.5 4.0 4.5 5.0
Time (µs)
Power Supply Voltage (V)

DS15041 - Rev 2 page 10/22

 TSZ901
Typical performance characteristics

Figure 18. Negative Slew rate at VCC = 5 V

Figure 19. Slew rate vs. temperature

10

2 Vcc=+/-2.5V
Rl=10kΩ to GND T=25°C
Positive slew-rate
Cl=47pF
1

Slew Rate (V/µs)

Vout T=-40°C T=125°C
Voltage (V)

Vin = 0.1xVdd to 0.9xVdd

T=25°C Slew rate measured at
0 0
10% and 90%

-1 T=-40°C
T=-40°C
Vin T=125°C
T=125°C Negative slew-rate
-2 T=25°C

-10
-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Time (µs) Supply Voltage (V)

Figure 20. Bode diagram in open loop at VCC = 5 V Figure 21. Bode diagram in open loop at VCC = 2.5 V

80 180 80 180
150 150
60 120 60 120
90 90
40 60 40 60
Phase (°)

Phase (°)
Gain (dB)

Gain (dB)

30 30
20 0 20 0

Vcc=5V -30 Vcc=2.5V -30

0 Vicm=2.5V -60 0 Vicm=1.25V -60
Rl=10kΩ to Vcc/2 Rl=10kΩ to Vcc/2
-90 -90
Cl=47pF Cl=47pF
-20 T=25°C -120 -20 T=25°C -120

Rf=10kΩ, Rg=100Ω -150 Rf=10kΩ, Rg=100Ω -150

-40 -180 -40 -180
10k 100k 1M 10M 100M 10k 100k 1M 10M 100M
Frequency (Hz) Frequency (Hz)

Figure 22. Bode diagram vs. temperature at VCC = 5 V Figure 23. Bode diagram vs. temperature at VCC = 2.5 V

60 0 60 0

40 -60 40 -60
Phase (°)
Gain (dB)
Phase (°)
Gain (dB)

20 -120 20 -120

Vcc=5V Vcc=2.5V
Vicm=2.5V Vicm=1.25V
Rl=10kΩ to Vcc/2 Rl=10kΩ to Vcc/2
0 -180 0 -180
Cl=47pF T=-40°C Cl=47pF T=-40°C
Gain=101 T=25°C Gain=101 T=25°C
Rf=10kΩ, Rg=100Ω T=125°C Rf=10kΩ, Rg=100Ω T=125°C

-20 -240 -20 -240

10k 100k 1M 10M 10k 100k 1M 10M

Frequency (Hz) Frequency (Hz)

DS15041 - Rev 2 page 11/22

 TSZ901
Typical performance characteristics

Figure 24. Phase margin vs. Iload and vs. VICM Figure 25. Phase margin vs. Cload and vs. VCC

20
18 80
Rl=10kΩ
16 T=25°C
Closed loop
14 Iout is positive 70 Specification G=+101
12 when current at Cl=47pF Rf=10kΩ, Rg=100Ω
10 is sourced Rl=10kΩ to Vicm
8 60
T=25°C

Phase Margin (°)

6
Iload (mA)

4 50
2 51
0

Phase Margin (°)

54 40
-2 Vcc=5V
57
-4 Vicm=2.5V
60
-6 30
-8 63
-10 66
-12 20 Vcc=2.5V
69
-14 72 Vicm=1.25V
-16 75 10
-18
-20
0
1 2 3 4 10 100 1000 10000
Vicm (V) Capacitive load (pF)

Figure 26. Small step response at VCC = 5 V Figure 27. Small step response at VCC = 2.5 V

0.10 0.10

Vout Vout
0.05 Vin 0.05
Vin
Voltage (V)

Voltage (V)

0.00 0.00

-0.05 Vcc=+/-2.5V -0.05 Vcc=+/-1V

Rl=10kΩ to GND Rl=10kΩ to GND
Cl=47pF Cl=47pF
T=25°C T=25°C
-0.10 -0.10
-0.1 0.0 0.1 0.2 0.3 -0.1 0.0 0.1 0.2 0.3
Time (µs) Time (µs)

Figure 28. Negative overvoltage recovery at VCC = 5 V Figure 29. Positive overvoltage recovery at VCC = 5 V

1.5 5.5

Vin Vcc=5V
G=1
1.0 5.0 Rl=10kΩ to Vcc/2
Vin T=25°C
Voltage (V)

Voltage (V)

Vout
0.5 4.5

Vout

0.0 4.0
Vcc=5V
G=1
Rl=10kΩ to Vcc/2
T=25°C
-0.5 3.5
-0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Time (µs) Time (µs)

DS15041 - Rev 2 page 12/22

 TSZ901
Typical performance characteristics

Figure 30. Settling time on negative input step Figure 31. Settling time on positive input step

0.005 0.005
Vcc=5V
0.004 0.004 Vicm=2.5V
Rl=10kΩ, Cl=47pF
0.003 0.003
T=25°C, G=-1
Output Error (V)

Output Error (V)

0.002 0.002 Input 3.5V to 2.5V
Output 1.5V to 2.5V
0.001 +0.1% 0.001 (Vout+Vin)/2 is plotted +0.1%

0.000 0.000

-0.001 -0.1% -0.001 -0.1%

Vcc=5V
Vicm=2.5V
-0.002 -0.002
Rl=10kΩ, Cl=47pF
-0.003 T=25°C, G=-1 -0.003
Input 1.5V to 2.5V
-0.004 Output 3.5V to 2.5V -0.004
(Vout+Vin)/2 is plotted
-0.005 -0.005
0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14
Time (µs) Time (µs)

Figure 32. Small step overshoot vs. Riso and vs. Cload Equivalent Input Voltage Noise Density (nV/VHz) Figure 33. Voltage noise density vs. frequency

140 VCC = 5V
100
120 VICM = 2.5V
100
Cload :
100pF
80
1nF
60
10nF
Overshoot (%)

40
Red : Vcc=2.5V
20
0 10
Blue : Vcc=5V

Vicm=Vcc/2
G=101
T=25°C
1
0 20 40 60 80 100 120 140 160 180 200 220 240 260 10 100 1k 10k 100k
Frequency (Hz)
Riso(Ohm)

Figure 35. Output linearity at VCC = 5 V

Figure 34. Noise vs. time at VCC = 5 V

200
3
180
Input Referred Voltage Noise (nV)

160
140 2 Vin
120
100
Vout Rl=600Ω
80 Vout Rl=10kΩ
60
1
Voltage (V)

40
20
0 0
-20
-40
-60
-80
-100
-120 Vcc=+/-2.5V Vcc=+/-2.5V
-140 Vicm=Vout=0V Vin=+/-2.5V
-160 25°C Cl=47pF
-180 Bandpass filter 0.1 to 10Hz T=25°C
-200
0 10
0 500 1000
Time (s)
Time (us)

DS15041 - Rev 2 page 13/22

 TSZ901
Typical performance characteristics

Figure 36. THD + noise vs. frequency Figure 37. THD + noise vs. VOUT

0.01 0.1
Vcc=5V
Gain=1
Vicm=Vrl=Vcc/2
Rl=10kΩ
THD + Noise (%)

THD + Noise (%)

BW=80kHz 0.01
T=25°C Plain : Vin=2Vpp
0.001 Red : f=1kHz

0.001 Vcc=5V
Rl=10kΩ
Dashed : Vin=4Vpp Gain=1 Blue : f=10kHz
Vicm=Vrl=2.5V
BW=22kHz
T=25°C
1E-4 1E-4
100 1k 10k 10m 100m 1
Frequency (Hz) AC Output Voltage (Vpp)

Figure 38. PSRR vs. frequency Figure 39. CMRR vs. frequency

120 120
Common Mode Rejection Ratio (dB)

Vcc=5V
Power Supply Rejection Ratio (dB)

Vicm=Vcc/2
100 100 Vin=1Vpp
Gain=11
Vcc-
T=25°C
80 Vcc+
80

60 Vcc=5V
Vicm=Vcc/2 60
Vripple=100mVpp
40 Gain=11
T=25°C 40

20
100 1k 10k 100k 1M 100 1k 10k 100k 1M
Frequency (Hz) Frequency (Hz)

Figure 40. EMIRR vs. frequency

150
140
130
120
EMI Rejection Ratio (dB)

110
100
90
80
70 Out
60 In+
50 Vcc+ Vcc=5V
40 Vicm=Vcc/2
30 Vin=-10dBm
20 Gain=1
10 T=25°C
0
10M 100M 1G
Frequency (Hz)

DS15041 - Rev 2 page 14/22

 TSZ901
Application information

5 Application information

5.1 Operating voltages

The TSZ901 device can operate from 2.5 to 5.5 V. The parameters are fully specified at 2.5 V, 3.3 V and 5 V
power supplies. However, the parameters are very stable over the full VCC range and several characterization
curves show the TSZ901 device characteristics over the full operating range. Additionally, the main specifications
are guaranteed over an extended temperature range from -40 to 125 °C.

5.2 Input offset voltage drift over the temperature

The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset
value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and
the amplifier input offset (Vio) is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can
be compensated during production at application level. The maximum input voltage drift over temperature enables
the system designer to anticipate the effect of temperature variations. The maximum input voltage drift over
temperature is computed using Equation 1.

ΔVio Vio_T − Vio_25°C

= max (1)
ΔT T − 25°C T = − 40°C and T = 125°C

The datasheet maximum value is guaranteed by a measurement on a representative sample size ensuring a Cpk
(process capability index) greater than 1.3.

5.3 Maximum power dissipation

The usable output load current drive is limited by the maximum power dissipation allowed by the device package.
The absolute maximum junction temperature for the TSZ901 is 150 °C. The junction temperature can be
estimated as follows:

T J = PD × θ JA + TA (2)

TJ is the die junction temperature.

PD is the power dissipated in the package.
θJA is the junction to thermal resistance of the package.
TA is the ambient temperature.
The power dissipated in the package PD is the sum of the quiescent power dissipated and the power dissipated
by the output stage transistor. It is calculated as follows:
PD = (VCC × ICC) + (VCC+ − VOUT) × IOUT when the op amp is sourcing the current.
PD = (VCC × ICC) + (VOUT − VCC−) × IOUT when the op amp is sinking the current.
Do not exceed the 150 °C maximum junction temperature for the device. Exceeding the junction temperature limit
can cause degradation in the parametric performance or even destroy the device.

5.4 PCB layout recommendations

Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load, and power
supply. The power and ground traces are critical as they must provide adequate energy and grounding for all
circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic
inductance. In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that
connects the bottom and top layer ground planes together in many locations is often used. The copper traces that
connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance.

5.5 Decoupling capacitor

In order to ensure full functionality of the op amp, it is mandatory to place a decoupling capacitor of at least 22 nF
as close as possible to the op amp supply pin. Proper decoupling will help to reduce electromagnetic interference
impact.

DS15041 - Rev 2 page 15/22

 TSZ901
Application information

5.6 Macromodel
Accurate macromodels of the TSZ901 device are available on the STMicroelectronics website at [Link].
These models are a trade-off between accuracy and complexity (that is, time simulation) of the TSZ901
operational amplifier. They emulate the nominal performance of a typical device within the specified operating
conditions mentioned in the datasheet. They also help to validate a design approach and to select the right
operational amplifier, but they do not replace on-board measurements.

DS15041 - Rev 2 page 16/22

 TSZ901
Typical applications

6 Typical applications

6.1 Low-side current sensing

Power management mechanisms are found in most electronic systems. Current sensing is useful for protecting
applications. The low-side current sensing method consists of placing a sense resistor between the load and the
circuit ground. The resulting voltage drop is amplified using the TSZ901.

Figure 41. Low-side current sensing schematic

C1

Rg1 Rf1

5V
In
Rshunt Vout

Ip
I
Rg2

Rf2

Vout can be expressed as follows:

Rg2 Rf1 Rg2 ⋅ Rf2

Vout = Rsℎunt ⋅ I 1 − ⋅ 1+ + Ip ⋅ (3)
Rg2 + Rf2 Rf2 Rg2 + Rf2
Rf1 Rf1
⋅ 1+ − In ⋅ Rf1 − Vio ⋅ 1 +
Rg1 Rg1

Assuming that Rf2 = Rf1 = Rf and Rg2 = Rg1 = Rg, Equation 3 can be simplified as follows:

Rf Rf
Vout = Rsℎunt ⋅ I ⋅ − Vio ⋅ 1 + + Rf ⋅ Iio (4)
Rg Rg

The main advantage of using the TSZ901 for a low-side current sensing relies on its low Vio, compared to general
purpose operational amplifiers. For the same current and targeted accuracy, the shunt resistor can be chosen
with a lower value, resulting in lower power dissipation, lower drop in the ground path, and lower cost. Particular
attention must be paid to the precision of Rg1 and Rf1, to maximize the accuracy of the measurement.
Note that the open-loop gains of the TSZ901 are defined close to the rail. It enables measurements over a wide
range of currents.

DS15041 - Rev 2 page 17/22

 TSZ901
Package information

7 Package information

To meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product
status are available at: [Link]. ECOPACK is an ST trademark.

7.1 SOT23-5 package information

Figure 42. SOT23-5 package outline

Table 7. SOT23-5 package mechanical data

Dimensions

Ref. Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 0.90 1.20 1.45 0.035 0.047 0.057

A1 0.15 0.006
A2 0.90 1.05 1.30 0.035 0.041 0.051
B 0.35 0.40 0.50 0.014 0.016 0.020
C 0.09 0.15 0.20 0.004 0.006 0.020
D 2.80 2.90 3.00 0.110 0.114 0.118
D1 1.90 0.075
e 0.95 0.037
E 2.60 2.80 3.00 0.102 0.110 0.118
F 1.50 1.60 1.75 0.059 0.063 0.069
L 0.10 0.35 0.60 0.004 0.014 0.024
K 0° 10° 0° 10°

DS15041 - Rev 2 page 18/22

 TSZ901
Ordering information

8 Ordering information

Table 8. Order codes

Order code Temperature range Package Marking

TSZ901ILT -40 °C to 125 °C SOT23-5 K250

TSZ901IYLT -40 °C to 125 °C, automotive grade (1) SOT23-5 K251

1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q002 or
equivalent. For qualification status detail, check " Maturity Status Link " on first page (" Quality & Reliability " tab on [Link]).

DS15041 - Rev 2 page 19/22

 TSZ901

Revision history
Table 9. Document revision history

Date Revision Changes

16-Sep-2025 1 Initial release.

Updated Φm, en p-p, trec and tinit values AC performance in Table 4,
10-Dec-2025 2 Table 5 and Table 6.
Added new Section 4: Typical performance characteristics.

DS15041 - Rev 2 page 20/22

 TSZ901
Contents

Contents
1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1.1 TSZ901 single operational amplifier (SOT23-5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.1 Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Input offset voltage drift over the temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Maximum power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4 PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5 Decoupling capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.6 Macromodel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6.1 Low-side current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
7.1 SOT23-5 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

DS15041 - Rev 2 page 21/22

 TSZ901

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
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DS15041 - Rev 2 page 22/22