Annual Conference of the Prognostics and Health Management Society, 2010

Modeling SiO2 Ion Impurities Aging in Insulated Gate

Power Devices Under Temperature and Voltage Stress

Antonio E. Ginart1, Irfan N. Ali1, José R. Celaya2, Patrick W. Kalgren1, Scott

D. Poll3, and Michael J. Roemer1
1
Impact Technologies, LLC, Rochester, NY, 14623, USA
[Link]@[Link]
[Link]@[Link]
[Link]@[Link]
[Link]@[Link]
2
SGT NASA Ames Research Center, Moffett Field, CA, 94035, USA
[Link]@[Link]
3
NASA Ames Research Center, Moffett Field, CA, 94035, USA
[Link]@[Link]

ABSTRACT reliability, especially for power devices has improved

markedly in the last decades but at the same time
This paper presents a formal computational interest in life assessment for end of life predictions
methodology to explain how the oxide in with associated confidence levels has emerged as a
semiconductors degrades over time and the dependence very important area. This created a new space that
of oxide degradation on voltage and temperature merges the lessons learned from traditional reliability
stresses. The effects of aging are modeled and with early diagnosis and prognosis. We explore that
quantified by modification of the gate-source space in this work by using ion mobility as an aging
capacitance value. The model output is validated using indicator in insulated gate power devices, such as
experimental results of a thermally aged power IGBTs and Power metal oxide semiconductor field
semiconductor device.* effect transistors (MOSFETs).

2. POWER SEMICONDUCTOR STRUCTURE

1. INTRODUCTION
The main silicon power devices are power MOSFETs
Device aging produces shifts in threshold voltage (Vth)
and IGBTs; the first are used mainly in applications
and capacitance parameters, primarily due to mobility
with less than 200 Volts while IGBTs are the preferred
of impurities, especially Na+ Ion (Kerr et al., 1964).
option for greater voltages. The power device structures
This phenomenon was an important reliability issue in are different from the highly integrated low power
the early stages of MOSFET fabrication because of the devices because they use different manufacturing
primitive fabrication process. As the manufacturing
processes and technologies. In order to support high
technology evolved and more pure silicon dioxide electric fields associated with the power, the preferred
material could be grown on devices, less importance
choice is vertical device construction with a large
was placed on ion migration loss in reliability research integration of dispositive in parallel. The geometric
(Miranda and Sune, 2004; Feinberg et al., 2000; disposition connecting individual devices in shunt
Feinberg and Widom, 2000). For power devices that
create well-known devices such as the HexFET™
are fabricated with vertical technology, oxide
(Clemente et al).
contamination and field distortion are the predominant
failures (Clemente and Teasdale, 1993). Semiconductor
2.1 Power MOSFET Structure
*
This is an open-access article distributed under the terms of A general structure of a vertical power MOSFET
the Creative Commons Attribution 3.0 United States License, device is shown in Figure 1. A power device is
which permits unrestricted use, distribution, and reproduction constructed by creating a mesh of vertical devices
in any medium, provided the original author and source are positioned in parallel to create high power. Therefore,
credited.

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 Annual Conference of the Prognostics and Health Management Society, 2010

the structure shown in Figure 1 is connected in parallel

to be combined into a power MOSFET.

Source Gate Source Field

contact contact contact Oxide

N+ Source
N+

Polysilicon
Gate
Channel
P- P-

Gate Oxide

N epi

N+ Substrate

Drain Contact

Figure 1: Structure of a commercial vertical power

MOSFET
Figure 3: IGBT parasitic structure and circuit
Parasitic components define the properties and representation
behavior of a semiconductor power device. These
properties change over time, providing important tools Figure 4 shows the two components (fast diode and
for early precursors to failures. Figure 2 shows a N-Type IGBT) integrated into the power device and
diagram with the material that creates the oxide and the encapsulated in the TO-220AB package corresponding
disposition of the main three parasitic capacitors that to the IGBT IRG4BC30KD from International
are characteristic of a power semiconductor: Cgs (gate- Rectifier. It also shows the X ray image of the IGBT
to-source), Cds (drain-to-source), and Cgd (gate-to- with a freewheeling diode as part of the device
drain). package.
Gate
Source
Cgs Cox

n+ Cgd
Cs p n+
p Drain-body

Cds Depletion layer

n-
n+
drain
Figure 2: Parasitic component of a vertical power
MOSFET

2.2 IGBT Structure

The parasitic structure of the IGBT is similar but more Figure 4: Structure of a commercial vertical power
complex than the vertical MOSFET shown in the IGBT
previous section. Due to the similarity of the internal
parasitic structure, this paper performed the 2.3 Power Device Stress Factors
experimental result on the IGBT, as the results should
be similar. Figure 3 shows a detail of the parasitic Industry reliability practices have led to classification
structure and the circuit representation of the IGBT. of vertical power devices stress and failure factors in
two distinct categories: silicon die defects and die

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 Annual Conference of the Prognostics and Health Management Society, 2010

packaging defects (Scroder, 1990; Clemente et al., gate and drain currents are show. It should be noted that
1993; Crook, 1979). The die defects in MOSFETs are subfigures (a) through (d) in Figure 5 are correlated
generally categorized under field distortion defects and with stages 1 through 4 in Figure 6. These figures show
oxide defects. Field distortion defects are a result of the the effect of parasitic capacitance on the characaristic
electric field in the MOSFET getting distorted. This waveforms of the device.
distortion is caused when a high voltage is applied to
the device in presence of polar molecules. A polar
molecule is such that one end of the molecule is
positively charged and the other end is negatively
charged (e.g., water and atmospheric ionic
contaminants). Oxide defects are the second most
common failures associated with die defects. Defects in
the MOSFET’s layer of gate oxide can cause failures
such as short-circuiting from gate to source. These
defects are often caused by thermal damage due to
thermal cycling, which in turn leads to more trap
generation. These traps cause more conduction and
eventually the short-circuiting.
The die packaging defects fall under several
categories: die attach damage, wire bond fatigue, and
metal corrosion. Die attach defects are caused by
thermal differentials created between the die and the
headers of the MOSFET devices. The ultimate result is
creation of voids and cracks in the die attach region
leading to degradation in the on resistance and thermal
resistance of the device. Wire bond fatigue is also
thermally induced and results in the separation of the Figure 5: Capacitance interaction during switch-on
wire bond of the MOSFET device. Finally, metal
corrosion occurs due to intrusion of water particles into
the device packaging through the atmosphere.
Naturally, introduction of water in the metallic
contact area leads to corrosion and that eventually
results in device degradation in the form of on-state
resistance shift.

3. SWITCHING PROCESS
Figure 5 shows how the different parasitic capacitances
influence the switching turn-on process (Mohan, et. al).
The subfigures (a) through (d) show the equivalent
circuit for the MOSFET to estimate the characteristic
voltage and current in the device as the switching
process progresses. Figure 5 (a) and (b) show how the
power transistor begins to switch with the current
initially circulating by the freewheeling diode DF. Figure 6: Effects of parasitic capacitance as a function
During these stages, the influence of Cgd (gate-to- of time
drain) and Cd (drain-to-source) with RG, the gate
resistance, is very important. In the final stages shown Given the influences of internal parasitic elements
as (c) and (d) RDS, drain-to-source resistance, together of power semiconductors, it is then important to
with Cgd defines the process. classify the effects of aging in these parasitic elements.
Figure 6 summarizes the influences of the Figure 7 shows a schematic of how aging can be
capacitances in the switching time during on-state and represented in changes of parasitic capacitance over
how the variation in the values of the parasitic time. Figure 7 shows the model of the power MOSFET
parameters will affect the time spent in the different with the relevant parasitic elements during switch on
stages. The gate drive voltage signal is a step response process. The (a) thorugh (d) subfigures show the model
whereas the other gate to source voltage (VGS) and simplification by lumping the components together.
Increasing the power losses during switching can be

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 Annual Conference of the Prognostics and Health Management Society, 2010

represented as regular increases of the value of RG. Where:

Moreover, the changes in the capacitance by ion AF: Acceleration factor
movement or new trap charges can be accounted for as TDH: Total duration hours
changes in CG over time. Section 7 provides more Semiconductor manufacturers perform millions of
details as to how this process occurs. Figure 7(d) is the hours of testing to determine failure rates. This gives
model this paper considered for evaluation, specifically extremely valuable information for the reliability of
the Cg is the parastic element that modeled and their product. Additionally, applying this concept with
monitored in the aged power device to characterize the more emphasis on the acceleration factor yields
aging effects. Other works (Celaya [Link], 2009) have important information for life estimation.
used on-resistance RDS on as an indicator of device The AF is generally determined from the Arrhenius
aging. equation but can also be determined using a power law,
as is common industry practice.
VG
CDG
D D 4.1 Field Distortion Acceleration Model
CDS RDG
Subs G Acceleration models for the reduction of life in
G
equipment have been used extensively. Representative
S examples include the Arrhenius model for temperature
RDS S RGS
CGS (Leblebici and Kang, 1993):
E

(b)
L(T ) = AF ⋅ e kT
(3)
(a)
D D
RDS ON
The acceleration factor, AF, is determined generally
RDS ON
from the Arrhenius model:
G G
E  1 1 
CG AF = exp a  −  

(4)
S S RG  k  T1 T2  
D.L Crook (Crook, 1979) proposed the following
expression in the case of two acceleration factors
(c) (d) (temperature and voltage):
Figure 7: Power device simplified circuit aging
 E  1 1   E − E1 
4. POWER DEVICE RELIABILITY
AF = exp a  −   ⋅ exp − 2  (5)
 k  T1 T2    E c 
The previous section highlights some of the common where:
and widely accepted reliability issues presented with
Ec has been experimentally (Crook) been
the design and operation of MOSFET/IGBT power
devices. In this section, traditional semiconductor
shown to equal 0.062 MV/cm.
Equation 6 shows the Power Law that is used
reliability concepts are related to remaining life
commonly in determining the life expectancy of power
estimation.
devices based on the data presented in (Pearce et al.)
From a reliability engineering point of view, the
Several manufacturers use gate voltages and
failure rates caused by factors described in the previous
temperatures for aging estimation. Based on the data
section have to be addressed and taken into
(Pearce et al.) the values for the IRF4XX series are
consideration.
computed to be A=-17.2, B=0.4, C=-0.15 and the
The mean time to failure (MTTF) is usually defined
respective curves are shown in Figure 8.
by the inverse of the failure rate of devices:

MTTF =
1
(1) AF = A * 10CT * 10B*VG + a (6)
λ
where λ is the failure rate. The thermal activation energy of a failure
A failure rate (λ) could be estimated by mechanism is determined by testing at a minimum of
1 two different temperature stress levels as is shown in
λ∝ (2) Figure 8. Figure 8 shows the power MOSFET life
TDH * AF expectancy using Power Law shown in equation 6. It
can be seen that the life expectancy of MOSFET

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 Annual Conference of the Prognostics and Health Management Society, 2010

devices changes with the varying bias voltages and are the aged devices resulting in a drop of collector-emitter
uniformly changing as the operating temperature ON voltage.
changes. In lab testing and field operations, it has been
shown that device’s failure gets accelerated when 14
Power MOSFET Life Expectancy
10
operated in higher temperature regions.
4V
12
10
8V
10
10
12V
8
10

Hours
16V
6
10
20V
4
10
24V
2
10

0
10
50 100 150 200 250 300
Temperature(Celsius)

Figure 9: Power MOSFET life expectancy under the

Figure 8: Power MOSFET life expectancy under Power hybrid model
Law The devices under test are discrete IGBTs from
International Rectifier (IRG4BC30KD). These devices
Figure 9 illustrates the concept of using a hybrid are rated at 600V collector-emitter voltage, 15A
acceleration life expectancy modeling. The hybrid collector current and are in a TO-220 package.
model concept combines the Power Law and Arrhenius 5.1 Accelerated Aging System
models. Doing so allows for a more realistic
representation of life expectancy of power MOSFET In order to evaluate the aging effects in power
devices based on extensive reliability studies and semiconductors, accelerated aging systems have been
operational usage. The two stress factors, temperature used to quickly induce aging effects in devices while
and bias voltage, take predominant effects in different keeping them operational. The aging system used for
regions based on the level of temperature stress. At low this experiment is described in detail in (Saha et al.,
temperatures, the bias voltage remains the dominant 2009). The system allows for accelerated aging of gate
factor; however, at high temperature a new controlled power transistors like power MOSFETs and
phenomenon rules the process. At higher temperatures, IGBTs. Custom-made software controls the accelerated
the life expectancy goes down much faster in life experiments and logs data for further analysis. A
accordance with the Arrhenius model. Moreover, the high level block diagram is presented in Figure 10;
variation in the gate voltages does not remain a factor details on the hardware and software implementations
in the life expectancy for all but the 24 V bias voltages are available in (Sonnenfeld et al., 2008).
as shown in Figure 9. In terms of accelerated life testing, the system can
apply different stresses like thermal, electrical or a
combination of them. The focus here is on thermal
5. THERMAL AGING
cycling which is achieved by doing power cycling on
The devices under test for this study are the same the devices under test. The system allows the
devices used for the identification of precursors of investigation of different failure mechanisms (intrinsic
IBGT failure presented in (Celaya et al., 2009). Several and extrinsic) like dielectric breakdown, hot-carrier
IGBTs were aged under thermal overstress in order to injection, electro-migration, contact migration, wire lift,
accelerate the life of the components through latch-up die-attach degradation and package delamination. This
failure or thermal runaway. The thermal overstress was aging system was designed based on the work
generated by power cycling the devices, resulting in a presented in (Ginart et al., 2007) and it has been used in
controlled thermal cycling. As stated in (Patil et al., the aging of IGBTs and power MOSFETs in order to
2009), it was observed that for aged devices, there is an understand failure mechanisms, identify precursors of
increase in threshold voltage and C-V tests were used failure, and develop degradation models for prognostics
to identify the failure mechanism. In addition, die and health management of these devices (Celaya et al.,
attach degradation was observed in CSAM images of 2009; Patil et al., 2009; Saha et al., 2009; Sonnenfeld et
al., 2008).

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 Annual Conference of the Prognostics and Health Management Society, 2010

runaway. The aging time (time to failure) under these

aging conditions ranged from 30 minutes to 2 hours.
Additional details are documented in (Celaya et al.,
2009).

6. SIMULATION & RESULTS

6.1 Aging Stress Factor and Capacitance Shift

The capacitance mainly changes by mobility of trap
charges during fabrication and additional traps
generated during operation as shown in Figure 11.
These charges are created mainly from bias voltages
and temperature. Regardless of the origins of the
impurities, the mobility of impurities produces a
variation of capacitances that can be used as an
indicator of aging in the semiconductor devices. Aging
in semiconductors usually has multiple failure
mechanisms that develop simultaneously before the
predominant mechanism becomes evident and finally
Figure 10: High-level diagram of accelerated aging leads to device failure. In vertical device structures the
system main failure mechanisms that have been reported are:
void formation from the packaging side and from the
5.2 Aging experiments device itself (Saha et al., 2009; Sonnenfeld et al., 2008;
Ginart et al., 2007; Srinivasan, 2000), oxide damage
The accelerated aging applied to the devices presented and field distortion (Pearce et al., 1993). Void
in this work consists of thermal cycling to accelerate formation leads to increase of the junction temperature
degradation using thermal overstress. The failure which in turn leads to failures. The oxide damage and
condition was considered as latch-up or thermal field distortion mechanisms are the main focus of this
runaway. Thermal cycles were induced by power work. For both failure mechanisms the capacitance
cycling the devices without the use of external heat changes with the realignment of the trap impurities,
sink. This reduced the heat dissipation capabilities of showing the aging progression in the Si02.
the devices, allowing the self-heating of the device due
to the power switching operation. The IGBT package
temperature was the controlled variable for the thermal Metal mobilityreducebythepresent of Trap Charges RA1

cycling. The temperature was measured in situ using an

infrared sensor. For the aging power cycle, the gate
voltage was a square signal with amplitude of 8V, a
CA1
frequency of 1 KHz and a duty cycle of 40%. Proper SemiconductorTrap Charges
amplification of the signal ensured that enough current
is available to charge the gate of the IGBT at the SiO2Damage AgingModel
selected frequency and duty cycle. The collector-
emitter was biased at 4V and a resistive load on the RA1 t Time
constant
order of 0.5 ohms was used on the collector side of the
device. VG
The temperatures are controlled within low and high
temperature bounds. The device was set on the power
cycling regime if the case temperature was below the
n+ +n
lower threshold and it was turned completely off if the
temperature reached the upper threshold. This
hysteresis controller provided the thermal cycles
needed to accelerate the age of the device. It should be Figure 11: Metal mobility reduced by the presence of
noted that currents and voltages were maintained within trap charges
the safe operating area while the temperature was
raised beyond the maximum rating to induce latch-up. The IGBT parameters for the device used in for
The high temperature bound was set to 300oC, resulting evaluation in this paper are shown in Table 1. The
in failed IGBTs due to loss of gate control or thermal

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 Annual Conference of the Prognostics and Health Management Society, 2010

IGBT device used in this paper is IRG4BC30KD from Co

International Rectifier. C= (9)
KW
1+ o t
Table 1: IRG4BC30KD relevant parameters K s xo
where Wt is the depletion width calculated by
1/ 2
 2K ε 
Wt =  S o (φ ox ) (10)
 qN A 
where φ ox is the oxide potential related to the
semiconductor doping concentration, and Co is the
oxide capacitance computed by
K o ε 0 AG
Co = (11)
xo
where AG is the gate area.
Following the Arrhenius equation shown in
Equation 5, the diffusion-like movement of trap charge
impurities caused by stress induced aging is modeled as
time moves forward. The diffusion process mobilizes
the impurities in an exponential fashion as a function of
temperature and the bias voltage, VG, thus changing the
oxide potential as defined in Equation 7. Therefore, the
change in the oxide potential leads to the depletion
width changing ultimately produces the shift in the
device capacitance with respect to the voltage.
Figure 12, Figure 13, and Figure 14 show the
6.2 Fundamental equations and modeling MATLAB simulation results of the mobility of the trap
charge impurities in the power devices and the
In this work, only the initial trap charge is included in corresponding shift in the capacitance. The simulation
the model whereas the trap generation process will be results are shown for the time scale of one, ten, and
included in the continuing future work. The equations thirty years. The temperature was kept constant at
that govern the potential changes in the oxide 100oC along with the initial trap charges and the gate
semiconductor interface are shown below (Pierret, voltage VG was set at 8V. The impurities, represented
1996): per m2, are shown to migrate over time from being
uniformly distributed across the device (year 1) and
x0
K 1 aggregating on one end by year 30. Correspondingly,
∆φox = s xo ε S − ∫ xρ ( x)dx (7) the capacitance starts varying and the shift over time is
K oε S
ox
Ko o shown. The initial capacitance is shown in blue circles
whereas the simulated capacitance at the respective
time is shown in a red line, illustrating a clear shift in
where:
capacitance over time as migration of impurities starts
Ks is the semiconductor dielectric constant accelerating.
Ko is the oxide dielectric constant,
xo is the oxide thickness, 6.3 Experimental Results
εs is the electric field in the semiconductor at the
oxide-semiconductor interface, An experiment to validate the simulation results was
conducted on an IGBT, which has a similar gate
ρox is the charge density in the oxide.
structure as that of a MOSFET. The IGBT was
This implies that for the same ΦS: subjected to the stress profiled in Figure 15. The stress
estimated was equivalent to a reduction of the
x0 remaining useful life (RUL) of the IGBT device. This
1
∆VG = −
K oε S ∫ xρ
o
ox ( x)dx (8) estimation in the RUL is based on the life expectancy
law modeled for high temperature stress as shown in
Finally, computing the capacitance for a nonideal Figure 9.
MOSFET/IGBT

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 Annual Conference of the Prognostics and Health Management Society, 2010

350

300

250

Temperature (C)
200

150

100

50

0
3 5 7 9 40 44 45 47 49 56 57 58 60 65
Time (Minutes)
Figure 15: Temperature stress profile

Figure 16 shows the results of the shifting of the

IGBT transistor capacitance as a function of the gate
Figure 12: Migration of trap charges and capacitance voltage. The normalized results show the shift in
variation at year 1 with 100oC and VG =8V capacitance of the device before and after the device
underwent the accelerated aging described in the
previous section. As can be seen, the shifting of the
device produces similar results to those obtained in the
simulation. It should be noted that since MOSFETs and
IGBTs have similar gate structure as describe earlier,
the gate parasitic capacitance, that has been modeled
and tested, would have similar results for both devices.

1.25
Pre-aging
Post-aging
1.00
Capacitance

0.75

0.50
Figure 13: Migration of trap charges and capacitance
variation at year 10 with 100oC and VG =8V 0.25
-4 -2 0 2 4
Gate Voltage V

Figure 16: Capacitance shift of IGBT device before and

after accelerated aging

7. CONCLUSION
Analytical and numerical relationships between the
semiconductor physics-based behavior and stress
factors through capacitance shifting was presented.
This work successfully modeled the capacitance and
the subsequent changing due to device aging. The
combination of the aging stress voltages and
temperature produces shifting in the impurities of oxide
that modifies the relationship of the gate capacitance
value and the gate voltages, resulting in a good
indicator of device aging. As mentioned previously,
Figure 14: Migration of trap charges and capacitance
variation at year 30 with 100oC and VG =8V

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 Annual Conference of the Prognostics and Health Management Society, 2010

future work will also include the trap charge generation devices”, Microelectronics Reliability, Vol. 44, pp.
phenomenon in the modeling and validation. 1-23. 2004.
Feinberg, A.A., Ersland, P., Kaper, V., and Widom, A.,
ACKNOWLEDGMENT
“On aging of key transistor device parameters,” in
The authors would like to acknowledge and appreciate Proc. Inst. Environmental Sciences &Technology,
the help extended for this work by Nishad Patil. 2000, pp. 231–236.
Feinberg, A.A., Widom, A., “On Thermodynamic
NOMENCLATURE Reliability Engineering.” IEEE TRANSACTIONS
L(T) life under thermal conditions ON RELIABILITY, VOL. 49, NO. 2, JUNE 2000.
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C, D experimental constant Characterization”, John Wiley and Sons, New
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T temperature in Kelvin Ginart, A., Brown, D., Kalgren, P.W., Roemer, M.J.,
k Boltzmann’s constant 8.6171.10-5 eV /oC “On-line Ringing Characterization as a PHM
Si02 Silicon dioxide Technique for Power Drives and Electrical
dt time step Machinery,” Autotestcon, 2007 IEEE. 7-20 Sept.
f, g generic functions 2007 pp 654 – 659.
I current Katsis, D.C., “Thermal Characterization of Die-Attach
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q magnitude of the electron charge (1.6 x 10-19 Virginia Polytechnic Institute. 2003.
coul) Katsis, D.C. ,van Wyk, J.D., “Void-induced thermal
V Voltage impedance in power semiconductor modules: some
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 Annual Conference of the Prognostics and Health Management Society, 2010

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