Module 5
Useful Modeling Techniques
Course Instructors:
A Section: Ms Rupal D’Souza
B Section : Ms K Aarya Shri
Objective
❏ To describe procedural continuous assignment statements
assign, deassign, force, and release. Explain their significance
in modeling and debugging.
❏ To understand how to override parameters by using the
defparam statement at the time of module instantiation.
❏ To explain conditional compilation and execution of parts of the
Verilog description.
❏ To identify system tasks for file output, displaying hierarchy,
strobing, random number generation, memory initialization, and
value change dump.
Topics
❏ Procedural Continuous Assignments
❏ Overriding Parameters
❏ Conditional Compilation and Execution
❏ Time Scale
❏ Useful System Tasks
Procedural Continuous Assignments
❏ Procedural assignments assign a value to a register.
❏ The value stays in the register until another procedural
assignment puts another value in that register.
❏ Procedural continuous assignments are procedural
statements which allow values of expressions to be driven
continuously onto registers or nets for limited periods of time.
❏ Procedural continuous assignments override existing
assignments to a register or net. They provide an useful
extension to the regular procedural assignment statement.
assign and deassign
❏ The keywords assign and deassign are used to express the first
type of procedural continuous assignment.
❏ The left-hand side of procedural continuous assignments can be
only be a register or a concatenation of registers. It cannot be a
part or bit select of a net or an array of registers.
❏ Procedural continuous assignments override the effect of regular
procedural assignments.
❏ Procedural continuous assignments are normally used for
controlled periods of time.
Ex: D-Flipflop with Procedural Continuous
Assignments
module edge_dff(q, qbar, d, clk,
reset);
output q,qbar; assign q = 1'b0;
assign qbar = 1'b1;
input d, clk, reset; end
reg q, qbar; else
always @(negedge clk) begin
begin deassign q;
q = d; deassign qbar;
qbar = ~d; end
end endmodule
always @(reset)
if(reset)
begin
force and release
❏ Keywords force and release are used to express the second
form of the procedural continuous assignments.
❏ They can be used to override assignments on both registers
and nets.
❏ force and release statements are typically used in the
interactive debugging process, where certain registers or nets
are forced to a value and the effect on other registers and nets
is noted.
❏ force and release statements should appear only in stimulus or
as debug statements.
force and release on registers
module stimulus;
...
❏ A force on a register overrides any ...
procedural assignments or edge_dff dff(Q, Qbar, D, CLK,
procedural continuous assignments RESET);
on the register until the register is ...
...
released.
initial
❏ The register variables will continue
begin
to store the forced value after being #50 force dff.q = 1'b1;
released, but can then be changed #50 release dff.q;
by a future procedural assignment. end
...
...
endmodule
force and release on nets
module top;
❏ force on nets overrides any
...
continuous assignments until the ...
net is released. assign out = a & b & c;
❏ The net will immediately return to ...
its normal driven value when it is initial
released. begin
❏ A net can be forced to an #50 force out = a | b & c;
expression or a value. #50 release out;
end
...
...
endmodule
Overriding Parameters
● There are two ways to override parameter values:
○ through the defparam statement
○ through module instance parameter value assignment.
defparam Statement
❏ Parameter values can be changed in any module instance in
the design with the keyword defparam.
❏ The hierarchical name of the module instance can be used to
override parameter values.
❏ Multiple defparam statements can appear in a module. Any
parameter can be overridden with the defparam statement.
defparam Statement
module hello_world;
parameter id_num = 0;
initial
$display("Displaying hello_world id
number = %d", id_num);
endmodule
module top;
defparam w1.id_num = 1,
w2.id_num = 2;
hello_world w1();
hello_world w2();
endmodule
ANSI C Style Parameter Declaration
module hello_world # (parameter id_num = 0);
initial
$display("Displaying hello_world id number = %d",
id_num);
endmodule
Module_Instance Parameter Values
❏ Parameter values can be overridden when a module is
instantiated
❏ If multiple parameters are defined in the module, during module
instantiation, they can be overridden by specifying the new
values in the same order as the parameter declarations in the
module.
❏ If an overriding value is not specified, the default parameter
declaration values are taken.
❏ One can override specific values by naming the parameters and
the corresponding values. This is called parameter value
assignment by name.
Examples
module top;
hello_world #(1) w1;
hello_world #(.id_num(2)) w2;
endmodule
Examples
module bus_master;
parameter delay1 = 2; module top;
parameter delay2 = 3; bus_master #(4, 5, 6) b1();
parameter delay3 = 7; bus_master #(9, 4) b2();
endmodule bus_master #(.delay2(4), delay3(7)) b3();
endmodule
Conditional Compilation and Execution
Conditional Compilation
❏ Conditional compilation can be accomplished by using
compiler directives `ifdef, `ifndef, `else, `elsif, and `endif
Conditional Compilation
module top;
'ifdef TEST bus_master b1();
module test;
... 'ifdef ADD_B2
... bus_master b2();
endmodule
'else 'elsif ADD_B3
module stimulus; bus_master b3();
...
'else
...
endmodule bus_master b4();
'endif 'endif
'ifndef IGNORE_B5
bus_master b5();
'endif
endmodule
❏ The `ifdef and `ifndef directives can appear anywhere in the
design.
❏ The `else directive is optional. A maximum of one `else
directive can accompany an `ifdef or `ifndef.
❏ Any number of `elsif directives can accompany an `ifdef or
`ifndef. An `ifdef or `ifndef is always closed by a
corresponding `endif.
Conditional Execution
❏ Conditional execution flags allow the designer to control
statement execution flow at run time.
❏ All statements are compiled but executed conditionally.
❏ Conditional execution flags can be used only for behavioral
statements.
❏ The system task keyword $test$plusargs and $value$plusargs
are used for conditional execution.
Conditional Execution with $test$plusargs
module test;
...
...
initial
begin
if($test$plusargs("DISPLAY_VAR"))
$display("Display = %b ", {a,b,c} );
else
$display("No Display");
end
endmodule
Conditional Execution with $value$plusargs
module test; $display("Test name option not
reg [8*128-1:0] test_string; specified");
integer clk_period; if($value$plusargs("clk_t=%d",
...
... clk_period))
initial forever #(clk_period/2) clk =
begin ~clk;
if($value$plusargs("testname=%s", else
test_string))
$display("Clock period option
$readmemh(test_string, vectors);
else name not specified");
end
endmodule
Time Scales
❏ Delay values in one module need to be defined by using certain time
unit
❏ delay values in another module need to be defined by using a
different time unit
❏ `timescale compiler directive - specify time units in verilog
❏ Syntax
`timescale <reference_time_unit> / <time_precision>
❏ Reference_time_unit - unit of measurement for times and delays
❏ Time_precision - precision to which the delays are rounded off
Example
`timescale 100 ns / 1 ns
module dummy1;
reg toggle;
initial
toggle = 1'b0;
always
begin
#5 toggle = ~toggle;
$display("%d, In %m toggle = %b ", $time, toggle);
end
endmodule
Example
`timescale 1 us / 10 ns
module dummy2;
reg toggle;
toggle = 1'b0;
initial
always #5
begin
toggle = ~toggle;
$display("%d , In %m toggle = %b ", $time, toggle);
end
endmodule
Result
❏ Both Program are identical
❏ Differed by timescale
❏ Dummy 1 executes 10
times more than dummy2
Useful System Task
❏ Files
❏ Display hierarchy
❏ Strobing
❏ Random number generation
❏ Memory initialization
❏ Value change dump
Files
❏ $fopen - open the file
❏ Usage: $fopen("<name_of_file>");
Usage: <file_handle> = $fopen("<name_of_file>");
❏ $fdisplay , $fmonitor, $fwrite and $fstrobe - write data into file
$fdisplay(<file_descriptor>, p1, p2 ..., pn);
$fmonitor(<file_descriptor>, p1, p2,..., pn);
❏ $fclose - close the file
Usage: $fclose(<file_handle>);
Example
integer handle1, handle2, handle3;
initial
begin
handle1 = $fopen("[Link]"); //handle1 = 32'h0000_0002 (bit 1 set)
handle2 = $fopen("[Link]"); //handle2 = 32'h0000_0004 (bit 2 set)
handle3 = $fopen("[Link]"); //handle3 = 32'h0000_0008 (bit 3 set)
end
Example
integer desc1, desc2, desc3; //three file descriptors
initial
begin
desc1 = handle1 | 1; //bitwise or; desc1 = 32'h0000_0003
$fdisplay(desc1, "Display 1");//write to files [Link]
desc2 = handle2 | handle1; //desc2 = 32'h0000_0006
$fdisplay(desc2, "Display 2");//write to files [Link] & [Link]
desc3 = handle3 ; //desc3 = 32'h0000_0008
$fdisplay(desc3, "Display 3");//write to file [Link] only
end
Displaying Hierarchy
Hierarchy at any level can be displayed by means of the %m option
❏ $display,
❏ $write
❏ $monitor
❏ $strobe task,
Example
module M; module top;
...
... M m1();
initial M m2();
M m3();
$display("Displaying in %m"); endmodule
endmodule
Result :
Displaying in top.m1
Displaying in top.m2
Displaying in top.m3
Strobing
❏ Strobing is done with the system task keyword $strobe.
❏ similar to the $display
❏ Order of $display task depends on compiler execution
❏ $strobe provides synchronization mechanism to ensure that data
is displayed only after all other assignment statements
Example
always @(posedge clock)
begin
a = b;
c = d;
end
always @(posedge clock)
$strobe("Displaying a = %b, c = %b", a, c); // display values at posedge
Random Number Generation
❏ Required for generating a random set of test vectors
❏ catches hidden bugs in the design
❏ Random vector generation is also used in performance analysis of
chip architectures
❏ Usage: $random;
$random(<seed>);
Example
module test;
integer r_seed;
reg [31:0] addr;//input to ROM
wire [31:0] data;//output from ROM
...
ROM rom1(data, addr);
initial
r_seed = 2;
always @(posedge clock)
addr = $random(r_seed);
...
endmodule
Initializing Memory from File
❏ Two tasks are provided to read numbers in binary or hexadecimal format
❏ Keyword: $readmemb and $readmemh
❏ Usage
$readmemb("<file_name>", <memory_name>);
$readmemb("<file_name>", <memory_name>, <start_addr>);
$readmemb("<file_name>", <memory_name>, <start_addr>,<finish_addr>);
Example
module test;
reg [7:0] memory[0:7];
integer i;
initial
begin
$readmemb("[Link]", memory);
module test;
for(i=0; i < 8; i = i + 1)
$display("Memory [%d] = %b", i, memory[i]);
end
endmodule
Value Change Dump File
❏ A value change dump (VCD) is an ASCII file that contains information about
simulation time, scope and signal definitions, and signal value changes in the
simulation run.
❏ All signals or a selected set of signals in a design can be written
❏ Postprocessing tools can take the VCD file as input and visually display hierarchical
information, signal values, and signal waveforms
❏ Tasks
❏ $dumpvars
❏ $dumpfile
❏ $dumpon, $dumpoff
❏ $dumpall
Example
initial
$dumpfile("[Link]");
initial $dumpvars;
initial $dumpvars(1, top);
initial $dumpvars(2, top.m1);
initial $dumpvars(0, top.m1);
initial
begin
$dumpon;
#100000 $dumpoff;
end
Consider the 4-bit full adder. Write a stimulus file to do random testing of
the full adder. Use a random number generator to generate a 32-bit
random number. Pick bits 3:0 and apply them to input a; pick bits 7:4 and
apply them to input b. Use bit 8 and apply it to c_in. Apply 20 random test
vectors and observe the output.
Design block
module fulladd4(c_out,sum, a, b, c_in);
output [3:0] sum;
output c_out;
input[3:0] a, b;
input c_in;
assign {c_out, sum} = a + b + c_in;
endmodule
Stimulus block
module test;
wire [3:0] sum;
wire c_out;
reg [3:0] a, b;
reg c_in;
reg[31:0]addr;
fulladd4 f1 (c_out,sum, a, b, c_in);
Stimulus block
initial
begin initial
repeat (20) $monitor($time,"a=%b, b=%b,
begin c_in=%b,c_out=%b, sum=%b, ",a,b,c_in,
#10 addr=$random; c_out,sum);
a=addr[3:0]; endmodule
b=addr[7:4];
c_in=addr[8];
end
end
Output
THANK YOU