DSP Architecture
Special features that require operations like
FFT
Filtering
Convolution
Correlation
Real time sample-based & Block based processing
Dedicated hardware architecture
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Architecture of General Microprocessors
Von Neumann architecture
Instructions-numerical codes
Single shared memory for programs & data
Single bus for memory access
Arithmetic unit
Program control unit
Serial fetching & execution
Instruction: Opcode & Operand
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Digital Signal Processors
Harvard architecture
DSP has two separate memory spaces.
One is dedicated to the program code, while the other is
employed for data.
Two corresponding address buses and two data buses are used
Parallel operation
Additional unit-multiplier and accumulator (MAC)-used for
the digital filtering operation
Shift unit-scaling operation for fixed-point implementation
when the processor performs digital filtering.
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DSP
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Execution cycle
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DSP Hardware Units
Multiplier And Accumulator
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Shifters
Scaling-Preventing overflow
Scaling down-shift right(divide by 2 & truncating fraction
part)
Example, for a 3-bit data word 0112 =310, shifting 011 to the
right gives 0012 = 1, that is, 3/2 = 1.5, and truncating 1.5
results in 1.
Scaling up-shift left (multiplying by 2)
Shifting the same number to the left, we have
1102 =610, that is, 3 *2 = 6
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Address Generators
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Formats
Fixed point DSP
2’s complement integer format
Integer arithmetic
Narrow dynamic range
Overflow may occur
Floating Point DSP
mantissa(fractional part) & exponent in addition to integer
format
Floating point arithmetic
Wide dynamic range
More hardware-expensive & slow
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Fixed point format
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System treating decimal values as
fractional numbers
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Q-15 (Fixed Point) format
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Q-N (Fixed Point) format
Less accurate due to truncation error
Addition & Subtraction Overflow
Underflow
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Floating Point Format
M-Mantissa
E-Exponent
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IEEE Floating Point Format
Single Precision Format
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Double Precision format
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Fixed Point Digital Signal Processor
Manufacturers-Analog Device, Texas Instruments, Motorola
Analog Devices offers a fixed-point DSP family such as
ADSP21xx.
Texas Instruments provides various generations of fixed-
point TMS320C1x (first generation), TMS320C2x,
TMS320C5x, and TMS320C62x.
Motorola manufactures varieties of fixed-point processors,
such as the DSP5600x family.
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TMS320C54x
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The fixed-point TMS320C54x families supporting 16-bit data
have on-chip program memory and data memory
Data RAM (random access memory) and program ROM
(read-only memory) used for program code, instruction, and
data.
Four data buses and four address buses
The program memory address bus and program memory
data bus are responsible for fetching the program instruction.
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C and D data memory address buses and the C and D data
memory data buses deal with fetching data from the data memory
E data memory address bus and the E data memory data bus are
dedicated to moving data into data memory.
E memory data bus can access the I/O devices.
Computational units consist of an ALU, an MAC, and a shift unit.
For TMS320C54x families, the ALU can fetch data from the C, D,
and Program memory data buses and access the E memory data
bus.
Two independent 40-bit accumulators, which are able to operate
40-bit addition.
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The multiplier, can fetch data from C and D memory data buses
and write data via the E memory data bus, is capable of operating
17-bit *17-bit multiplications.
The 40-bit shifter has the same capability of bus access as the
MAC.
The program control unit fetches instructions via the program
memory data bus.
In order to speed up memory access, there are two address
generators available:
one responsible for program addresses and one for data addresses.
Advanced Harvard architecture is employed
Processing performance offers 40 MIPS (million instruction sets
per second).
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Floating Point Processors
Floating-point DS processors perform DSP operations using
floating-point arithmetic
Advantages-Getting rid of finite word length effects such as
overflows, round-off errors, truncation errors, and
coefficient quantization errors.
High-performance speed and calculation precision
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TMS320C3x
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The processor has a large memory space and is equipped with
dual-access on-chip memories.
A program cache is employed to enhance the execution of
commonly used codes.
Uses the Harvard architecture
There also exist memory buses and data buses for direct-
memory access (DMA) for concurrent I/O and CPU
operations
Peripheral access such as serial ports, I/O ports, memory
expansion, and an external clock.
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The C3x CPU contains the floating-point/integer multiplier;
an ALU
32-bit barrel shifter; internal buses; a CPU register file; and
dedicated auxiliary register arithmetic units (ARAUs).
The multiplier operates single-cycle multiplications on 24-bit
integers and on 32-bit floating-point values.
Parallel instructions-Fast
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ARAU-circular buffering and bit-reversal addressing (digital
filtering and FFT operations).
The CPU register file offers 28 registers
Special functions of the registers include eight extended 40-
bit precision registers for maintaining accuracy of the
floating-point results.
Eight auxiliary registers can be used for addressing and for
integer arithmetic.
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The prominent feature of C3x is its floating-point capability
Three floating-point formats are supported.
A short 16-bit floating-point format has 4 exponent bits, 1 sign
bit, and 11 mantissa bits.
A 32-bit single precision format has 8 exponent bits, 1 sign bit,
and 23 fraction bits.
A 40-bit extended precision format contains 8 exponent bits, 1
sign bit, and 31 fraction bits.
The TMS320C30 offers high-speed performance with 60
nanosecond single cycle instruction execution time
Equivalent to 16.7 MIPS.
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FIR & IIR Filter Implementations in
fixed point systems
Input data, filter coefficients, and processed output data to be
in the Q-format
Can avoid overflow due to multiplications and can prevent
overflow due to addition by scaling input data
When the filter coefficients are out of the Q-format range,
coefficient scaling must be done
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First, to avoid overflow for an adder, we can scale the input
down by a scale factor S,
where h(k) is the impulse response of the adder output and
Imax the maximum amplitude of the input in Q-format.
The adder output can actually be expressed as a convolution
output:
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Scaling down of the input by a factor of S will guarantee that
the output of the adder is in Q-format.
The idea is that scaling down the coefficients will make them
less than 1, and later the filtered output will be scaled up by
the same amount before it is sent to DAC.
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Direct Form II realization
Decomposing H(z) into product of two transfer functions
H1(z) and H2(z). The transfer function H1(z) is an all pole
filter while H2(z) is an all zero filter
H(z)=H1(z)H2(z)
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No of Delay
Blocks - N
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Fixed point implementation of Direct
Form-II
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