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VHDL Code for Arithmetic Circuits

The document contains VHDL code for various digital components including full adders, multiplexers, and shift registers. It defines entities and architectures for each component, detailing their input and output ports, as well as the logic operations performed within them. The code is structured for simulation and synthesis in digital design applications.

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vutrithang142857
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2 views6 pages

VHDL Code for Arithmetic Circuits

The document contains VHDL code for various digital components including full adders, multiplexers, and shift registers. It defines entities and architectures for each component, detailing their input and output ports, as well as the logic operations performed within them. The code is structured for simulation and synthesis in digital design applications.

Uploaded by

vutrithang142857
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd

codeHA: FA:

library IEEE; library IEEE;


use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL; use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL; use IEEE.STD_LOGIC_arith.ALL;
entity FA is entity FA is
port( port(
A : in bit; A : in bit;
B : in bit; B : in bit;
Ci : in bit; Ci : in bit;
S : out bit; S : out bit;
Co : out bit Co : out bit
); );
end FA; end FA;
architecture chuyen of FA is architecture chuyen of FA is
begin begin
S <= A xor B xor Ci; S <= A xor B xor Ci;
Co <= (A and B) or (Ci and (A xor Co <= (A and B) or (Ci
B)); and (A xor B));
end chuyen; end chuyen;

\FS/ library IEEE; \HS/library IEEE;


library IEEE; use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all; entity HS is
library work; port (
use [Link]; A: in std_logic;
entity FS is B: in std_logic;
port ( D: out std_logic;
A_FS: in std_logic; Bo: out std_logic);
B_FS: in std_logic; end entity HS;
Bin: in std_logic; architecture cau_truc of HS is
D_FS: out std_logic; begin
Bo_FS: out std_logic); D <= A xor B;
end FS; Bo <= (not A) and B;
architecture cau_truc of FS is end cau_truc;
signal C: std_logic_vector(1 downto 0);
signal E: std_logic;
component HS
port (A: in std_logic;
B: in std_logic;
D: out std_logic;
Bo: out std_logic);
end component;
for u0: HS use entity [Link](cau_truc);
for u1: HS use entity [Link](cau_truc);
begin
u0: HS port map(A=>A_FS, B=> B_FS, D=>E, Bo=>C(0));
u1: HS port map(A=>E, B=>Bin, D=>D_FS, Bo=>C(1));
Bo_FS <= C(0) or C(1);
end cau_truc;
/Adder4/ /SUB4/library IEEE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; entity SUB4 is
use IEEE.STD_LOGIC_UNSIGNED.ALL; Port (
library work; A : in STD_LOGIC_VECTOR(3 downto
use [Link]; 0);
entity adder4 is B : in STD_LOGIC_VECTOR(3 downto
port(A : in std_logic_vector(3 downto 0); 0);
B : in std_logic_vector(3 downto 0); Bin : in STD_LOGIC;
CI : in std_logic; D : out STD_LOGIC_VECTOR(3
SUM : out std_logic_vector(3 downto 0); downto 0);
CO : out std_logic); Bout : out STD_LOGIC
end adder4; );
architecture Cau_truc of adder4 is end SUB4;
signal C: std_logic_vector(2 downto 0);
component fulladder architecture Cau_truc of SUB4 is
port (A : in std_logic; component FS
B: in std_logic; Port (
Cin : in std_logic; A : in STD_LOGIC;
S: out std_logic; B : in STD_LOGIC;
Cout : out std_logic Bin : in STD_LOGIC;
); D : out STD_LOGIC;
end component; Bout : out STD_LOGIC
for u0: fulladder use entity );
[Link](LUONG_DATA); end component;
for u1: fulladder use entity signal b0, b1, b2, b3 : STD_LOGIC;
[Link](LUONG_DATA); begin
for u2: fulladder use entity U0 : FS port map (A(0), B(0), Bin, D(0),
[Link](LUONG_DATA); b0);
for u3: fulladder use entity U1 : FS port map (A(1), B(1), b0, D(1),
[Link](LUONG_DATA); b1);
begin U2 : FS port map (A(2), B(2), b1, D(2),
u0: fulladder port b2);
map(A=>A(0),B=>B(0),Cin=>CI,S=>Sum(0),Cout=>C(0)); U3 : FS port map (A(3), B(3), b2, D(3),
u1: fulladder port b3);
map(A=>A(1),B=>B(1),Cin=>C(0),S=>Sum(1),Cout=>C(1));
u2: fulladder port Bout <= b3;
map(A=>A(2),B=>B(2),Cin=>C(1),S=>Sum(2),Cout=>C(2)); end Cau_truc;
u3: fulladder port
map(A=>A(3),B=>B(3),Cin=>C(2),S=>Sum(3),Cout=>CO);
end Cau_truc;
/MUX/library ieee; -- JK_FF.vhd
use ieee.std_logic_1164.all; library ieee;
use ieee.std_logic_arith.all; use ieee.std_logic_1164.all;
entity MUX is
port(I0,I1,I2,I3: in std_logic; entity JK_FF is
sel: in std_logic_vector(1 downto port (
0); clk : in std_logic;
Z: out std_logic ); J : in std_logic;
end MUX; K : in std_logic;
architecture sel of MUX is Q : out std_logic;
begin Qn : out std_logic
MUX: process (I0,I1,I2,I3,sel) );
begin end entity;
case sel is
when "00" => Z <= I0; architecture rtl of JK_FF is
when "01" => Z <= I1; signal q_int : std_logic := '0';
when "10" => Z <= I2; begin
when others => Z <= I3; process(clk)
end case; begin
end process MUX; if rising_edge(clk) then
end sel; -- Công thức JK → D
-- D = J·Q' + K'·Q
q_int <= (J and (not q_int)) or ((not K)
and q_int);
end if;
end process;

Q <= q_int;
Qn <= not q_int;
end architecture;
Ha
/mux8/library ieee; /dmux8/library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
entity MUX8 is entity DMUX8 is
port( port(
I0, I1, I2, I3, I4, I5, I6, I7 : in std_logic; D : in std_logic;
sel : in std_logic_vector(2 downto 0); sel : in std_logic_vector(2 downto 0);
E : in std_logic; E : in std_logic;
Z : out std_logic Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 : out std_logic
); );
end MUX8; end DMUX8;
architecture behavioral of MUX8 is architecture behavioral of DMUX8 is
begin begin
MUX8_PROC : DMUX8_PROC : process(D,sel,E)
process(I0,I1,I2,I3,I4,I5,I6,I7,sel,E) begin
begin -- mặc định tất cả ngõ ra = 0
if E = '1' then Y0 <= '0'; Y1 <= '0'; Y2 <= '0'; Y3 <= '0';
case sel is Y4 <= '0'; Y5 <= '0'; Y6 <= '0'; Y7 <= '0';
when "000" => Z <= I0; if E = '1' then
when "001" => Z <= I1; case sel is
when "010" => Z <= I2; when "000" => Y0 <= D;
when "011" => Z <= I3; when "001" => Y1 <= D;
when "100" => Z <= I4; when "010" => Y2 <= D;
when "101" => Z <= I5; when "011" => Y3 <= D;
when "110" => Z <= I6; when "100" => Y4 <= D;
when others => Z <= I7; when "101" => Y5 <= D;
end case; when "110" => Y6 <= D;
else when others => Y7 <= D;
Z <= '0'; end case;
end if; end if;
end process MUX8_PROC; end process DMUX8_PROC;
end behavioral; end behavioral;
library ieee;cau20dff library ieee; bcddemtieen
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
entity SHIFT_REG is use ieee.numeric_std.all;
port( entity BCD_COUNTER is
Din : in std_logic; port(
clk : in std_logic; clk : in std_logic;
rst : in std_logic; rst : in std_logic;
Q : out std_logic_vector(3 downto 0) Q : out std_logic_vector(3 downto 0)
); );
end SHIFT_REG; end BCD_COUNTER;
architecture behavioral of SHIFT_REG is architecture behavioral of BCD_COUNTER is
begin signal count : unsigned(3 downto 0);
SHIFT_PROC : process(clk) begin
begin BCD_PROC : process(clk)
if rising_edge(clk) then begin
if rst = '1' then if rising_edge(clk) then
Q <= "0000"; if rst = '1' then
else count <= "0000";
Q(3) <= Din; elsif count = "1001" then
Q(2) <= Q(3); count <= "0000";
Q(1) <= Q(2); else
Q(0) <= Q(1); count <= count + 1;
end if; end if;
end if; end if;
end process SHIFT_PROC; end process BCD_PROC;
end behavioral; Q <= std_logic_vector(count); end behavioral;

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