MODULE V

2 marks:
​
1. Define the basic concepts pipelining?
Performance of a computer can be increased by increasing the performance of the CPU. This can be
done by executing more than one task at a time. This procedure is referred to as pipelining. The concept
of pipelining is to allow the processing of a new task even though the processing of previous task has not
ended.
​
2. What is pipelining hazard?
In pipelining, there are situations where the next instruction cannot execute in the following clock cycle.
Such situations are called pipelining hazards. These hazards occur due to resource conflicts, data
dependencies, or changes in control flow, and they are broadly classified into three types: structural
hazards, data hazards, and control hazards.
​
3. Summarize the Challenges of Instruction level parallelism (ILP)?
Instruction-level parallelism (ILP) improves performance by overlapping instruction execution, but it faces
several challenges. Data and control dependencies limit how many instructions can run in parallel.
Structural and pipeline hazards, along with scheduling complexity, further limit the achievable parallelism.
​
4. Infer Throughput and Speedup.
Throughput: Is the amount of processing that can be accomplished during a given interval of time. The
amount of hardware increases with parallel processing and with it, the cost of the system increases.
Speedup of a pipeline processing: Pipeline processing speedup is the ratio of pipeline to nonpipeline
processing time. The ideal speedup, or maximum speedup is equal to the number of pipeline stages.
That is, when n is very large, a pipelined processor can produce output approximately m times faster than
a nonpipelined processor. When n is small, the speedup decreases.

​
5. Illustrate DMA.
Direct Memory Access (DMA) is a mechanism that allows data to be transferred directly between I/O
devices and main memory without continuous involvement of the processor. DMA transfers are much
faster than processor-based transfers for two main reasons: (1) the transfer is handled entirely by
hardware, so no time is spent fetching and decoding instructions, and (2) data moves directly between
memory and the I/O device without passing through the processor. The DMA controller is capable of
temporarily taking control of the system buses from the processor to perform the transfer efficiently.
​
6. Interpret USB.
The Universal Serial Bus (USB) is one of the most widely used interconnection standards. Various
devices such as mice, flash drives, disk drives, printers, and cameras use USB connectors. Its
commercial success comes from its simplicity and low cost. The original USB specification supported two
speeds: low-speed (1.5 Mb/s) and full-speed (12 Mb/s).

​
​
7. Interpret SCSI. ​
SCSI (Small Computer System Interface) is a standard bus defined by the American National Standards
Institute (ANSI). It is used to connect a wide range of devices to a computer and is particularly well-suited
for disk drives. SCSI is commonly used in environments such as institutional databases and email
systems where multiple high-performance disk drives are required.
​
8. Describe I/O device Interface.
An input-output interface provides the mechanism for transferring data between the computer’s internal
storage and external I/O devices. Since peripherals operate differently from the CPU in terms of speed,
data format, and control signals, special interface circuits are required. The I/O interface resolves these
differences and enables smooth communication between the CPU and each peripheral device.
​
9. Describe interrupts and exceptions.
Interrupt: An interrupt is a signal that temporarily halts the normal execution of a program to allow the
CPU to respond to an external hardware event. Hardware interrupts originate from devices such as
timers, keyboards, disks, I/O ports, and expansion cards. Since these events occur independently of the
currently running program, the CPU stops its current task, services the interrupt, and then resumes
execution.
Exception: Exception is a software interrupt, which can be identified as a special handler routine. An
exception occurs due to an “exceptional” condition that occurs during program execution.
​
10. Describe I/O transfers.
I/O transfers involve moving data between external devices and the computer’s memory. Input data from
devices is stored in memory for later processing, while output data is taken from memory and sent to
devices. The CPU only executes I/O instructions, but the actual source or destination of data is always
the memory unit. I/O transfers may use the CPU as an intermediate path or transfer data directly to and
from memory, depending on the mode used.

16 Marks

Q1. i) Define parallelism and its types.

Definition of Parallelism

Parallelism refers to the ability of a computer system to perform multiple operations

simultaneously. Instead of executing instructions one after another, parallelism divides tasks
into smaller units that can be executed at the same time, thereby improving performance,
throughput, and efficiency. It is used in both hardware and software to speed up computation,
handle large data, and optimize resource usage.

Parallelism can be implemented at different levels in a computer system, ranging from

instruction execution inside the CPU to execution of multiple programs across processors.

Types of Parallelism

Parallelism is generally classified into the following types:

1. Bit-Level Parallelism

●​ Increases parallelism by processing multiple bits of data at once.

●​ Achieved by using wider ALUs (e.g., 8-bit, 16-bit, 32-bit, 64-bit processors).
●​ Improves speed by reducing the number of instructions needed for operations on large
data.

2. Instruction-Level Parallelism (ILP)

●​ Allows multiple instructions to execute simultaneously.

●​ Uses techniques such as:
○​ Pipelining
○​ Superscalar execution
○​ Out-of-order execution
○​ Branch prediction
●​ The goal is to overlap instruction execution to reduce execution time.

3. Data-Level Parallelism (DLP)

●​ Achieved when the same operation is applied to multiple data elements at once.
●​ Common in scientific computing, AI, and multimedia applications.
●​ Implemented using:
○​ Vector processors
○​ SIMD (Single Instruction, Multiple Data)
○​ GPUs

4. Task-Level Parallelism (TLP)

●​ Focuses on executing different tasks or threads in parallel.

●​ Each task performs a separate function.
●​ Enabled using:
○​ Multithreading
○​ Multicore processors
○​ Distributed computing

5. Process-Level Parallelism

●​ Entire processes run simultaneously.

●​ Each process may contain multiple instructions or tasks.
●​ Used in operating systems that support multitasking and multiprocessing.

6. Parallelism Based on Flynn’s Taxonomy

Flynn classified parallel computers into four types:

a) SISD (Single Instruction, Single Data)

Traditional sequential execution (no parallelism).

b) SIMD (Single Instruction, Multiple Data)

One instruction operates on many data elements (vector processors, GPUs).

c) MISD (Multiple Instruction, Single Data)

Rare, theoretical model.

d) MIMD (Multiple Instruction, Multiple Data)

Multiple processors execute different instructions on different data.​

Used in multicore CPUs and distributed systems.

ii) List the main characteristics of Instruction level parallelism.

Main Characteristics of Instruction Level Parallelism (ILP)

1. Concurrent Execution of Multiple Instructions

ILP allows more than one instruction to be executed at the same time. By overlapping
instruction execution, the CPU improves throughput and reduces the time needed to complete a
sequence of instructions.

2. Pipelined Instruction Processing

ILP relies heavily on pipelining, where the instruction cycle is divided into stages such as fetch,
decode, execute, memory access, and write-back. While one instruction is decoded, another is
fetched, and another is executed. This stage-wise overlap increases parallelism inside the CPU.

3. Exploitation of Independent Instructions

ILP works by identifying instructions that have no data dependencies or control dependencies.
Independent instructions can execute in parallel without waiting for results of previous
instructions, enabling better overlap and utilization of CPU resources.

4. Multiple Functional Units in the CPU

Modern processors contain several arithmetic units, floating-point units, load/store units, and
branch units. ILP utilizes these multiple execution units so that different instructions can be
processed simultaneously without structural hazards.

5. Superscalar Architecture Support

In ILP systems, the processor can fetch, decode, and issue multiple instructions per clock
cycle. Superscalar CPUs contain parallel pipelines and can dispatch several instructions to
different execution units at the same time.
6. Out-of-Order Execution

ILP uses dynamic scheduling techniques, allowing the processor to execute instructions out of
the original program order. As soon as operands for an instruction are ready, it can execute,
avoiding delays caused by earlier stalled instructions.

7. Use of Speculation and Branch Prediction

To increase instruction overlap, ILP processors use sophisticated branch predictors. They guess
the outcome of branch instructions and fetch subsequent instructions speculatively. This
minimizes pipeline stalls and improves parallel execution in the presence of control hazards.

8. Compiler and Hardware Cooperation

ILP is enhanced by both compiler techniques and hardware mechanisms. Compilers unroll
loops, schedule instructions, remove dependencies, and optimize code to expose more
parallelism. Hardware further supports ILP through hazard detection, register renaming,
forwarding, and speculation.

Conclusion

Instruction-level parallelism increases CPU performance by exploiting parallel execution within a

single instruction stream. Through pipelining, multiple execution units, speculation, and
advanced scheduling techniques, ILP maximizes hardware utilization and reduces execution
time.

Q2. Write a short notes on Peripheral devices .With a neat sketch explain the working principle of
DMA ​

Peripheral Devices ​
Peripheral devices are external hardware components connected to a computer to perform input, output,
or storage functions. They do not form part of the core computer architecture (CPU and main memory)
but allow the system to communicate with the outside world. Since peripherals operate differently from
the CPU, special interfacing techniques are required to handle communication, data format conversion,
and control operations.

[Link] of Peripheral Devices

[Link] Devices

Used to send data or control signals to the computer.​

Examples: Keyboard, mouse, scanner, microphone, camera.

ii. Output Devices

Used to present data from the computer to the user.​

Examples: Monitor, printer, speakers, projector.
iii. Storage Devices

Used for data storage and retrieval.​

Examples: Hard disk, SSD, CD/DVD, USB flash drive, external drives.

2. Characteristics of Peripheral Devices

Peripheral devices differ from the CPU in several important ways:

a. Electromechanical Nature

Peripherals such as keyboards, printers, and disks are electromechanical, whereas CPU and
memory are purely electronic.​
Therefore, signal conversion is required to match electrical level, timing, and encoding.

b. Speed Mismatch

Peripherals are much slower than the CPU.​

A synchronization mechanism (handshaking, buffering, interrupts, DMA, etc.) is required to
allow proper data transfer.

c. Different Data Formats and Codes

Peripheral data formats (ASCII characters, bit streams, sensor signals, etc.) differ from the
processor word format.​
Thus, data translation is necessary.

d. Device-Specific Operating Modes

Every peripheral (keyboard, disk, printer) has its own operational characteristics.​
Separate controllers and interface units are needed to ensure the operation of one device
does not affect others.

3. I/O Device Interface

To overcome the differences between CPU and peripherals, I/O interface units are used.
These interface units:

●​ Connect peripheral controllers to the system bus

●​ Decode addresses
●​ Interpret I/O commands
●​ Provide status signals
●​ Synchronize data transfer
●​ Ensure correct handshaking between CPU and device

A typical I/O interface handles four types of commands:

1.​ Control – activate the device

2.​ Status – check device readiness
 3.​ Data Output – send data from CPU to device
4.​ Data Input – transfer data from device to CPU

4. I/O Bus and Interface Modules

The CPU communicates with several peripherals using a common I/O bus that consists of:

●​ Data lines
●​ Address lines
●​ Control lines

Each peripheral is connected via an interface module that contains:

●​ Address decoder
●​ Data buffer register
●​ Status and control register
●​ Signals to the device controller

The processor selects a device by placing its address on the bus, and only the interface with the
matching address responds.

5. Methods of Communication Between CPU and I/O

Computers use three approaches to connect memory and I/O to the CPU:

1.​ Separate memory and I/O buses

2.​ Common bus with separate control lines
3.​ Common bus with shared control lines

6. Isolated I/O

●​ Memory and I/O use different address spaces

●​ Separate instructions like IN, OUT are required
●​ I/O Read / I/O Write control lines specify that the address belongs to an I/O device

This approach is commonly used in microprocessors (like 8085, 8086).

7. Memory-Mapped I/O

●​ I/O devices share the same address space as memory

●​ No separate I/O instructions
●​ CPU uses load/store instructions to communicate with peripherals
●​ Easier to program and integrate
●​ More flexible addressing

This is commonly used in RISC systems and modern architectures.

Conclusion
 Peripheral devices play a vital role in expanding a computer’s functionality. Because they differ
from CPU and memory in speed, data format, and operation, specialized I/O interfaces, device
controllers, and communication techniques are required. Concepts like isolated I/O and
memory-mapped I/O govern how peripherals are accessed within a computer system.

Working Principle of DMA

Direct Memory Access (DMA) is a technique where data is transferred directly between an I/O
device and main memory without continuous involvement of the CPU. This increases
system performance because the CPU is freed from slow byte-by-byte transfer operations.

1. Need for DMA

In programmed or interrupt-driven I/O, the CPU handles every data transfer.​

This wastes CPU time because:

1.​ I/O devices (disk, ADC, NIC) are much slower than the CPU.
2.​ CPU must execute instructions for every transfer.

DMA overcomes this by using a DMA Controller (DMAC) such as 8237/8257, which performs
the data transfer autonomously.

2. Components of DMA Controller

A typical DMA controller contains:

●​ Address Register (CAR) – holds starting memory address

●​ Count Register (CWCR) – number of bytes/words to transfer
●​ Control Register – specifies read/write direction
●​ Data Buffer – temporary holding of data
●​ Control Logic – manages signals like DREQ, DACK, HOLD, HLDA

3. Working Principle of DMA (Step-by-Step)

Step 1: CPU Initializes DMA (DMA Setup)

The CPU programs the DMA controller by loading:

●​ Starting memory address

●​ Word/byte count
●​ Transfer direction:
○​ Memory → I/O
○​ I/O → Memory

After initialization, the CPU continues its own tasks.

Step 2: DMA Requests Bus Control

 When the I/O device is ready, it sends a DMA Request (DREQ) signal to the DMAC.​
The DMA controller then sends HOLD to the CPU.

The CPU:

●​ Completes its current bus cycle

●​ Acknowledges with HLDA (Hold Acknowledge)

Now, DMA becomes the bus master.

Step 3: DMA Performs Data Transfer

With bus control, DMA transfers data directly:

●​ Places memory address on address bus

●​ Activates Memory Read/Write and I/O Read/Write signals
●​ Moves data between memory and the I/O device
●​ Increments address register
●​ Decrements count register

One byte/word is transferred per cycle.

CPU remains idle during this process (enters HOLD state).

Step 4: DMA Completes Transfer

When the count register reaches Terminal Count (0):

●​ DMA stops the transfer

●​ Releases the bus (HOLD = 0)
●​ CPU regains bus and resumes full operation
●​ DMA sends an interrupt to indicate transfer completion

4. DMA Transfer Modes

●​ Burst Mode: DMA transfers an entire block at once (CPU halted)

●​ Cycle Stealing: DMA transfers one word per cycle by “stealing” CPU cycles
●​ Transparent Mode: DMA transfers occur only when CPU is idle

5. Advantages of DMA

●​ Very high-speed data transfer

●​ CPU is free for computation
●​ Reduced overhead and better system performance
●​ Best for large block transfers (disk, graphics, audio/video)

6. Drawback of DMA

●​ DMA becomes bus master, so CPU cannot use the bus during DMA cycles
 ●​ CPU stays in HOLD state temporarily

Q3. Discuss with neat diagrams, How Hazards improved in Pipelining. ​

​
How Hazards Are Improved in Pipelining

Pipelining improves the overall performance of a processor by executing multiple instructions

concurrently. However, hazards reduce the efficiency of pipelines by causing stalls or incorrect
execution. Modern processors use various techniques to detect, reduce, and eliminate hazards.
Hazards in pipelining are mainly of three types: Structural Hazards, Data Hazards, and
Control Hazards. The improvements made to handle these hazards are explained below.

1. Structural Hazards and Their Improvements

Structural hazards occur when hardware resources are insufficient to execute multiple pipeline
stages simultaneously. To improve this, the following techniques are used:

(a) Hardware Duplication

●​ Separate instruction memory and data memory (Harvard architecture).

●​ Separate ALU units for integer and floating-point operations.​
This avoids resource conflicts and allows all stages to execute smoothly.

(b) Pipelined Functional Units

●​ ALU, multiplier, or floating-point units are made pipelined.

 ●​ Every stage of these units works in parallel, reducing delays.

(c) Multi-port Register File

●​ Multiple read and write ports allow simultaneous operand access.

●​ Prevents conflicts during register fetch and write-back stages.

These improvements remove structural bottlenecks and ensure smooth data flow.

2. Data Hazards and Their Improvements

Data hazards arise when instructions depend on results of previous instructions. Three types
exist: RAW (Read After Write), WAR (Write After Read), and WAW (Write After Write).​
Modern pipelines use the following methods to eliminate or reduce data hazards:

(a) Forwarding (Data Bypassing)

●​ The most common and powerful technique.

●​ The output of ALU is passed directly to the next instruction’s input without waiting for
the value to be written into registers.
●​ Eliminates most RAW hazards and reduces stalls drastically.

(b) Hazard Detection Unit

●​ A dedicated hardware unit that detects hazards at decode stage.

●​ If forwarding is not possible (e.g., load-use hazard), the unit inserts a bubble (stall)
automatically.

(c) Compiler-Based Scheduling (Instruction Reordering)

●​ Compilers rearrange instructions to avoid dependent instructions being placed

immediately next to each other.
●​ Eliminates many hazards even before the program runs.

(d) Register Renaming

●​ Removes WAR and WAW hazards.

●​ Hardware allocates physical registers dynamically to avoid name conflicts.
●​ Used in modern CPUs with out-of-order execution.

(e) Scoreboarding

●​ A centralized control technique used in CDC 6600.

●​ Keeps track of instruction dependencies and ensures safe execution order.

3. Control Hazards and Their Improvements

 Control hazards occur due to branch instructions which change the flow of execution. They can
cause pipeline flushing. The following techniques significantly reduce control hazards:

(a) Branch Prediction

●​ Predicts whether a branch will be taken or not taken.

●​ Modern CPUs use:
○​ Static prediction (simple and fast)
○​ Dynamic prediction (more accurate)​
▪ 1-bit and 2-bit predictors​
▪ Branch History Table​
▪ Global history predictors​
▪ Tournament (hybrid) predictors​
High prediction accuracy greatly reduces flushing.

(b) Delayed Branching

●​ Compiler fills the branch delay slot with a useful instruction.

●​ Even if branch is taken, no cycle is wasted.

(c) Branch Target Buffer (BTB)

●​ A small cache that stores previous branch addresses and targets.

●​ Eliminates the delay of calculating branch addresses.

(d) Loop Buffer

●​ A small fast memory storing the body of loops.

●​ Avoids fetching from instruction cache again and again.

(e) Speculative Execution

●​ Processor guesses the direction and executes instructions ahead.

●​ If the guess is correct, time is saved.
●​ If incorrect, results are discarded (rollback), but the overall speed improves.

(f) Early Branch Resolution

●​ Branch decision is moved from later stages to ID or EX stage.

●​ Reduces the number of cycles wasted due to branch uncertainty.

4. Overall Improvements in Pipeline Performance

Through the above techniques, the following benefits are achieved:

●​ Reduction in pipeline stalls and bubbles

●​ Increased Instruction Throughput
●​ Higher Instruction-Level Parallelism (ILP)
●​ More efficient utilization of hardware resources
 ●​ Ability to execute dependent and branch-heavy code effectively

Modern CPUs achieve near-ideal pipeline performance due to continuous improvements in

hazard handling.

Conclusion

Hazards are unavoidable in pipelined processors, but they can be significantly reduced using
architectural and compiler-level techniques. Techniques such as hardware duplication,
forwarding, hazard detection units, register renaming, branch prediction, BTB, delayed
branching, and speculative execution ensure that pipeline performance is improved and
stalls are minimized. These improvements allow pipelined processors to execute instructions
faster, efficiently, and reliably.

Q4. Describe in detail about input-output-processor (IOP) organization. ​

Input–Output Processor (IOP) Organization ​

An Input–Output Processor (IOP) is a specially designed, intelligent processor used to control and
manage input–output operations independently of the Central Processing Unit (CPU). The main purpose
of an IOP is to take over complex I/O tasks so that the CPU can focus on computation, thereby
increasing overall system performance. IOPs act as an intermediary between I/O devices and the main
memory, reducing CPU involvement in data transfer.
1. Introduction to IOP

An Input–Output Processor is a programmable processor dedicated to handling I/O tasks

such as:

●​ Device control
●​ Data formatting
●​ Error detection
●​ Direct data transfer between I/O and memory

The IOP executes its own set of I/O instructions and operates parallel to the CPU.​
While the CPU executes computational instructions, the IOP handles I/O operations, thus
achieving overlap of processing and I/O.

2. Need for IOP

I/O devices are inherently slower than the CPU. If the CPU manages them directly, it wastes
most of its time waiting.​
To prevent this:

• CPU delegates

●​ Data transfer
●​ Device control
●​ Buffering
●​ Interrupt handling

• IOP operates autonomously

This leads to:

●​ Higher system throughput

●​ Reduced CPU idle time
●​ Efficient handling of multiple devices simultaneously
3. IOP Organization (Block Diagram Explanation)

The IOP organization typically includes the following components:

(a) IOP Control Unit

●​ Acts like a CPU control unit but specialized for I/O tasks.
●​ Fetches, decodes, and executes I/O instructions.
●​ Controls data flow between memory and peripheral devices.

(b) IOP Local Memory

●​ Stores I/O programs (I/O command list).

●​ Stores device-specific routines and status information.
●​ Acts as buffer space during data transfer.

(c) Communication Registers

1.​ Command Register – CPU writes I/O commands for IOP.

2.​ Status Register – IOP writes status/info for CPU.
3.​ Data Register – Used for passing parameters or small data.

These registers form the CPU–IOP communication interface.

(d) I/O Channels

IOPs use channels to connect to multiple devices. Types include:

●​ Multiplexer Channel – Connects many slow devices simultaneously.

●​ Selector Channel – Connects one high-speed device at a time.
●​ Block Multiplexer Channel – Supports interleaving of multiple block transfers.

Channels are responsible for:

●​ Device selection
●​ Addressing
●​ Synchronization
●​ Data stream control

(e) DMA Logic (Direct Memory Access)

Many IOPs also contain DMA hardware.

●​ Transfers data directly between I/O and main memory.

●​ Frees CPU from handling each transfer.
●​ Supports burst or cycle-steal mode.

The IOP supervises multiple DMA operations concurrently.

(f) Device Controllers

Each I/O device (disk, keyboard, printer, etc.) is attached through its own device controller.​
IOP sends:

●​ Commands
●​ Data
●​ Control signals

to these controllers.

4. Working of an Input–Output Processor

Step 1: CPU Initializes the IOP

●​ CPU loads a Command List or Control Block into memory.

●​ CPU sends a start I/O instruction to the IOP through a command register.

Step 2: IOP Fetches the Control Block

●​ IOP reads the I/O program from memory.

●​ It interprets I/O commands (read, write, move, test status, etc.).

Step 3: IOP Interacts with I/O Devices

●​ Selects device through device controller.

●​ Performs handshaking with the device.
●​ Sets up DMA transfer if required.

Step 4: Data Transfer

IOP transfers data:

●​ Between memory ↔ device

●​ Without CPU involvement
●​ Using DMA or channel programs

Step 5: IOP Updates Status

●​ After completing the operation, the IOP updates the status register.
●​ Generates an interrupt to notify CPU only at the end of the entire I/O task.

Thus, CPU is free during the whole process.

5. Advantages of Using an IOP

(a) Parallelism
 CPU and IOP work simultaneously, increasing throughput.

(b) Reduced CPU Load

CPU is not involved in data transfer or device control.

(c) Faster I/O Handling

IOP executes specialized I/O instructions and uses DMA.

(d) Better Device Management

Can control multiple devices efficiently through channels.

(e) High System Performance

Total execution time decreases; bottlenecks are minimized.

6. Comparison Between CPU and IOP

Feature CPU IOP

Purpose Computation Input/Output Control

Instruction Set Arithmetic/logic Device control, I/O commands

Speed Very high Moderate

Priority Higher Lower

Communication Only via registers via devices, controllers, DMA

7. Applications of IOP

IOPs are widely used in:

●​ Mainframe systems
●​ High-speed data acquisition
●​ Real-time control systems
●​ Database servers
●​ Network communication systems

8. Conclusion
 The Input–Output Processor (IOP) organization provides an efficient mechanism for handling
complex I/O operations independently of the CPU. By using local memory, control units,
channels, device controllers, and DMA logic, the IOP performs all I/O tasks autonomously. This
parallel operation between CPU and IOP reduces CPU workload, increases system throughput,
and allows simultaneous control of multiple devices. Hence, IOP plays an essential role in
modern computer architectures requiring efficient and high-speed I/O management.

Q5. Discuss briefly the protocols of universal serial bus. ​

The Universal Serial Bus (USB) is the most widely used I/O interface for connecting peripherals such as
keyboards, mice, cameras, storage devices, and multimedia equipment. The functioning of USB is
governed by a well-defined set of protocols that control how devices are detected, addressed,
transferred, synchronized, and powered. These protocols ensure high reliability, flexibility, and
“plug-and-play” operation.

1. USB Communication Model

USB communication is host-controlled.

●​ Only the host (computer) initiates all communication.

●​ The devices never communicate directly with each other.
●​ USB follows a master–slave model using systematic polling.

This host-controlled model is the foundation of all USB protocols.

2. Device Enumeration Protocol

When a USB device is connected or powered on, the system automatically detects it.​
Steps in the enumeration protocol:

1.​ Device starts with the default address 0.

2.​ Host sends Reset signal through the hub.
3.​ Host issues Get Descriptor to read device information.
4.​ Device reports:
○​ Device class
○​ Vendor ID, Product ID
○​ Endpoint structures
5.​ Host assigns a unique 7-bit USB address.
6.​ Appropriate device driver is selected and loaded.

Purpose:

●​ Enables plug-and-play operation

●​ Allows automatic configuration without user involvement

3. Polling Protocol
 USB strictly follows a polling-based communication protocol.

●​ Devices cannot send data whenever they want.

●​ The host continuously polls devices in a fixed schedule.
●​ Device responds only when the host gives permission.

Advantages:

●​ No collisions occur
●​ Hubs remain simple and low-cost
●​ Bandwidth allocation is predictable

4. USB Transfer Protocols (Transaction Types)

USB supports four types of data-transfer protocols, each designed for specific device
requirements.

(a) Control Transfer Protocol

●​ Used for device configuration, commands, and status.

●​ Essential during enumeration.
●​ Guaranteed delivery using error checking and retries.

(b) Bulk Transfer Protocol

●​ For large, non-time-critical data.

●​ Example: printers, scanners, mass storage devices
●​ Uses available bus bandwidth and ensures error-free transmission.

(c) Isochronous Transfer Protocol

●​ Used for real-time multimedia applications (audio/video).

●​ Data is delivered at regular, periodic intervals.
●​ No retries → timing is more important than accuracy.

(d) Interrupt Transfer Protocol

●​ Used for small, fast, time-sensitive data.

●​ Example: keyboard, mouse, medical sensors
●​ Guarantees a minimum polling interval.

These four protocols allow USB to support a wide range of I/O devices efficiently.

5. Packet Protocol (USB Packet Structure)

USB communication is packet-based, meaning data is sent in structured packets.​

The main packet types are:
(a) Token Packets

●​ Indicate the type and direction of the transfer.​

(IN, OUT, SETUP)

(b) Data Packets

●​ Carry the actual data payload.​

(DATA0, DATA1, DATA2)

(c) Handshake Packets

●​ Acknowledge the success or failure of transactions.​

(ACK, NAK, STALL)

(d) Special Packets

●​ Used for synchronizing frames.​

(Start-of-Frame – SOF)

Each packet contains:

●​ Sync field
●​ PID (Packet Identifier)
●​ Device address
●​ Endpoint number
●​ CRC for error detection

This protocol ensures reliable high-speed data communication.

6. Start-of-Frame (SOF) Protocol

The host sends a Start-of-Frame (SOF) packet every 1 millisecond.​

Functions:

●​ Synchronizes all devices in the USB tree

●​ Provides timing reference for isochronous transfers
●​ Divides the USB bus into frames for scheduling

In USB 2.0, micro-frames of 125 microseconds are used for higher precision.

7. Signalling Protocol

USB uses two electrical signalling methods:

(a) Single-Ended Signalling

●​ Used in low-speed (1.5 Mbps) and full-speed (12 Mbps) devices

●​ Voltage referenced to ground
 ●​ More sensitive to noise

(b) Differential Signalling

●​ Used for high-speed (480 Mbps) and SuperSpeed devices

●​ Data transmitted over twisted pair
●​ Noise is cancelled because both lines carry equal and opposite signals
●​ Allows very high data rates

This protocol enhances signal integrity and supports long cable lengths.

8. Hub Communication Protocol

USB supports a tree topology using hubs.

Hub protocol performs:

●​ Port management
●​ Device detect/disconnect
●​ Over-current protection
●​ Signal regeneration and forwarding
●​ Power distribution (5V)

Hubs forward packets to the correct device based on USB addresses.

9. Power Management Protocol

USB supports dynamic power allocation:

●​ Bus-powered devices draw power directly from USB (5V)

●​ Self-powered devices use their own supply
●​ Host can suspend or resume devices based on activity​
This improves energy efficiency.

10. Error Detection and Handling Protocol

USB uses:

●​ CRC (Cyclic Redundancy Check)

●​ Handshake packets (ACK/NAK/STALL)
●​ Retry mechanisms (only for control and bulk transfers)

This ensures reliable communication despite electrical noise.

Conclusion
 The Universal Serial Bus uses a rich set of protocols—enumeration, polling, transfer types,
packet structure, signalling, frame synchronization, and power control—to deliver a flexible,
high-speed, and user-friendly interface. These protocols together make USB one of the most
successful I/O standards in modern computer systems.

Q6. Do the complete study on Interrupts and exceptions.​

​
1. Introduction​
Interrupts and exceptions are mechanisms that temporarily stop the normal execution of a program so
that the processor can respond to an important event. Although both cause a deviation from the normal
flow of execution, interrupts originate from external hardware, while exceptions originate from
internal processor conditions.

2. Interrupts

2.1 Definition

An interrupt is a hardware-generated signal that informs the CPU that an external device
needs attention. It causes the CPU to pause the current program, service the request, and
resume execution.

2.2 Sources of Interrupts

●​ Keyboard, mouse, I/O ports

●​ Timer chip
●​ Disk controllers
●​ Network interface
●​ CMOS clock
●​ Expansion cards (sound, video, etc.)

Interrupts occur independently of the currently executing program.

2.3 Working Mechanism of an Interrupt

1.​ External device raises an interrupt signal.

2.​ CPU finishes current instruction.
3.​ CPU saves program context (registers, PC, flags).
4.​ Interrupt vector is used to locate ISR (Interrupt Service Routine).
5.​ CPU executes ISR to service the external device.
6.​ CPU restores saved context.
7.​ CPU resumes the interrupted program.

During ISR execution, most systems disable further interrupts unless explicitly re-enabled.

3. Exceptions
3.1 Definition

An exception is a software or processor-generated event that arises due to abnormal

conditions that occur during instruction execution.

3.2 Causes of Exceptions

●​ Divide-by-zero
●​ Illegal opcodes
●​ Page faults
●​ Memory protection violations
●​ Arithmetic overflow
●​ System call instructions

Exceptions always occur because of an instruction in the running program.

3.3 Exception Handling Process

1.​ CPU detects the exceptional condition.

2.​ CPU automatically enters kernel mode.
3.​ Saves program context.
4.​ Identifies the type of exception.
5.​ Executes the exception handler.
6.​ The handler corrects the error or terminates the process with a proper message.
7.​ Context is restored and execution resumes (if possible).

4. CPU Context / State

The CPU context includes:

●​ All general-purpose registers

●​ Program counter (PC)
●​ Stack pointer
●​ Processor status word
●​ Control registers

This context must be saved during any interrupt or exception and restored afterward.

5. Types of Interrupts

5.1 Vectored and Non-Vectored Interrupts

Vectored Interrupts

●​ ISR address is fixed and known by the CPU.

●​ Faster handling.
●​ Cannot be easily expanded.
 Example: NMI of 8086 (vector number 2)

Non-Vectored Interrupts

●​ ISR address is not fixed.

●​ CPU receives the address from interrupting device or controller (e.g., 8259 PIC).
●​ Supports multiple devices.

Example: INTR of 8086 (any vector 0–255)

5.2 Maskable and Non-Maskable Interrupts

Maskable Interrupts (MI)

●​ Can be disabled by the processor (masking).

●​ Used for low-priority events like keyboard input.

Example: INTR of 8086 (disabled when IF = 0)

Non-Maskable Interrupts (NMI)

●​ Cannot be disabled.
●​ Used for critical events such as power failure and hardware faults.

Example: NMI of 8086

5.3 Hardware and Software Interrupts

Hardware Interrupts

Generated by external hardware signals on CPU pins.

Software Interrupts (Exceptions)

Generated by executing a special instruction (e.g., INT n in 8086).

6. Types of Exceptions

Exceptions are classified into three types:

6.1 Faults

●​ Correctable exceptions
●​ After correction, execution resumes at the same instruction​
Example: Page fault

6.2 Traps
 ●​ Reported immediately after instruction execution​
Example: Breakpoint, debugging traps

6.3 Aborts

●​ Serious errors
●​ Execution cannot safely continue​
Example: Machine check, hardware failure

7. Interrupt Vector Table (IVT)

An IVT is a table stored in memory that contains the starting addresses of all ISRs.

●​ Each interrupt/exception has a unique vector number.

●​ The CPU uses the vector number × entry size to locate the ISR entry.
●​ Used in x86, ARM, MIPS, and many other architectures.

8. Priorities and Nested Interrupts

8.1 Interrupt Priorities

●​ Multiple interrupts may occur simultaneously.

●​ Priority levels determine which interrupt is serviced first.
●​ Higher priority interrupts preempt lower ones.

8.2 Nested Interrupts

●​ Occur when a higher priority interrupt interrupts an ISR.

●​ CPU supports nesting through:
○​ Interrupt enable flags
○​ Interrupt controller (8259 PIC or APIC in modern systems)

9. Real-World Uses of Interrupts and Exceptions

9.1 Timer Interrupt

Used by OS for multitasking, context switching, and scheduling.

9.2 Keyboard/Mouse Interrupts

Used for real-time input handling.

9.3 Disk Interrupts

Used for completing read/write operations.

9.4 Page Fault Exception

Used in virtual memory systems for loading required pages into RAM.

9.5 System Calls (Software Interrupts)

Operating systems use instructions like INT 80h (Linux) for communication between user
processes and kernel.

10. Conclusion

Interrupts and exceptions together form the backbone of modern computer operation.

●​ Interrupts allow the CPU to respond to asynchronous hardware events.

●​ Exceptions handle abnormal internal conditions during program execution.
●​ The complete process involves saving the CPU context, identifying the cause, servicing
the request, and resuming execution.​
They are essential for multitasking, virtual memory, device management, reliability, and
overall system stability.