FPGA/CPLD Universal Register & Display
Controller
Hardware Implementation Guide (Kit Model: CI-33004)
Digital Systems Lab
December 22, 2025
1 System Overview
This document provides instructions for operating and troubleshooting the VHDL Uni-
versal Register project. The system accepts an 8-bit input, stores it in a shift register,
and displays the current value in decimal (0-255) on a 3-digit 7-segment display using
Time-Division Multiplexing (TDM).
2 Project Compilation Guide
To successfully compile the project, you must structure the files correctly in your EDA
tool (Xilinx ISE, Vivado, or Quartus).
2.1 File Hierarchy
The design consists of three modular files. Ensure all are added to your project:
1. Level 1 (Top Module): super_reg_top.vhd
This is the wrapper that connects the logic to the physical board pins.
2. Level 2 (Logic Core): super_reg.vhd
Contains the shift register logic (Load, Shift Left, Shift Right).
3. Level 2 (Display Interface): Display_Controller.vhd
Contains the BCD conversion and 7-segment multiplexing logic.
2.2 Implementation Steps
1. Create Project: Initialize a new project targeting the specific CPLD/FPGA chip
on the CI-33004 kit.
2. Add Sources: Import the three VHDL files listed above.
3. Set Top Level: In the design hierarchy view, right-click super_reg_top.vhd and
select "Set as Top Module" (or "Set as Top Level Entity").
4. Synthesize: Run the Synthesis tool. Verify that there are no errors.
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5. Assign Pins: Open the User Constraints/Pin Planner and map the ports (clk,
data_in, seg_out, etc.) to the physical pins (see Section 3).
6. Program: Generate the programming file (.bit or .jed) and load it onto the kit.
3 Integration Verification & Final Checklist
3.1 Code Validation
Status: Ready for Synthesis. The top-level design is structurally correct and properly
integrates the modules:
• Component Declarations: Match entity definitions perfectly.
• Signal Wiring: reg_data_out correctly bridges the register output to the display
input.
• Clocking: The same clk signal drives both modules (critical for synchronous op-
eration).
• Debugging: The led_out and flag_led ports are correctly wired for visual de-
bugging.
3.2 Pre-Synthesis Checklist
Before hitting "Compile," verify these settings in Quartus/ISE:
1. File Organization: Ensure the project contains exactly the three files listed in
Section 2.1.
2. Top-Level Entity: You must specify super_reg_top as the top-level design entity
(not super_reg or Display_Controller).
3. Pin Assignments: Use the following map for your Constraints File (.ucf/.qsf):
# Clock (Use Kit’s 3.5 kHz output)
clk -> PIN_XX
# Inputs
data_in[0..7] -> DIP Switches (SW0-SW7)
data_sh_r -> Toggle Switch
data_sh_l -> Toggle Switch
control[0..2] -> Control Switches
# Outputs
seg_out[0..6] -> 7-Seg Segments (a-g)
dig_sel[0..3] -> Digit Enables (D1-D4)
led_out[0..7] -> Bar LEDs (Debug)
flag_led -> Single LED
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3.3 Functional Test Sequence
Perform this specific test sequence to verify logic before full operation:
1. Setup: Set control = "000" (Parallel Load Mode).
2. Input: Set data_in = "00000101" (Decimal 5).
3. Clock: Pulse the clock once.
4. Expected Result:
• Display shows "005".
• LEDs show binary 00000101.
5. Count Test: Set control = "110" (Count Up) and pulse the clock multiple times.
6. Result: Display should count 005 → 006 → 007 → 008 . . .
3.4 Hardware Specific Alerts
• Clock Source: Ensure you are using the 3.5 kHz fixed frequency, not the
adjustable one. The Display Controller is tuned for ≈ 3.5 kHz.
• Digit Count: The kit has 4 digits, but this controller uses 3 (Hundreds, Tens,
Units). The 4th digit select line (dig_sel(3)) will remain disabled. This is normal
behavior for 8-bit (0-255) values.
• Polarity Check: The controller assumes Common Anode. If your display shows
inverted patterns (dark segments on lit background), remove the not keywords in
the VHDL decoder logic.
4 Hardware Setup & Pin Assignment (Reference)
• Clock Source: Must be connected to the Kit’s 3.5 kHz clock generator.
• Segments (a-g): Connect to the parallel bus driving the segment anodes.
• Digit Select: Connect to the transistor bases enabling individual digits.
5 Operation Manual
Follow this sequence to verify functionality:
1. Power On: Ensure the kit is powered and the clock is active.
2. Reset: Press the assigned Reset button. The display should read 000.
3. Parallel Load:
• Set the 8 data switches to a value (e.g., all ON = 255).
• Press the Load button.
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• Verify the display shows the corresponding decimal number.
4. Shifting:
• Engage Shift Right: The number should halve (integer division).
• Engage Shift Left: The number should double.
6 Troubleshooting Guide
Use the table below to diagnose common visual issues on the 7-segment display.
Symptom Root Cause Solution
Display flickers visibly Scan rate is too slow. The Change digit_ptr to use
eye can detect the switching be- lower bits of scan_timer
tween digits because the clock (e.g., 3 downto 2).
divider is too high.
Ghosting (e.g., 888) Scan rate is too fast. The Change digit_ptr to use
LEDs do not have enough time higher bits (e.g., 6 downto
to turn off before the next digit 5).
turns on.
Inverted Digits Wrong Polarity. The code Remove the not keyword
assumes Common Anode, but in the 7-segment decoder
the board is Common Cathode. process.
Strange Symbols Pin Mapping Error. The Re-check constraints. En-
segments are wired in the sure MSB maps to ’a’ and
wrong order (e.g., ’a’ is con- LSB maps to ’g’.
nected to ’g’).
Table 1: Common Display Issues and Fixes
7 Advanced Configuration: Calculating Scan Rates
To customize the flicker-free refresh rate, use the following formula to select the correct
scan_timer bits:
Clock Frequency
Refresh Rate =
2Bit Position
Example for 3.5 kHz Clock:
• Target Refresh: ≈ 200 Hz (per digit)
• 2Bit Position = 3500/200 = 17.5
• Closest power of 2 is 16 (24 ).
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• Conclusion: Use bits 5 downto 4 (or 4 downto 3 depending on counter size) to
achieve the target rate.