BCSE205L Computer Architecture and Organization

Presented By,
[Link] Kumar
ASP / SENSE
VIT University – Chennai Campus
 [Link]
organization-and-architecture/

Overview of Organization and

Architecture
 MODULES

1 MODULE Introduction To Computer Architecture and

Organization.

2 MODULE Data Representation and Computer Arithmetic

3 MODULE Instruction Sets and Control Unit

4 MODULE Memory System Organization and Architecture.

3
 MODULES

5 MODULE Interfacing and Communication.

6 MODULE Subsystems

7 MODULE High Performance Processors

4
 Reference Books:
[Link] A. Patterson, John L. Hennessy, Computer Organization and
Design-The hardware/software interface, 2013, 5th edition, Morgan
Kaufmann Publishers, USA.

2. Carl Hamacher, ZvonkoVranesic, Safwat Zaky and Naraig Manjikian,

Computer Organization and Embedded Systems, 2012, 6th edition
McGraw Hill, USA.

3. William Stallings, Computer Organization and Architecture, 2016,

10th edition, Pearson / PHI, USA
5
 Introduction To Computer
1 MODULE Architecture and Organization.

6
Key Focus Area of Module 1:
S1 Focus Area Overview of Organization and Architecture –Functional
components of a computer

S2 Focus Area Registers and register files

S3 Focus Area Functional interconnections of components -

Overview of IAS computer

S4 Focus Area Organization of the von Neumann machine - Harvard

architecture

S5 Focus Area CISC & RISC Architectures.

 COMPUTER SYSTEM

8
 COMPUTER ARCHITECTURE
 The term Architecture can be defined as an art and science of designing an object.
(What it has do)

9
 What is computer architecture?

• Computer architecture deals with the functionality of every hardware unit of a CPU. i.e.
what a specific hardware unit works in a computer

• CISC , RISC, MISC

Computer architecture is a specification detailing how a set of software and hardware
technology standards interact to form a computer system or platform.

• It refers to the system attributes visible to a user and what is the direct impact of these
attributes on the program execution. i.e: 32 bit or 64 bit

•Datapath: Single cycle, multi cycle, pipeline

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11
What is computer Organization?
 The computer organization describe the details of the various hardware components related
to the various functional units present in the system.

 The computer organization deals with the arrangement of various system hardware
components and the function performed by the components.

 The computer organization defines the existence of various functional units and its
components .It also defines the interaction between various functional component.

 The computer organization defines the structure and behavior of the digital computers. The
main objective of the computer organization is to understand the various computer
hardware components and the interaction between these components.

12
 computer Organization

13
What is computer organization?
• Computer organization deals with the
implementation of every hardware unit of a
CPU. i.e. how a specific hardware unit works in
a computer

• It refers to the operational units of the

hardware device and interconnections between
various hardware devices realize the
architectural specifications.

•Ex: Hardisk : SATA or SSD, USB etc..

 Difference Between Computer Architecture and
Organization

15
 COMPUTER ARCHITECTURE COMPUTER ORGANISATION
1 Computer Architecture is concerned with the way Computer Organization is concerned with the structure and
hardware components are connected together to behavior of a computer system as seen by the user.(how it has
form a computer system (what it has do) do)

2 It acts as the interface between hardware and It deals with the components of a connection in a system.
software.
3 Computer Architecture helps us to understand the Computer Organization tells us how exactly all the units in
functionalities of a system. the system are arranged and interconnected
4 A programmer can view architecture in terms of Whereas Organization expresses the realization of
instructions, addressing modes and registers. architecture.

5 While designing a computer system architecture is An organization is done on the basis of architecture
considered first.
6 Computer Architecture deals with high-level design Computer Organization deals with low-level design issues.
issues
7 Architecture involves Logic (Instruction sets, Organization involves Physical Components (Circuit design,
Addressing modes, Data types, Cache optimization) Adders, Signals, Peripherals)

16
 Functional components of a computer

There are 4 functional components of a [Link] are:

CPU (Central I/O Main memory System

Processing Unit) (Input/output) interconnection
Functional components of a computer
 Central Processing Unit (CPU)
 Computer processes the received data according to instructions
 Called the brain of the computer because it is the control center of the computer
 Data is fetched either from input device or from memory
 Other processing components are the auxiliary processors – also called as onboard
processors
 Auxiliary processors – to enhance the functionalities of CPU
 Continued…
 Complex components such as graphics card, network interface etc., need
auxiliary processors
 Ex., when a user tries to draw an image, the graphics card does the calculations in
drawing the image

Fig. 1 Auxiliary processor for network interface

Source:
20 [Link] as on 13 July 2020
 Three main components of CPU :

Arithmetic and logic

1
unit (ALU)

2 Control Unit (CU)

3 Memory unit (MU)

21
 Arithmetic and Logic Unit (ALU)

 Perform mathematical calculations

 Takes logical decisions
 Arithmetic operations
Addition
Subtraction
Multiplication
Division
 Logical operations
Comparisons
AND, OR etc.
 Control Unit

 Controls the data flow in and out of the processor

 It also controls the operations of the ALU, memory and I/O devices
 It carries out the instructions stored in the memory
 It decodes those instructions, interprets it and sends control signals to the
I/O devices
CPU
ALU (Arithmetic & Logic Unit): This unit
performs the data processing functions of a computer

Control unit:
 Coordinates the tasks between the computer

components.
 It takes the data from input devices

 Sends the input to processing units

 Transmits the final result/data to output

devices.

Registers: This is a storage unit within the CPU. The

data in this unit is collected from the higher memory
components (i.e. cache).
Input unit

 Input units are used to provide the input data

to the computer to solve the problem given to

the computer.
The commonly used input devices are shown
in the diagram.
Output unit

 The output devices are used to produce

the results which are processed by the
computer system

The most commonly used output devices

are shown in the diagram
System interconnection

 A mechanism that provides for communication among

various components of a computer like CPU, main
memory, secondary memory etc.
 System bus is very common mechanism for connecting
such components
 MEMORY

29
Access Time

Storage
 Memory registers
 Temporary unit of storage in CPU
 Data stored here are directly used by the processor
 Different sizes – 16, 32,64
 Functions of register
Storing data
Storing address
Instruction locations
 User registers can be used to store data and address by the user
 Accumulator is the main register – it always has an operand that would be used by
the ALU
What is RAM?
 The information stored in this type of memory is lost when the power
supply to the PC or laptop is switched off.

SRAM DRAM
 SRAM DRAM

It stores information as long as the power

It stores information as long as the power
is supplied or a few milliseconds when the
is supplied.
power is switched off.
Transistors are used to store information Capacitors are used to store data in
in SRAM. DRAM.
To store information for a longer time, the
Capacitors are not used hence no
contents of the capacitor need to be
refreshing is required.
refreshed periodically.
SRAM is faster compared to DRAM. DRAM provides slow access speeds.
It does not have a refreshing unit. It has a refreshing unit.
36
 SRAM DRAM

These are expensive. These are cheaper.

SRAMs are low-density devices. DRAMs are high-density devices.
In this bits are stored in the form of
In this bits are stored in voltage form.
electric energy.
These are used in cache memories. These are used in main memories.
Consumes less power and generates less Uses more power and generates more
heat. heat.

37
 ROM (Read Only Memory)
 Read-only memory is a type of non-volatile memory used in computers and other
electronic devices.
 Data stored in ROM cannot be electronically modified after the manufacture of the
memory device.
 Data stored in ROM is retained even after the computer is turned off ie, non-
volatile. Types of ROM:
 Programmable ROM, where the data is written after the memory chip has been
created. It is non-volatile.
 Erasable Programmable ROM, where the data on this non-volatile memory
chip can be erased by exposing it to high-intensity UV light.
 Electrically Erasable Programmable ROM, where the data on this non-
volatile memory chip can be electrically erased using field electron emission.
 Difference
Random Access Memory (RAM) Read Only Memory (ROM)

RAM is a volatile memory that could ROM is a non-volatile memory that the
Data-
store the could retain the
Retention
data as long as the power is supplied. data even when the power is turned off.
Read and write operations are
Read/Write Only read operations are supported.
supported.
It is typically used to store firmware or
Used to store the data that has to be
microcode, which is used
Use currently processed by CPU
to initialize and control hardware
temporarily.
components of the computer.
Speed It is a high-speed memory. It is much slower than the RAM.
CPU CPU can easily access data stored in CPU cannot easily access data stored in
39Interaction RAM. ROM.
Difference Random Access Memory
Read Only Memory (ROM)
(RAM)
Size and Large size with higher capacity, Small size with less capacity, concerning
Capacity concerning ROM. RAM.
Used as/in CPU Cache, Primary memory. Firmware, Micro-controllers.
The data stored is easily The data stored is not as easily accessible as
Accessibility
accessible. in the concerning RAM.
Cost RAM is more costlier than ROM. ROM is cheaper than RAM.
A RAM chip can store only a few A ROM chip can store multiple megabytes
Chip Size
gigabytes (GB) of data. (MB) of data.
Used for the temporary storage
Used to store firmware, BIOS, and other
Function of data currently being processed
data that needs to be retained.
40 by the CPU.
Interconnection of components – simple
bus interconnect
Interconnection of components – Bus system
43
Bus interconnect

 The I/O devices, the ALU and the Control Unit are connected together by buses
 Shared transmission medium - busses carry address and data
 Signal transmitted by one device can be received by all the devices connected to
the bus
 Simultaneous transmission of data by two or more devices is not possible since the
data might overlap
 Bus consists of multiple communication pathways or lines
Each line in the bus can carry single binary bit either 0 or 1.
 8 bus lines are required to transmit 8 bit unit of data
 Continued…
System bus  Connects major computer components like I/O devices,
processor, memory etc.

Fig 1 Bus Structure

Source: [Link] as on 16 July 2020
 Continued…
 On a bus, the lines are classified into data lines, address lines and control lines

 Power lines are also available that transmit power to the attached module
 Data lines – path for moving data among the system modules – collectively called
data bus
 Address lines – used to define the source and destination of the data on the data bus
Control lines – Controls the access for data and address lines
 Transmits both command and timing information between modules
Timing signals – how long the data is valid
Command signals – operations to be performed
 Continued…
Control lines
 Memory Write – data on the bus is written to the memory location
Memory read – data from the memory location is moved to the bus
 I/O write – data on the bus is written to the I/O port
 I/O read – data from the I/O device is moved to the bus
 Transfer ack – acknowledges transfer of data from and to I/O ports
 Bus request – indicates that a module needs to take control of the bus
 Continued…

 Bus grant – indicates that the requesting module has been given permission
 Interrupt request – Indicates that an interrupt is pending
Interrupt ack - Acknowledges that the pending interrupt is recognized
 Clock – Used to synchronize operations
 Reset – Initializes every module
 Operation of a bus
 If a module wants to send data
Obtain the use of the bus
Transfer the data
 When a module wants to receive data
Obtain the use of the bus
Send a request to the other module over appropriate control and address lines
Wait for the second module to send the data.

On chip bus – connects processor and memory

 On board bus – connects processor and main memory and other devices
 Computer system can be expanded later
 If a component on a board fails, then component can be replaced easily
 Multiple bus hierarchy
 When many devices are connected to the bus, then performance comes down
 More number of devices – longer bus – large propagation delay
 When the data transfer is high, from many modules, the bus becomes a
bottleneck
Design Elements for bus
Design
Elements

Method of Type of data

Bus Types Timing Bus Width
Arbitration transfer

Dedicated Centralized Synchronous Address Read

Multiplexed Distributed Asynchronous Data Write

Read-modify-
write

Read-after-
write

Block
 1. Bus type
 Dedicated – bus lines are dedicated to a specific function or subset of
components
 Physical dedication – use of a single bus for a single module
 Disadvantage is increased size and cost

 Multiplexed – Address and data can be transmitted over the same bus lines
 Uses fewer lines, less space and low cost
 Disadvantage – complex circuitry for each module
 2. Mode of Arbitration

 Arbitration is used to set either the I/O devices or the processer as master
 Master then transfers data to the appropriate slave

 Centralized scheme – single bus controller is responsible to allocate timing on the

bus
 Distributed scheme – each module contains access control logic and all modules
work synchronously to use the bus
 3. Timing buses
 Synchronous timing or asynchronous timing
 Occurrence of events on the bus is determined by a clock
 Transmission of a single 1-0 defines one clock cycle or bus cycle
 Bus cycle defines a time slot
Synchronous timing

Source: [Link]
module-must-place-data-bus-sufficiently-ahead-q15969579 as on 17 July 2020
Asynchronous timing and data transfer
4. Bus width
 Wider the data bus, large data is transferred at a time
 Wider the address bus, more number of locations can be addressed
Registers and register files
Registers
 Register is a very fast computer memory, used to store data/instruction in-
execution.
 A Register consists of a group of flip-flops and gates that effect their transition.
 A Register constructed with four D-type flip-flops and a common clock pulse
output.
Registers
Registers have 3 specific roles:

1. User visible registers

2. Condition code registers

3. Control and status registers

 Instructions, Operands, Opcodes and Addressing

 Instructions are operations performed by the CPU.

 Operands are entities operated upon by the instruction.
 An opcode is short for 'Operation Code'.
 Addresses are the locations in memory of specified data.

 In assembly language mnemonic form an opcode is a command such as MOV or ADD or JMP.
MOV AL, 34h

In this ex., the operands are the register named AL and the value 34 hex.
 Commonly used Registers
 Accumulator: This is the most common register, used to store data taken out from the
memory.

 General Purpose Registers: This is used to store data intermediate results during
program execution. It can be accessed via assembly programming.

• Data Register : These registers only holds the data. The restriction of these registers
is, these can not be used for operand address calculation
Control / Status - Special Purpose Registers:

 Users do not access these registers. These registers are for Computer
system,
 MAR: Memory Address Register are those registers that holds the address for
memory unit.
 MBR: Memory Buffer Register stores instruction and data received from the
memory and sent from the memory.
 PC: Program Counter holds the address of the next instruction to be read from
memory after the current instruction is executed.
 IR: Instruction Register holds the instruction to be executed.
Control / Status registers
 Parity Flag (PF) − It indicates the total number of 1-bits in the result obtained from an arithmetic
operation.

 Sign Flag (SF) − It shows the sign of the result of an arithmetic operation. This flag is set
according to the sign of a data item following the arithmetic operation.

 Zero Flag (ZF) − It indicates the result of an arithmetic or comparison operation. A nonzero
result clears the zero flag to 0, and a zero result sets it to 1.

 Auxiliary Carry Flag (AF) − It contains the carry from bit 3 to bit 4 following an arithmetic
operation;

 Carry Flag (CF) − It contains the carry of 0 or 1 from a high-order bit (leftmost) after an
arithmetic operation. It also stores the contents of last bit of a shift or rotate operation.
 Control /Status registers
Program status word (PSW): This register contains status information. This also contains
condition codes as well as some status information.

Overflow Flag (OF) − It indicates the overflow of a high-order bit (leftmost bit) of data after
a signed arithmetic operation.

Direction Flag (DF) − It determines left or right direction for moving or comparing string
data.

Interrupt Flag (IF) − It determines whether the external interrupts like keyboard entry, etc.,
are to be ignored or processed.

Trap Flag (TF) − It allows setting the operation of the processor in single-step mode. The
DEBUG program we used sets the trap flag, so we could step through the execution one
instruction at a time.
Processor Registers – Intel Architecture

 There are ten 32-bit and six 16-bit processor registers in IA-32 architecture. The
registers are grouped into three categories −
 General registers,
 Control registers,
 Segment registers.

 The general registers are further divided into the following groups −
 Data registers,
 Pointer registers,
 Index registers.
Data Registers
Data Registers
 Some of these data registers have specific use in arithmetical operations.

 AX is the primary accumulator; it is used in input/output and most arithmetic instructions. For

example, in multiplication operation, one operand is stored in EAX or AX or AL register according to

the size of the operand.

 BX is known as the base register, as it could be used in indexed addressing.

 CX is known as the count register, as the ECX, CX registers store the loop count in iterative

operations.

 DX is known as the data register. It is also used in input/output operations. It is also used with AX

register along with DX for multiply and divide operations involving large values.
Pointer Registers
 The pointer registers are 32-bit EIP, ESP, and EBP registers and corresponding 16-bit right portions
IP, SP, and [Link] are three categories of pointer registers −

 Instruction Pointer (IP) − The 16-bit IP register stores the offset address of the next instruction
to be executed.

 Stack Pointer (SP) − The 16-bit SP register provides the offset value within the program stack.

 Base Pointer (BP) − The 16-bit BP register mainly helps in referencing the parameter variables
passed to a subroutine. The address in SS register is combined with the offset in BP to get the
location of the parameter.
Index Registers
 The 32-bit index registers, ESI and EDI, and their 16-bit rightmost portions.
 SI and DI, are used for indexed addressing and sometimes used in addition and
subtraction.
 There are two sets of index pointers −
 Source Index (SI) − It is used as source index for string operations.
 Destination Index (DI) − It is used as destination index for string operations.
8086 Microprocessor Register Organization
 Von-Neumann vs. Harvard architectures.

76
 Two Types of Computers
 Fixed Program Computers
 They cannot reprogram
 Limited number of specific function
 Designed for accomplish the specific tasks
Eg., Calculators, TV remote, etc..

 Stored Program Computers

 Introduced by Von Neumann in 1940
 They have memory unit attached to it store the instruction
 Design for perform the multiple task
 Contin ….
•Store the instructions and data electronically as binary numbers in a
storage space associated with a computer

•Both instruction and data can be stored in dedicated storage units called
memory
How to implement the Stored-Program
Concept in reality?

SOLUTION:

• Von Neumann Architecture

• Harvard architecture
 Von Neumann architecture
• Von Neumann architecture has common

memory space to store both program and data

memory- uses Stored Program concept
• Central Processing Unit (CPU), Main
Memory Unit and Input/Output Device
• One piece of data or one instruction can able

to read at a time
Basic Von Neumann Architecture

CPU made with three components – Control unit, ALU and Registers
Source: [Link] as on 19 July 2020
Components of Von Neumann Architecture
Control Unit
 Handles all processor control signals
 Controls the directions of all input and output flow
 Fetches code for instructions
 Controls how data travels inside the system

Arithmetic and Logic Unit

• Handles all calculations
• Addition, subtraction, multiplication, division,
comparisons
• Logical operations, bit shifting operations
 Special function Registers
1. Accumulator – Stores the results of ALU
2. Program Counter (PC) – Counter value points to the next
instruction to be executed. This address is given to memory address
register (MAR)
3. Memory Address Register (MAR) – Stores memory locations of
the instruction to be fetched from memory or written to it
4. Memory Data Register (MDR) – Stores instruction fetched or
data to be transferred to memory
5. Current Instruction Register (CIR) – Stores the current
instruction which is to be coded and executed
6. Instruction Buffer Register (IBR) – Instruction which need not be
executed immediately
 What is IAS computer?
 Von-neumann designed a new stored-program
computer in 1946 called IAS computer
 Most of the computers still use the stored program
concept of Von-neumann.

 IAS computer works on following principles:

 Same memory is used to store both the program
and data
 The program is executed in written sequence.
 IAS computer CPU used several vacuum-tubes to
store operands and results.
 Important facts about IAS computer
 The memory contains words that basically represents data or instruction
 The basic data is a binary number in IAS computer
 IAS instructions are 20 bits long.
 Instruction in IAS consists of two parts - 1) operation code or op-code which is of 8-
bit. 2) address of 12-bit
 The IAS computer has CPU
 CPU consists of program control unit and data processing unit. It also contains
control unit along with various set of high speed registers.
 These registers are meant for temporary storage of instructions and data.
 The main memory is used for storing programs and data.
 Bottleneck of Von Neumann
 Instructions can be fetched one at a time and can only be executed sequentially
 Both these factors are the downsides of Von Neumann Architecture
 This is called Von Neumann Bottleneck
 To improve CPU performance, the configuration of the CPU must be inspected
and changed appropriately
 Very important architecture – used in PCs and even in super computers
 Harvard Architecture

 Principles

 In Harvard architecture concept, Memory for data was separated from the memory

for instruction

 This concept is known as the Parallel access of data and instructions are possible
 Features of Harvard Architecture
 Separate data path and instruction path is available
 An instruction is executed in a single cycle
 Fetching of data and instructions can be done simultaneously
 There is less chance of corruption since data and instructions are
transferred via different buses
 Modern processors uses Harvard architecture
90
Difference between Von Neumann and Harvard
Architectures
S. No Von Neumann Architecture Harvard Architecture

1. Common bus for transfer of data Separate buses for data and
and instruction instruction
2. Two clock cycles are required for Single clock cycle for single
a single instruction instruction
3. CPU cannot access instruction CPU can simultaneously fetch
and read/write simultaneously instructions and perform
read/write operations
4. It is used in personal computers It is used in micro controllers and
and small computers signal processing.
 RISC Vs CISC

92
 RISC architecture
 Instruction set contains limited and simple instructions
 If data in memory is to be referenced, only LOAD and STORE instructions are
used.
 Instructions use very few addressing modes
 Instructions are short and have a fixed format
 Number of registers available are more
Simple and small execution hardware is necessary
 A hard-wired controller is needed rather than a microprogram
 CPU takes only less silicon area and runs faster
 Per clock cycle only one machine instruction is executed
 Register to register operations are possible
 Continued – One instruction per clock
cycle
 Machine cycle – time taken to fetch two operands from registers, perform ALU
operation and store the result in another register
 RISC instruction pipeline is more efficient due to simple instructions
 In RISC architecture, complex instructions are executed as a set of simple instructions
 Register to register operation

 Only LOAD and STORE instructions reference data memory

 All other operations work with registers alone
 This characteristic simplifies the instruction set and therefore the control path
 Since registers are used more than memory locations, the highly used operands are
readily available for quick access
 Continued….

 Variables and intermediate results can be stored in registers

 Hence there is no need to use LOAD and STORE repeatedly
 Since the complex instructions are converted to simpler ones, there is extra silicon
area where more number of registers can be designed.
 This is typical of RISC architecture.
 Other characteristics of RISC

 Only few simple addressing modes are used

 All RISC instructions use simple register addressing modes
 Ex., register direct, indirect indexed etc.
 Instructions are of fixed length and uniform format and hence loading and decoding
of instructions are fast.
 There is no need to wait to know the length of the instruction in order to start
decoding
 Advantages of RISC
 Simplicity: RISC architectures have a simplified instruction set, which makes the
hardware design and instruction execution relatively straightforward. This simplicity
enables faster execution and easier debugging of programs.
Performance: RISC processors typically have a higher clock speed compared to
complex instruction set computer (CISC) processors. The reduced instruction set
allows for a smaller, simpler instruction pipeline, which can result in faster execution
times for many common operations.
Reduced Complexity: RISC architectures typically have a smaller number of
instructions, making them easier to understand, program, and maintain. This
simplicity can lead to faster development and reduced design complexity for both
hardware and software.

Optimization of frequently used and most used instructions

 Disadvantages of RISC
 [Link] Size: RISC architectures often require more instructions to perform complex operations
compared to CISC architectures. This can result in larger program sizes and increased memory
usage.
 2. Limited Instructions: RISC architectures may lack certain complex instructions that are
available in CISC architectures. This can make certain high-level operations more time-consuming
to implement and may require more instructions to achieve the same result.
 3. Memory Access: RISC architectures commonly use on load/store architectures, where data
must be explicitly loaded from memory to registers before operations can be performed. This can
lead to increased memory access instructions and potential performance bottlenecks.
 4. Development Complexity: While RISC architectures offer simplicity, they can place more
burden on software developers. Developers need to manually optimize code and handle more
low-level details, such as register allocation and instruction scheduling, to achieve optimal
performance.
 5. Increased Compiler Dependency: RISC architectures heavily rely on efficient compilers to
optimize code and take advantage of the architecture's features. If a reliable and efficient compiler
is not available for a particular RISC architecture, it can impact overall performance and
development experience.
 CISC ARCHITECTURE

 It has large number of instructions, complex instructions and data types

 Complex addressing modes
 Direct hardware implementation of high level language segments
 Microprogramming technique is used to implement complicated instructions
 Memory bottleneck – due to complex addressing modes and multiple memory access
per instruction
 Continued
 Programs are smaller in size hence they have better performance
They consume less memory space
Fewer instruction leads to fewer fetch operations and hence smaller execution time
In paging method, fewer pages are sufficient and hence page faults are reduced.
 Execution efficiency is improved by using microcode instead of machine codes for
complex operations.
 Disadvantages of CISC
 Complex instructions are harder to implement
Though programs are short and occupy less memory, it doesn’t add as an advantage
because memory is cheap nowadays
 More complex control unit
 Microprogram control takes more storage space
 Hence, simple instructions take longer to execute
 continued

 Since the instruction set is large, it requires complex hardware steps for decoding and
executing instructions
 This instruction set may not match high level language statements
 The instruction sets designed for executing instructions of many high level languages
might not efficiently execute instructions of a single language
 Design tasks are complex
comparisons
 How should new high level programs be compiled and executed efficiently on a
processor architecture?
1. CISC: design very complex architectures using a large instruction set and complex
addressing modes. Include instructions that are close to those in HLL
2. RISC: simplify the instruction set and adapt it to the requirements of the user’s
program
CISC Example:
Consider the following CISC-style instruction:
MOV AX, [BX+SI+10]
 In this instruction, the value at the memory address calculated by adding the contents of
registers BX, SI, and 10 is loaded into register AX. CISC instructions often involve complex
addressing modes and can perform multiple operations in a single instruction.
RISC Example:
Now let's consider the same example using RISC-style instructions:
 LOAD R1, [R2+R3]
 ADD R1, R1, #10
 In this RISC example, two separate instructions are used. The first instruction loads the value
at the memory address calculated by adding the contents of registers R2 and R3 into register
R1. The second instruction adds an immediate value of 10 to the contents of register R1.
RISC instructions are simpler and typically perform a single operation per instruction.
 Which one is better? RISC or CISC?
1. Many comparisons show that benchmark programs are run really faster in RISC
then CISC
2. But, the fastness is not attributed completely to the RISC architecture. Some
would say that the speed is due to better technology and compilers
3. CISC requires lesser memory to store the program since it consists of lesser
number of instructions.
4. Most current processors are not dedicatedly made of RISC or CISC, they have a
combination of both the architectures.
Consider that a program has 60 % simple instruction and 40 % complex instruction. The
cycle time is 100 ns. The total number of instruction is 7,00,000. Following table gives you
the number of machine cycles for simple and complex instructions. Calculate the time
taken to execute the whole program in both RISC and CISC architecture and compare the
both. Conclude which architecture is best.

Type of Number of Machine Number of Machine

Architecture Cycles for Simple Cycles for Complex
Instruction Instruction
RISC 1 12
CISC 4 8
RISC Architecture:
- Number of machine cycles for simple instructions: 1
- Number of machine cycles for complex instructions: 12
Total machine cycles for simple instructions = Number of machine cycles for simple
instructions * Percentage of simple instructions * Total number of instructions
= 1 * 0.6 * 700,000
= 420,000

Total machine cycles for complex instructions = Number of machine cycles for complex instructions *
Percentage of complex instructions * Total number of instructions
= 12 * 0.4 * 700,000
= 3,360,000
Total time for simple instructions = Total machine cycles for simple instructions * Cycle time
= 420,000 * 100 ns
= 42,000,000 ns
= 42 ms
Total time for complex instructions = Total machine cycles for complex instructions * Cycle
time
= 3,360,000 * 100 ns
= 336,000,000 ns
= 336 ms

Total time taken to execute the whole program in RISC architecture = Total time for simple
instructions + Total time for complex instructions
= 42 ms + 336 ms
= 378 ms
CISC Architecture:
- Number of machine cycles for simple instructions: 4
- Number of machine cycles for complex instructions: 8
Total machine cycles for simple instructions = Number of machine cycles for simple instructions *
Percentage of simple instructions * Total number of instructions
= 4 * 0.6 * 700,000
= 1,680,000
Total machine cycles for complex instructions = Number of machine cycles for complex
instructions * Percentage of complex instructions * Total number of instructions
= 8 * 0.4 * 700,000
= 2,240,000
Total time for simple instructions = Total machine cycles for simple instructions * Cycle time
= 1,680,000 * 100 ns
= 168,000,000 ns
= 168 ms
Total time for complex instructions = Total machine cycles for complex instructions * Cycle time
= 2,240,000 * 100 ns
= 224,000,000 ns
= 224 ms
Total time taken to execute the whole program in CISC architecture = Total time for simple
instructions + Total time for complex instructions
= 168 ms + 224 ms
= 392 ms
After recalculating with the correct number of machine cycles, we can see that the time taken to
execute the whole program is 378 ms for RISC architecture and 392 ms for CISC architecture.
In this case, the RISC architecture appears to be slightly faster than the CISC architecture for
executing the given program. However, it's important to consider other factors such as the specific
requirements of the program, the available hardware, and the ease of programming before
determining which architecture is the best choice.