ARM

Advanced RISC Machine (ARM) Processor is considered to be family of

Central Processing Units that is used in music players, smartphones,
wearables, tablets and other consumer electronic devices.

The architecture of ARM processor is created by Advanced RISC

Machines, hence name ARM. This needs very few instruction sets and
transistors. It has very small size. This is reason that it is perfect fit for
small size devices. It has less power consumption along with reduced
complexity in its circuits.

They can be applied to various designs such as 32-bit devices and

embedded systems. They can even be upgraded according to user
needs.
 The main features of ARM Processor
Multiprocessing Systems –
ARM processors are designed so that they can be used in cases of
multiprocessing systems where more than one processors are used to process
information. First AMP processor introduced by name of ARMv6K had ability
to support 4 CPUs along with its hardware.

Tightly Coupled Memory –

Memory of ARM processors is tightly coupled. This has very fast response
time. It has low latency (quick response) that can also be used in cases of
cache memory being unpredictable.

Memory Management –
ARM processor has management section. This includes Memory Management
Unit and Memory Protection Unit. These management systems become very
important in managing memory efficiently.
 The main features of ARM Processor
Thumb-2 Technology –
Thumb-2 Technology was introduced in 2003 and was used to create variable
length instruction set. It extends 16-bit instructions of initial Thumb
technology to 32-bit instructions. It has better performance than previously
used Thumb technology.

One cycle execution time –

ARM processor is optimized for each instruction on CPU. Each instruction is of
fixed length that allows time for fetching future instructions before executing
present instruction. ARM has CPI (Clock Per Instruction) of one cycle.
Pipelining –
Processing of instructions is done in parallel using pipelines. Instructions are
broken down and decoded in one pipeline stage. The pipeline advances one
step at a time to increase throughput (rate of processing).

Large number of registers –

Large number of registers are used in ARM processor to prevent large amount
of memory interactions. Registers contain data and addresses. These act as
local memory store for all operations.
 ARM Architecture

The ARM architecture processor is an advanced reduced instruction set

computing [RISC] machine and it’s a 32bit reduced instruction set computer
(RISC) microcontroller. It was introduced by the Acron computer organization
in 1987. This ARM is a family of microcontroller developed by makers like ST
Microelectronics,Motorola, and so on. The ARM architecture comes with
totally different versions like ARMv1, ARMv2, etc., and, each one has its own
advantage and disadvantages.
Arm architecture
Arm block diagram
 ARM family
The ARM cortex is a complicated microcontroller within the ARM family that
has ARMv7 design. There are 3 subfamilies within the ARM cortex family :

ARM Cortex Ax-series

ARM-Cortex Rx-series
ARM-Cortex Mx-series

The ARM Architecture have

Arithmetic Logic Unit

Booth multiplier
Barrel shifter
Control unit
Register file
ARM Microcontroller Register Modes
An ARM microcontroller is a load store reducing instruction set computer
architecture means the core cannot directly operate with the memory. The
data operations must be done by the registers and the information is stored in
the memory by an address. The ARM cortex-M3 consists of 37 register sets
wherein 31 are general purpose registers and 6 are status registers. The ARM
uses seven processing modes to run the user task.

USER Mode
FIQ Mode
IRQ Mode
SVC Mode
UNDEFINED Mode
ABORT Mode
Monitor Mode
USER Mode: The user mode is a normal mode, which has the least number of
registers. It doesn’t have SPSR and has limited access to the CPSR.
FIQ and IRQ: The FIQ and IRQ are the two interrupt caused modes of the CPU.
The FIQ is processing interrupt and IRQ is standard interrupt. The FIQ mode
has additional five banked registers to provide more flexibility and high
performance when critical interrupts are handled.
SVC Mode: The Supervisor mode is the software interrupt mode of the
processor to start up or reset.
Undefined Mode: The Undefined mode traps when illegal instructions are
executed. The ARM core consists of 32-bit data bus and faster data flow.
THUMB Mode: In THUMB mode 32-bit data is divided into 16-bits and
increases the processing speed.
THUMB-2 Mode: In THUMB-2 mode the instructions can be either 16-bit or
32-bit and it increases the performance of the ARM cortex –M3
microcontroller. The ARM cortex-m3 microcontroller uses only THUMB-2
instructions.
Some of the registers are reserved in each mode for the specific use of the
core. The reserved registers are
Stack Pointer (SP).
Link Register (LR).
Program Counter (PC).
Current Program Status Register (CPSR).
Saved Program Status Register (SPSR).

The reserved registers are used for specific functions. The SPSR and CPSR
contain the status control bits which are used to store the temporary data.
The SPSR and CPSR register have some properties that are defined operating
modes, Interrupt enable or disable flags and ALU status flag.

The ARM core operates in two states 32-bit state or THUMBS state.
 ARM and Thumb state
Versions 4T and 4TxM of the ARM architecture define a 16-bit instruction set
called the Thumb instruction set. The functionality of the Thumb instruction set
is a subset of the functionality of the 32-bit ARM instruction set.

The Thumb instruction set:

imposes some limitations on register access (see Thumb instruction capabilities).

does not allow conditional execution except for branch instructions

(see Conditional execution)

does not allow access to the barrel shifter except as a separate instruction.
Refer to Thumb instruction set overview for more information.

A processor that is executing Thumb instructions is said to be operating in Thumb

state. A Thumb-capable processor that is executing ARM instructions is said to be
operating in ARM state.
ARM processors always start in ARM state. You must explicitly change to Thumb
state using a BX (Branch and exchange instruction set) instruction.
 Thumb instruction set overview
The functionality of the Thumb instruction set, with one exception, is a subset of
the functionality of the ARM instruction set. The instruction set is optimized for
production by a C compiler.

All Thumb instructions are 16 bits long and are stored halfword aligned in memory.
Because instructions are stored halfword-aligned, the bottom bit of the address of
an instruction is always set to zero in Thumb state. This bit is ignored by all Thumb
instructions that have an address operand except for the Branch Exchange (BX)
instruction.

All Thumb data processing instructions:

operate on full 32-bit values

use full 32-bit addresses for data access and for instruction fetches.
In general, the Thumb instruction set differs from the ARM instruction set in the
following ways. Refer to the ARM Architectural Reference Manual for detailed
information on the syntax of the Thumb instruction set, and how Thumb
instructions differ from their ARM counterparts:
 Thumb instruction set overview
Branch instructions
These instructions are used to branch backwards to form loops, to branch forward
in conditional structures, to branch to subroutines, and to change the processor
from Thumb state to ARM state. Program-relative branches, particularly conditional
branches, are more limited in range than in ARM code, and branches to
subroutines can only be unconditional.

Data processing instructions

These operate on the general purpose registers. The result of the operation is put
in one of the operand registers, not in a third register. There are fewer data
processing operations available than in ARM state. They have limited access to
registers r8 to r15.

The ALU status flags in the CPSR are always set by these instructions except
when MOV or ADD instructions access registers r8 to r15. Thumb data processing
instructions that access registers r8 to r15 cannot set the flags.
Status register access instructions: There are no Thumb instructions to access
the CPSR or SPSR.
Single register load and store instructions: These instructions load or store the
value of a single low register from or to memory. In Thumb state they cannot
access registers r8 to r15.
Multiple register load and store instructions :These instructions load from
memory or store to memory any subset of the registers in the range r0 to r7.
In addition, the PUSH and POP instructions implement a full descending stack
using the stack pointer (r13) as the base. PUSH can stack the link register
and POP can load the program counter.

Semaphore instructions There are no Thumb semaphore instructions.

Coprocessor instructions There are no Thumb coprocessor instructions.
 Thumb instruction capabilities
The following general points apply to Thumb instructions:

Conditional execution
The conditional branch instruction is the only Thumb instruction that can be
executed conditionally on the value of the ALU status flags in the CPSR. All
data processing instructions set these flags, except when one or more high
registers are specified as operands to the MOV or ADD instructions. In these
cases the flags cannot be set.

You cannot have any data processing instructions between an instruction that
sets a condition and a conditional branch that depends on it. You must use
conditional branches over any instructions that you wish to be conditional.

Register accessIn Thumb state, most instructions can access only r0-r7. These
are referred to as the low registers.
Registers r8 to r15 are limited access registers. In Thumb state these are
referred to as high registers. They can be used, for example, as fast temporary
storage.

Refer to the ARM Architectural Reference Manual for a complete list of the
Thumb data processing instructions that can access the high registers.

Access to the barrel shifter

In Thumb state you can use the barrel shifter only in a separate operation,
using an LSL, LSR, ASR, or ROR instruction.
ARM Instruction Sets

Jin-Fu Li
Department of Electrical Engineering
National Central University
Jungli, Taiwan
 Outline
Registers, Memory Access, and Data Transfer
Arithmetic and Logic Instructions
Branch Instructions
Assembly Language
I / O Operations
Subroutines
Program Examples

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19

 Content Coverage

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 ARM Processor
ARM processor was designed by Advanced RISC
Machine (ARM) Limited Company
ARM processors are major used for low-power and low
cost applications
◆ Mobile phones
◆ Communication modems
◆ Automotive engine management systems
◆ Hand-held digital systems
This chapter introduces the ARM instruction sets based on
the ARM7 processor
◆ Different versions of ARM processors share the same basic
machine instruction sets

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21

 Registers and Memory Access
In the ARM architecture
◆ Memory is byte addressable
◆ 32-bit addresses
◆ 32-bit processor registers
Two operand lengths are used in moving data between the
memory and the processor registers
◆ Bytes (8 bits) and words (32 bits)
Word addresses must be aligned, i.e., they must be
multiple of 4
◆ Both little-endian and big-endian memory addressing are
supported
When a byte is loaded from memory into a processor
register or stored from a register into the memory
◆ It always located in the low-orde r byte position of the register
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22
 Register Structure
31 0
R0
R1
15
General
Purpose
registers

R14

31 0
R15 (PC) Program counter

31 30 29 7 4 0
CPSR 28 6 … Status register
N-Negative
Z-Zero
C-Carry Processor mode bits
V-Overflow Interrupt disable bits
Conditional code flags
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 Register Structure
processor mode bits and interrupt disable bits

There are 15 additional general-purpose registers called the

banked registers
◆ They are duplicates of some of the R0 to R14 registers
◆ They are used when the processor switches into Supervisor or
Interrupt modes of operation

Saved copies of the Status register are also available in the

Supervisor and Interrupt modes

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24

 ARM Instruction Encoding Format
Each instruction is encoded into a 32-bit word
Access to memory is provided only by Load and Store
instructions
The basic encoding format for the instructions, such as Load,
Store, Move, Arithmetic, and Logic instructions, is shown
below
31 28 2720 1916 1512 114 3 0

Condition OP code Rn Rd Other info Rm

An instruction specifies a conditional execution code

(Condition), the OP code, tw o or three registers (Rn, Rd, and
Rm), and some other information

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25

 Conditional Execution of Instructions

A distinctive and somewhat unusual feature of ARM

processors is that all instructions are conditionally
executed
◆ Depending on a condition specified in the instruction
The instruction is executed only if the current state of the
processor condition code flag satisfies the condition
specified in bits b31-b28 of the instruction
◆ Thus the instructions whose condition is not meet the processor
condition code flag are not executed
One of the conditions is used to indicate that the
instruction is always executed

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 Memory Addressing Modes
Pre-indexed mode
◆ The effective address of the operand is the sum of the contents of the
base register Rn and an offset value

Pre-indexed with writeback mode

◆ The effective address of the operand is generated in the same way as in
the Pre-indexed mode, and then the effective address is
written back into Rn

Post-indexed mode
◆ The effective address of the operand is the contents of Rn. The offset
is then added to this address and the result is written back into Rn

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27

 ARM Indexed Addressing Modes
Name Assembler syntax Addressing function
With immediate offset:
Pre-indexed [Rn, #offset] EA=[Rn]+offset
Pre-indexed with writeback [Rn, #offset]! EA=[Rn]+offset; Rn [Rn]+offset
Post-indexed [Rn], #offest EA=[Rn]; Rn [Rn]+offset

With offset in Rn
Pre-indexed [Rn, +Rm, shift] EA=[Rn]+[Rm] shifted
Pre-indexed with writeback [Rn, +Rm, shift]! EA=[Rn]+[Rm] shifted;
Rn [Rn]+ [Rm] shifted
Post-indexed [Rn], +Rm, shift EA=[Rn];
Rn [Rn]+ [Rm] shifted
Location EA=Location=[PC]+offset
Relative (Pre-indexed with
Immediate offset)
shift=direction #integer, where direction is LSL for left shift or LSR for right shift, and integer is a
5-bit unsigned number specifying the shift format
+ Rm=the offset magnitude in register Rm can be added to or subtracted from the contents
of based register Rn
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 Relative Addressing Mode
Memory
address word (4 bytes)

1000 LDRR1, ITEM

1004 -
1008 - Updated [PC]=1008

52=offset

ITEM=1060 Operand

The operand must be within the range of 4095 bytes forward or backward from the
updated PC.

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 Pre-Indexed Addressing Mode

1000 R5
Based register
STR R3, [R5,R6]
200 R6
Offset register

1000

200=offset

1200 Operand

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 Post-Indexed Addressing with Writeback

1000 R2
Based register
1000 6
25 R10
100=25x4
Offset register

1100 -17

100=25x4

Load instruction:
1200 321 LDR R1, [R2], R10, LSL, #2

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 Pre-Indexed Addressing with Writeback

2012 R5
Based register (stack pointer)

27 R0

2008 27
2012 - TOS (top-of-stack)

After execution of
Push instruction
Push instruction:
STR R0, [R5,# -4]!

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 Load/Store Multiple Operands
In ARM processors, there are two instructions for loading and
storing multiple operands
◆ They are called Block transfer instructions
Any subset of the general purp ose registers can be loaded or
stored
◆ Only word operands are allowed, and the OP codes used are
LDM (Load Multiple) and STM (Store Multiple)
The memory operands must be in successive word
locations
All of the forms of pre- and post-indexing with and
without writeback are available
They operate on a Base register Rn specified in the
instruction and offset is always 4
◆ LDMIA R10!, {R0,R1,R6,R7}
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 Load/Store Multiple Operands
LDMIA and STMIA
Load and store multiple registers.

Syntax
op Rn!, {reglist}

where:
Op is either: LDMIA Load multiple, increment after
STMIA Store multiple, increment after.

Rn is the register containing the base address.

Rn must be in the range r0-r7.
Reglist is a comma-separated list of low registers or low-register
ranges.
 Load/Store Multiple Operands
Usage

Registers are loaded stored and in numerical order, with the lowest
numbered register at the address initially in Rn.

The value in Rn is incremented by 4 (times the number of registers

in reg-list.)

Incorrect examples

LDMIA r3!,{r0,r9} ; high registers not allowed

STMIA r5!, {} ; must be at least one register ; in list
STMIA r5!,{r1-r6} ; value stored from r5 is unpredictable
 Arithmetic Instructions
The basic expression for arithmetic instructions is
◆ OPcode Rd, Rn, Rm
For example, ADD R0, R2, R4
◆ Performs the operation R0 [R2]+[R4]
SUB R0, R6, R5
◆ Performs the operation R0 [R6]-[R5]
Immediate mode: ADD R0, R3, #17
◆ Performs the operation R0 [R3]+17
The second operand can be shifted or rotated before being
used in the operation
◆ For example, ADD R0, R1, R5, LSL #4 operates as follows: the
second operand stored in R5 is shifted left 4-bit positions
(equivalent to [R5]x16), and its is then added to the contents of
R1; the sum is placed in R0

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 Logic Instructions
The logic operations AND, OR, XOR, and Bit-Clear are
implemented by instructions with the OP codes AND,
ORR, EOR, and BIC.
For example
◆ AND R0, R0, R1: performs R0 [R0]+[R1]
The Bit-Clear instruction (BIC) is closely related to the
AND instruction.
◆ It complements each bit in operand Rm before ANDing them
with the bits in register Rn.
◆ For example, BIC R0, R0, R1. Let R0=02FA62CA, R1=0000FFFF.
Then the instruction results in the pattern 02FA0000 being placed in
R0
The Move Negative instruction complements the bits of the
source operand and places the result in Rd.
◆ For example, MVN R0, R3
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 Branch Instructions
Conditional branch instructions contain a signed 24-bit
offset that is added to the updated contents of the
Program Counter to generate the branch target address
The format for the branch instructions is shown as below

31 28 27 24 23 0
Condition OP code offset

◆ Offset is a signed 24-bit number. It is shifted left two-bit positions (all

branch targets are aligned word addresses), signed extended
to 32 bits, and added to the updated PC to generate the branch
target address
◆ The updated PC points to the instruction that is two words (8 bytes)
forward from the branch instruction

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 ARM Branch Instructions
The BEQ instruction (Branch if Equal to 0) causes a
branch if the Z flag is set to 1

1000 BEQ LOCATION

1004
Updated [PC]=1008

Offset=92

LOCATION=1100 Branch target instruction

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 Setting Condition Codes
Some instructions, such as Compare, given by
◆ CMP Rn, Rm which performs the operation [Rn]-[Rm] have the
sole purpose of setting the cond ition code flags based on the
result of the subtraction operation
The arithmetic and logic instructions affect the condition
code flags only if explicitly specified to do so by a bit in
the OP-code field. This is indicated by appending the
suffix S to the OP-code
◆ For example, the instruction ADDS R0, R1, R2 set the condition
code flags
◆ But ADD R0, R1, R2 does not

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40

 An Example of Adding Numbers

LDR R1, N Load count into R1

LDR R2, POINTER Load address NUM1 into R2
MOV R0, #0 Clear accumulator R0
LOOP LDR R3, [R2], #4 Load next number into R3
ADD R0, R0, R3 Add number into R0
SUBS R1, R1, #1 Decrement loop counter R1
BGT LOOP Branch back if not done
STR R0, SUM Store sum

Assume that the memory location N, PO INTER, and SUM are within the range
Reachable by the offset relative to the PC
GT: signed greater than BGT:
Branch if Z=0 and N=0

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 Assembly Language
The ARM assembly language has assembler directives to
reserve storage space, assign numerical values to address
labels and constant symbols, define where program and data
blocks are to be placed in memory, and specify the end of the
source program text
The AREA directive, which uses the argument CODE or
DATA, indicates the beginning of a block of memory that
contains either program instructions or data
The ENTRY directive specifies that program execution is to
begin at the following LDR instruction
In the data area, which follows the code area, the DCD
directives are used to label and initialize the data operands

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 An Example of Assembly Language
Assembler directives AREA CODE
ENTRY

Statements that LDR R1, N

generate LDR R2, POINTER
machine MOV R0, #0
instructions LOOP LDR R3, [R2], #4
ADD R0, R0, R3
SUBS R1, R1, #1
BGT LOOP
STR R0, SUM
Assembler directives AREA DATA
SUM DCD 0
N DCD 5
POINTER DCD NUM1
NUM1 DCD 3, -17, 27, -12, 322
END

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 Assembly Language
An EQU directive can be used to define symbolic names for
constants
For example, the statement
◆ TEN EQU 10
When a number of registers are used in a program, it is
convenient to use symbolic na mes for them that relate to
their usage
◆ The RN directive is used for this purpose
◆ For example, COUNTER RN 3 establishes the name COUNTER for
register R3
The register names R0 to R15, PC (for R15), and LR( for
R14) are predefined by the assembler
◆ R14 is used for a link register (LR)

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