Chapter 4-Basic Computer Organization and Design

Computer organization refers to the operational unit and their interconnection that realize the
architectural specification. Computer organization deals with how different parts of a computer are
organized and how various operations are performed between different parts to do a specific task. The
organization of the computer is defined by its internal registers, timing and control structure, and set of
instruction that is uses.

4.1. Design of a Basic Computer

Basic computer is a model (an imaginary system) that helps to understand the basic concepts behind
designing a computer. A basic computer consists of the following hardware components.

1. A memory unit with 4096 words of 16 bits each

2. Registers: AC (Accumulator), DR (Data register), AR (Address register), IR (Instruction register), PC

(Program counter), TR (Temporary register), SC (Sequence Counter), INPR (Input register), and
OUTR (Output register).

3. Flip-Flops: I, S, E, R, IEN, FGI and FGO

 • S2S1S0: Selects the register/memory that
would use the bus
• LD (load): When enabled, the particular
register receives the data from the bus
during the next clock pulse transition
• E(extended AC bit): flip-flop holds the carry
• DR, AC, IR, and TR: have 16 bits each
• AR and PC: have 12 bits each since they
hold a memory address
• When the contents of AR or PC are applied
to the 16-bit common bus, the four most
significant bits are set to zeros
• When AR or PC receives information from
the bus, only the 12 least significant bits are
transferred into the register
• INPR and OUTR: communicate with the
eight least significant bits in the bus
• INPR: Receives a character from the input
device (keyboard,…etc) which is then
transferred to AC
• OUTR: Receives a character from AC and
delivers it to an output device (say a
Monitor)
• Five registers have three control inputs: LD
(load), INR (increment), and CLR (clear)

The input data and output data of the memory are connected to the common bus. But the memory
address is connected to AR. Therefore, AR must always be used to specify a memory address. By using a
single register for the address, we eliminate the need for an address bus that would have been needed
otherwise.

• Register  Memory: Write operation

• Memory  Register: Read operation (note that AC cannot directly read from memory)

Note that the content of any register can be applied onto the bus and an operation can be performed in
the adder and logic circuit during the same clock cycle.

The transition at the end of the cycle transfers the content of the bus into the destination register, and the
output of the adder and logic circuit into the AC.

For example, the two micro-operations

DR←AC and AC←DR (Exchange)

 can be executed at the same time. This is done by:

• 1- place the contents of AC on the bus (S2S1S0=100)

• 2- enabling the LD (load) input of DR

• 3- Transferring the contents of the DR through the adder and logic circuit into AC

• 4- enabling the LD (load) input of AC

All during the same clock cycle. The two transfers occur upon the arrival of the clock pulse transition at the
end of the clock cycle.

4.2. Instructional Code

Computer instructions are a set of machine language instructions that a particular processor understands
and executes. A computer performs tasks on the basis of the instruction provided. An instruction
comprises of groups called fields. These fields include:

 The Operation code (Opcode) field which specifies the operation to be performed.

 The Address field which contains the location of the operand, i.e., register or memory location.

 The Mode field which specifies how the operand will be located.

A basic computer has three instruction code formats which are: Memory–reference instruction, Register–
reference instruction and Input-Output instruction.

Memory-reference instruction
In Memory-reference instruction, 12 bits of memory is used to specify an address and one bit to specify
the addressing mode ‘I’.

Register-reference instructions
The Register-reference instructions are represented by the Opcode 111 with a 0 in the leftmost bit (bit 15)
of the instruction.
The Operation code (Opcode) of an instruction refers to a group of bits that define arithmetic and logic
operations such as add, subtract, multiply, shift, and compliment. A Register-reference instruction
specifies an operation on or a test of the AC (Accumulator) register.

Input-Output instruction
Just like the Register-reference instruction, an Input-Output instruction does not need a reference to
memory and is recognized by the operation code 111 with a 1 in the leftmost bit of the instruction. The
remaining 12 bits are used to specify the type of the input-output operation or test performed.

 The three operation code bits in positions 12 through 14 should be equal to 111. Otherwise, the
instruction is a memory-reference type, and the bit in position 15 is taken as the addressing mode I.

 When the three operation code bits are equal to 111, control unit inspects the bit in position 15. If
the bit is 0, the instruction is a register-reference type. Otherwise, the instruction is an input-
output type having bit 1 at position 15.

4.3. Instruction Cycle

A program residing in the memory unit of a computer consists of a sequence of instructions. These
instructions are executed by the processor by going through a cycle for each instruction.

In a basic computer, each instruction cycle consists of the following phases:

1. Fetch instruction from memory.

2. Decode the instruction.

3. Read the effective address from memory.

4. Execute the instruction.

4.4. Timing and Control
The timing for all registers in the basic computer is controlled by a master clock generator. The clock
pulses are applied to all flip-flops and registers in the system, including the flip-flops and registers in the
control unit. The clock pulses do not change the state of a register unless the register is enabled by a
control signal (i.e., Load).

The control signals are generated in the control unit and provide control inputs for the multiplexers in the
common bus, control inputs in processor registers, and micro-operations for the accumulator. There are
two major types of control organizations. These are:

– Hardwired control
• In the hardwired organization, the control logic is implemented with gates, flip-flops,
decoders, and other digital circuits.

– Micro-programmed control
• In the micro-programmed organization, the control information is stored in a control
memory (if the design is modified, the micro-program in control memory has to be
updated)

4.5. Input-Output Configuration

In computer architecture, input-output devices act as an interface between the machine and the user.
Instructions and data stored in the memory must come from some input device. The results are displayed
to the user through some output device. The following block diagram shows the input-output
configuration for a basic computer.

 The input-output terminals send and receive information.

  The amount of information transferred will always have eight bits of an alphanumeric code.

 The information generated through the keyboard is shifted into an input register ‘INPR’.

 The information for the printer is stored in the output register ‘OUTR’.

 Registers INPR and OUTR communicate with a communication interface serially and with the AC in
parallel.

 The transmitter interface receives information from the keyboard and transmits it to INPR.

 The receiver interface receives information from OUTR and sends it to the printer serially.
4.6. Central Processing Unit
The part of computer that does data processing operations is called central processing unit (CPU)
The CPU is made of 3 parts:
1. Registers: stores intermediate data generated during execution
2. ALU: performs required micro operations
3. Control Unit: controls transfer of data among registers and instruct ALU to perform correct operation
General Register Organization

A flip-flop in digital electronics is a circuit with two stable states that can be used to store binary data. A
set of flip-flops forms a register. A register is a unique high-speed storage area in the CPU. The information
is always defined in a register before processing. Registers speed up the implementation of programs.

Registers implement two important functions in the CPU operation are as follows −

 It can support a temporary storage location for data. This supports the directly implementing
programs to have fast access to the data if required.

 It can save the status of the CPU and data about the directly implementing program.

Intermediate data are needed to be stored like pointers, counters, return address, temp results, and
partial products. Intermediate data cannot be saved in main memory because their access is time
consuming. It is more efficient and faster to store them inside processor and connect them through a
common bus. In Basic Computer, there is only one general purpose register, the Accumulator (AC) but in
modern CPUs, there are many general purpose registers. It is advantageous to have many registers.
Transfers between registers within the processor are relatively fast. Going “off the processor” to access
memory is much slower.
4.7. Stack Organization
A useful feature that is included in the CPU of most computers is a stack or last-in, first-out (LIFO) list. A
stack is a storage device that stores information in such a manner that the item stored last is the first item
retrieved. The stack in digital computers is essentially a memory unit with an address register that can
count only (after an initial value is loaded into it). The register that holds the address for the stack is
called a stack pointer (SP) because its value always points at the top item in the stack. The two
operations of a stack are the insertion and deletion of items. However, nothing is pushed or popped in a
computer stack. These operations are simulated by incrementing or decrementing the stack pointer
register. Register Stack can be placed in a portion of a large memory or it can be organized as a collection
of a finite number of memory words or registers. The figure below shows the organization of a 64-word
register stack.
The stack pointer register SP contains a binary
number whose value is equal to the address of
the word that is currently on top of the stack.
Three items are placed in the stack: A, B, and C,
in that order. Item C is on top of the stack so that
the content of SP is now 3. To remove the top
item, the stack is popped by reading the memory
word at address 3 and decrementing the content
of SP. Item B is now on top of the stack since SP
holds address 2. To insert a new item, the stack is
pushed by incrementing SP and writing a word in
the next-higher location in the stack. Note that
item C has been read out but not physically
removed. This does not matter because when
the stack is pushed, a new item is written in its
place. In a 64-word stack, the stack pointer
contains 6 bits because 26 =64. Similarly, when
000000 is decremented by 1, the result is
111111. The one-bit register FULL is set to 1
when the stack is full, and the one-bit register
EMTY is set to 1 when the stack is empty of
items.
DR is the data register that holds the binary data to be written into or read out of the stack. Initially, SP is
cleared to 0, EMTY is set to 1, and FULL is cleared to 0, so that SP points to the word at address 0 and the
stack is marked empty and not full. If the stack is not full (if FULL = 0), a new item is inserted with a push
operation. The push operation is implemented with the following sequence of micro-operations;

 SP ← SP + 1 Increment stack pointer

 M[SP] ← DR Write item on top of the stack
 If (SP = 0) then (FULL ←1) Check if stack is full
 EMTY ← 0 Mark the stack not empty
Since SP has only six bits, it cannot exceed a number greater than 63 (111111 in binary). When 63 is
incremented by 1, the result is 0 since 111111 + 1 = 1000000 in binary, but SP can accommodate only the
six least significant bits.
4.8. Characteristics of RISC and CISC
RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set Computing) are two different
approaches to designing the instruction set of a CPU (Central Processing Unit). RISC processors are
characterized by having a small, highly optimized instruction set. This means they have a smaller number
of instructions that they can execute, but each of these instructions is designed to be very fast and
efficient. CISC processors are characterized by a larger and more complex instruction set.

CPU of a computer that commonly uses CISC processors

CPU of a mobile phone that commonly uses RISC processors
RISC and CISC processors operate differently. In a RISC-based system, the CPU is designed to execute a
small number of highly optimized instructions quickly and efficiently. This is achieved by simplifying the
processor's architecture and reducing the number of transistors it contains. RISC processors have a simple,
fixed-length instruction set and a small number of registers (high-speed memory locations) that store data.
To execute an instruction, the processor retrieves the instruction from memory and decodes it to
determine what operation it specifies.

In a CISC-based system, the CPU is designed to execute a larger and more complex instruction set that can
handle a wider range of tasks. This is achieved by including more transistors and a more complex
architecture in the processor. The CISC processor architecture has a variable-length instruction set and a
larger number of registers than RISC processors. To execute an instruction, the processor retrieves the
instruction from memory and decodes it to determine what operation it specifies. It may also need to
fetch additional data from memory to complete the operation. The results are stored back in the memory
once the operation has been performed.