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Three-State Gates

 A multiplexer can be constructed with three-state gates—digital circuits that exhibit three
states.
 Two of the states are signals equivalent to logic 1 and logic 0 as in a conventional gate.
 The third state is a high-impedance state in which (1) the logic behaves like an open circuit,
which means that the output appears to be disconnected, (2) the circuit has no logic
significance, and (3) the circuit connected to the output of the three-state gate is not affected
by the inputs to the gate.
 Three-state gates may perform any conventional logic, such as AND or NAND. However,
the one most commonly used is the buffer gate.

 The graphic symbol for a three-state buffer gate is shown in Fig. 4.29 . It is distinguished
from a normal buffer by an input control line entering the bottom of the symbol.
 The buffer has a normal input, an output, and a control input that determines the state of the
output. When the control input is equal to 1, the output is enabled and the gate behaves like a
conventional buffer, with the output equal to the normal [Link] the control input is 0,
the output is disabled and the gate goes to a high-impedance state, regardless of the value in
the normal input.
 The high-impedance state of a three-state gate provides a special feature not available in
other gates. Because of this feature, a large number of three-state gate outputs can be
connected with wires to form a common line without endangering loading effects.

 The construction of multiplexers with three-state buffers is demonstrated in Fig. 4.30 .

 Figure 4.30(a) shows the construction of a two-to-one-line multiplexer with 2 three-state
buffers and an inverter. The two outputs are connected together to form a single output line.
 When the select input is 0, the upper buffer is enabled by its control input and the lower
buffer is disabled. Output Y is then equal to input A . When the select input is 1, the lower
buffer is enabled and Y is equal to B . The construction of a four-to-one-line multiplexer is
shown in Fig. 4.30(b) .
 The outputs of 4 three-state buffers are connected together to form a single output line.
 The control inputs to the buffers determine which one of the four normal inputs I0 throughI3
will be connected to the output line. No more than one buffer may be in the active state at
any given time

SEQUENTIALCIRCUITS

 A block diagram of a sequential circuit is shown in Fig. 5.1 . It consists of a combinational

circuit to which storage elements are connected to form a feedback path.
 The storage elements are devices capable of storing binary information. The binary
information stored in these elements at any given time defines the state of the sequential
circuit at that time.
 The sequential circuit receives binary information from external inputs that, together with
the present state of the storage elements, determine the binary value of the outputs
 The block diagram demonstrates that the outputs in a sequential circuit are a function not
only of the inputs, but also of the present state of the storage elements.
 The next state of the storage elements is also a function of external inputs and the present
state. Thus, a sequential circuit is specified by a time sequence of inputs, outputs, and
internal states . In contrast, the outputs of combinational logic depend only on the present
values of the inputs.

 The block diagram of a synchronous clocked sequential circuit is shown in Fig. 5.2 . The
outputs are formed by a combinational logic function of the inputs to the circuit or the values
stored in the flip-flops (or both).
 The value that is stored in a flip-flop when the clock pulse occurs is also determined by the
inputs to the circuit or the values presently stored in the flip-flop (or both).
 The new value is stored (i.e., the flip-flop is updated) when a pulse of the clock signal
occurs. Prior to the occurrence of the clock pulse, the combinational logic forming the next
value of the flip-flop must have reached a stable value. Consequently, the speed at which the
combinational logic circuits operate is critical.
 If the clock (synchronizing) pulses arrive at a regular interval, as shown in the timing
diagram in Fig. 5.2 , the combinational logic must respond to a change in the state of the
flip-flop in time to be updated before the next pulse arrives.
 Propagation delays play an important role in determining the minimum interval between
clock pulses that will allow the circuit to operate correctly. A change in state of the flip-flops
is initiated only by a clock pulse transition

S T O R A G E E L E M E N T S : L AT C H E S

 A storage element in a digital circuit can maintain a binary state indefinitely (as long as
power is delivered to the circuit), until directed by an input signal to switch states.
 The major differences among various types of storage elements are in the number of inputs
they possess and in the manner in which the inputs affect the binary state.
 Storage elements that operate with signal levels (rather than signal transitions) are referred to
as latches ; those controlled by a clock transition are flip-flops. Latches are said to be level
sensitive devices; flip-flops are edge-sensitive devices. The two types of storage elements
are related because latches are the basic circuits from which all flip-flops are constructed.
SR Latch

 The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND
gates, and two inputs labeled S for set and R for reset.
 The SR latch constructed with two cross-coupled NOR gates is shown in Fig. 5.3 .
 The latch has two useful states. When output Q = 1 and Q = 0, the latch is said to be in the
set state .
 When Q = 0 and Q = 1, it is in the reset state . Outputs Q and Q are normally the
complement of each other. However, when both inputs are equal to 1 at the same time, a
condition in which both outputs are equal to 0 (rather than be mutually complementary)
occurs. If both inputs are then switched to 0 simultaneously, the device will enter an
unpredictable or undefined state or a metastable state. Consequently, in practical
applications, setting both inputs to 1 is forbidden.

 The SR latch with two cross-coupled NAND gates is shown in Fig. 5.4 . It operates with
both inputs normally at 1, unless the state of the latch has to be changed.
 The application of 0 to the S input causes output Q to go to 1, putting the latch in the set
state. When the S input goes back to 1, the circuit remains in the set state.
 After both inputs go back to 1, we are allowed to change the state of the latch by placing a 0
in the R input. This action causes the circuit to go to the reset state and stay there even after
both inputs return to 1.
 The condition that is forbidden for the NAND latch is both inputs being equal to 0 at the
same time, an input combination that should be avoided.
 In comparing the NAND with the NOR latch, note that the input signals for the NAND
require the complement of those values used for the NOR latch. Because the NAND latch
requires a 0 signal to change its state, it is sometimes referred to as an S R latch.
 The primes (or, sometimes, bars over the letters) designate the fact that the inputs must be in
their complement form to activate the circuit.

 The operation of the basic SR latch can be modified by providing an additional input signal
that determines (controls) when the state of the latch can be changed by determining whether
S and R (or S and R ) can affect the circuit.
 An SR latch with a control input is shown in Fig. 5.5 . It consists of the basic SR latch and
two additional NAND gates.
 The control input En acts as an enable signal for the other two inputs. The outputs of the
NAND gates stay at the logic-1 level as long as the enable signal remains at 0.
 This is the quiescent condition for the SR latch. When the enable input goes to 1,
information from the S or R input is allowed to affect the latch.
 The set state is reached with S = 1, R = 0, and En = 1(active-high enabled). To change to the
reset state, the inputs must be S = 0, R = 1, and En = 1. In either case, when En returns to 0,
the circuit remains in its current state.
 The control input disables the circuit by applying 0 to En, so that the state of the output does
not change regardless of the values of S and R . Moreover, when En = 1 and both the S and
R inputs are equal to 0, the state of the circuit does not change. These conditions are listed in
the function table accompanying the diagram.

D Latch (Transparent Latch)

 One way to eliminate the undesirable condition of the indeterminate state in the SR latch is
to ensure that inputs S and R are never equal to 1 at the same time. This is done in the D
latch, shown in Fig. 5.6 .
 This latch has only two inputs: D (data) and En (enable). The D input goes directly to the S
input, and its complement is applied to the R input. As long as the enable input is at 0, the
cross-coupled SR latch has both inputs at the 1 level and the circuit cannot change state
regardless of the value of D .
 The D input is sampled when En = 1. If D = 1, the Q output goes to 1, placing the circuit in
the set state. If D = 0, output Q goes to 0, placing the circuit in the reset state.

 The graphic symbols for the various latches are shown in Fig. 5.7 . A latch is designated by a
rectangular block with inputs on the left and outputs on the right. One output designates the
normal output, and the other (with the bubble designation) designates the complement
output.
 The graphic symbol for the SR latch has inputs S and R indicated inside the block. In the
case of a NAND gate latch, bubbles are added to the inputs to indicate that setting and
resetting occur with a logic-0 signal.
 The graphic symbol for the D latch has inputs D and En indicated inside the block.

STORAGEELEMENTS:FLIP-FLOPS

 The state of a latch or flip-flop is switched by a change in the control input. This momentary
change is called a trigger, and the transition it causes is said to trigger the flip-flop.
 The D latch with pulses in its control input is essentially a flip-flop that is triggered every
time the pulse goes to the logic-1 level. As long as the pulse input remains at this level, any
changes in the data input will change the output and the state of the latch.

 As seen from the block diagram of Fig. 5.2 , a sequential circuit has a feedback path from
the outputs of the flip-flops to the input of the combinational circuit.
 Consequently, the inputs of the flip-flops are derived in part from the outputs of the same
and other flip-flops. When latches are used for the storage elements, a serious difficulty
arises.
 The state transitions of the latches start as soon as the clock pulse changes to the logic-1
level.
 Flip-flop circuits are constructed in such a way as to make them operate properly when they
are part of a sequential circuit that employs a common clock.
 The problem with the latch is that it responds to a change in the level of a clock pulse. As
shown in Fig. 5.8 (a), a positive level response in the enable input allows changes in the
output when the D input changes while the clock pulse stays at logic 1.
 The key to the proper operation of a flip-flop is to trigger it only during a signal transition .
This can be accomplished by eliminating the feedback path that is inherent in the operation
of the sequential circuit using latches.
 A clock pulse goes through two transitions: from 0 to 1 and the return from 1 to 0. As shown
in Fig. 5.8 , the positive transition is defined as the positive edge and the negative transition
as the negative edge.

Edge-Triggered D Flip-Flop

 The construction of a D flip-flop with two D latches and an inverter is shown in Fig. 5.9 .
The first latch is called the master and the second the slave.
 The circuit samples the D input and changes its output Q only at the negative edge of the
synchronizing or controlling clock (designated as Clk ).
 When the clock is 0, the output of the inverter is 1. The slave latch is enabled, and its output
Q is equal to the master output Y .
 The behavior of the master–slave flip-flop just described dictates that (1) the output may
change only once, (2) a change in the output is triggered by the negative edge of the clock,
and (3) the change may occur only during the clock’s negative level.
 The value that is produced at the output of the flip-flop is the value that was stored in the
master stage immediately before the negative edge occurred
 Another construction of an edge-triggered D flip-flop uses three SR latches as shown in Fig.
5.10 . Two latches respond to the external D (data) and Clk (clock) inputs.
 The third latch provides the outputs for the flip-flop. The S and R inputs of the output
latchare maintained at the logic-1 level when Clk = 0.
 This causes the output to remain in its present state. Input D may be equal to 0 or 1. If D = 0
when Clk becomes 1, R changes to 0.
 This causes the flip-flop to go to the reset state, making Q = 0. If there is a change in the D
input while Clk = 1, terminal R remains at 0 because Q is 0.
 Thus, the flip-flop is locked out and is unresponsive to further changes in the input. When
the clock returns to 0, R goes to 1, placing the output latch in the quiescent condition without
changing the output. Similarly, if D = 1 when Clk goes from 0 to 1, S changes to 0.
 This causes the circuit to go to the set state, making Q = 1. Any change in D while Clk = 1
does not affect the [Link] timing of the response of a flip-flop to input data and to the
clock must be taken into consideration when one is using edge-triggered flip-flops.
 There is a minimum time called the setup time during which the D input must be maintained
at a constant value prior to the occurrence of the clock transition.

Other Flip-Flops

 Very large-scale integration circuits contain several thousands of gates within one package.
Circuits are constructed by interconnecting the various gates to provide a digital system.
Each flip-flop is constructed from an interconnection of gates.
 The most economical and efficient flip-flop constructed in this manner is the edge-triggered
D flipflop, because it requires the smallest number of gates.
 Other types of flip-flops can be constructed by using the D flip-flop and external logic. Two
flip-flops less widely used in the design of digital systems are the JK and T flip-flops.
 There are three operations that can be performed with a flip-flop: Set it to 1, reset it to 0, or
complement its output.
 With only a single input, the D flip-flop can set or reset the output, depending on the value
of the D input immediately before the clock transition. Synchronized by a clock signal, the
JK flip-flop has two inputs and performs all three operations.
 The circuit diagram of a JK flip-flop constructed with a D flip-flop and gates is shown in
Fig. 5.12 (a). The J input sets the flip-flop to 1, the K input resets it to 0, and when both
inputs are enabled, the output is complemented. This can be verified by investigating the
circuit applied to the D input:
 D=JQ’+K’Q
 When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1. When J =
0 and K = 1, D = 0, so the next clock edge resets the output to 0.
 When both J = K = 1 and D = Q’ , the next clock edge complements the output. When both
J = K = 0 and D = Q, the clock edge leaves the output unchanged.
 The graphic symbol for the JK flip-flop is shown in Fig. 5.12 (b). It is similar to the graphic
symbol of the D flip-flop, except that now the inputs are marked J and K .
 The T (toggle) flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop
when inputs J and K are tied together. This is shown in Fig. 5.13 (a).
 When The T flip-flop can be constructed with a D flip-flop and an exclusive-OR gate as
shown in Fig. 5.13 (b).

 The T flip-flop can be constructed with a D flip-flop and an exclusive-OR gate as shown in
Fig. 5.13 (b). The expression for the D input is D = T { Q = TQ’ + T’ Q When T = 0, D = Q
and there is no change in the output. When T = 1, D = Q and
the output complements. The graphic symbol for this flip-flop has a T symbol in the input.
Characteristic Tables

 A characteristic table defines the logical properties of a flip-flop by describing its operation
in tabular form. The characteristic tables of three types of flip-flops are presented in Table
5.1 .

 They define the next state (i.e., the state that results from a clock transition) as a function of
the inputs and the present state. Q ( t ) refers to the present state Q(t + 1) is the next state one
clock period later. Note that the clock edge input is not included in the characteristic table,
but is implied to occur between times t and t + 1.

 Thus, Q(t) denotes the state of the flip-flop immediately before the clock edge, and Q(t + 1)
denotes the state that results from the clock transition.
Characteristic Equations

 The logical properties of a flip-flop, as described in the characteristic table, can be expressed
algebraically with a characteristic equation. For the D flip-flop, we have the characteristic
equation

Q(t + 1) = D

 which states that the next state of the output will be equal to the value of input D in the
present state. The characteristic equation for the JK flip-flop can be derived from the
characteristic table or from the circuit of Fig. 5.12 .

 We obtain Q(t + 1) = JQ’ + K’ Q where Q is the value of the flip-flop output prior to the
application of a clock edge. The characteristic equation for the T flip-flop is obtained from
the circuit of Fig. 5.13 :

Q(t + 1) = T { Q = TQ’ + T’ Q

Direct Inputs

 Some flip-flops have asynchronous inputs that are used to force the flip-flop to a particular
state independently of the clock. The input that sets the flip-flop to 1 is called presetor direct
set .
 The input that clears the flip-flop to 0 is called clear or direct reset . When power is turned
on in a digital system, the state of the flip-flops is unknown.

 The direct inputs are useful for bringing all flip-flops in the system to a known starting state
prior to the clocked operation.

 A positive-edge-triggered D flip-flop with active-low asynchronous reset is shown in Fig.

5.14 .
 The circuit diagram is the same as the one in Fig. 5.10 , except for the additional reset input
connections to three NAND gates.

 When the reset input is 0, it forces output Q’ to stay at 1, which, in turn, clears output Q to 0,
thus resetting the flip-flop.

 Two other connections from the reset input ensure that the S input of the third SR latch stays
at logic 1 while the reset input is at 0, regardless of the values of D and Clk .

 The graphic symbol for the D flip-flop with a direct reset has an additional input marked
with R . The bubble along the input indicates that the reset is active at the logic-0 level. Flip-
flops with a direct set use the symbol S for the asynchronous set input.

 The function table specifies the operation of the circuit. When R = 0, the output is reset to 0.
This state is independent of the values of D or Clk .

 Normal clock operation can proceed only after the reset input goes to logic 1.

 The clock at Clk is shown with an upward arrow to indicate that the flip-flop triggers on the
positive edge of the clock. The value in D is transferred to Q with every positive-edge clock
signal, provided that R = 1.