SN65HVD10, SN65HVD10Q, SN75HVD10

SN65HVD11, SN65HVD11Q, SN75HVD11

SN65HVD12, SN75HVD12
[Link] .......................................................................................................................................... SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009

3.3-V RS-485 TRANSCEIVERS

1FEATURES
• Operates With a 3.3-V Supply DESCRIPTION
• Bus-Pin ESD Protection Exceeds 16 kV HBM The SN65HVD10, SN75HVD10, SN65HVD11,
• 1/8 Unit-Load Option Available (Up to 256 SN75HVD11, SN65HVD12, and SN75HVD12
Nodes on the Bus) combine a 3-state differential line driver and
differential input line receiver that operate with a
• Optional Driver Output Transition Times for single 3.3-V power supply. They are designed for
Signaling Rates (1) of 1 Mbps, 10 Mbps, and balanced transmission lines and meet or exceed
32 Mbps ANSI standard TIA/EIA-485-A and ISO 8482:1993.
• Meets or Exceeds the Requirements of ANSI These differential bus transceivers are monolithic
TIA/EIA-485-A integrated circuits designed for bidirectional data
communication on multipoint bus-transmission lines.
• Bus-Pin Short Circuit Protection From –7 V to The drivers and receivers have active-high and
12 V active-low enables respectively, that can be externally
• Low-Current Standby Mode . . . 1 µA Typical connected together to function as direction control.
• Open-Circuit, Idle-Bus, and Shorted-Bus Very low device standby supply current can be
Failsafe Receiver achieved by disabling the driver and the receiver.
• Thermal Shutdown Protection The driver differential outputs and receiver differential
inputs connect internally to form a differential input/
• Glitch-Free Power-Up and Power-Down
output (I/O) bus port that is designed to offer
Protection for Hot-Plugging Applications minimum loading to the bus whenever the driver is
• SN75176 Footprint disabled or VCC = 0. These parts feature wide positive
and negative common-mode voltage ranges, making
APPLICATIONS them suitable for party-line applications.
• Digital Motor Control
D OR P PACKAGE
• Utility Meters (TOP VIEW)
• Chassis-to-Chassis Interconnects
• Electronic Security Stations R 1 8 VCC
• Industrial Process Control RE 2 7 B
• Building Automation DE 3 6 A
D 4 5 GND
• Point-of-Sale (POS) Terminals and Networks

1
R

2
RE

3
DE
6
A
4
(1) The signaling rate of a line is the number of voltage D
transitions that are made per second expressed in the units 7
B
bps (bits per second).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2002–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009 .......................................................................................................................................... [Link]

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION
SIGNALING PACKAGE
UNIT LOADS TA SOIC MARKING
RATE SOIC (1)
PDIP
32 Mbps 1/2 SN65HVD10D SN65HVD10P VP10
10 Mbps 1/8 –40°C to 85°C SN65HVD11D SN65HVD11P VP11
1 Mbps 1/8 SN65HVD12D SN65HVD12P VP12
32 Mbps 1/2 SN75HVD10D SN75HVD10P VN10
10 Mbps 1/8 –0°C to 70°C SN75HVD11D SN75HVD11P VN11
1 Mbps 1/8 SN75HVD12D SN75HVD12P VN12
32 Mbps 1/2 SN65HVD10QD SN65HVD10QP VP10Q
–40°C to 125°C
10 Mbps 1/8 SN65HVD11QD SN65HVD11QP VP11Q

(1) The D package is available taped and reeled. Add an R suffix to the part number (i.e., SN75HVD11DR).

ABSOLUTE MAXIMUM RATINGS

(1) (2)
over operating free-air temperature range unless otherwise noted
UNIT
VCC Supply voltage range –0.3 V to 6 V
Voltage range at A or B –9 V to 14 V
Input voltage range at D, DE, R or RE –0.5 V to VCC + 0.5 V
Voltage input range, transient pulse, A and B, through 100 Ω, see Figure 11 –50 V to 50 V
IO Receiver output current –11 mA to 11 mA
A, B, and GND ±16 kV
Electrostatic Human body model (3)
All pins ±4 kV
discharge
(4)
Charged-device model All pins charge ±1 kV
Continuous total power dissipation See Dissipation Rating Table
Electrical Fast Transient/Burst (5) A, B, and GND ±4 kV
TJ Junction temperature 170°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A and IEC 60749-26.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
(5) Tested in accordance with IEC 61000-4-4.

PACKAGE DISSIPATION RATINGS

PACKAGE TA ≤ 25°C DERATING FACTOR (1) TA = 70°C TA = 85°C TA = 125°C
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING
D (2) 597 mW 4.97 mW/°C 373 mW 298 mW 100 mW
(3)
D 990 mW 8.26 mW/°C 620 mW 496 mW 165 mW
P 1290 mW 10.75 mW/°C 806 mW 645 mW 215 mW

(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
(3) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7.

2 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated

Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11

SN65HVD12, SN75HVD12
 SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
[Link] .......................................................................................................................................... SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range unless otherwise noted
MIN NOM MAX UNIT
VCC Supply voltage 3 3.6
VI or VIC Voltage at any bus terminal (separately or common mode) –7 (1) 12
VIH High-level input voltage D, DE, RE 2 VCC V
VIL Low-level input voltage D, DE, RE 0 0.8
VID Differential input voltage Figure 7 –12 12
Driver –60
IOH High-level output current mA
Receiver –8
Driver 60
IOL Low-level output current mA
Receiver 8
RL Differential load resistance 54 60 Ω
CL Differential load capacitance 50 pF
HVD10 32
Signaling rate HVD11 10 Mbps
HVD12 1
TJ (2) Junction temperature 145 °C

(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) See thermal characteristics table for information regarding this specification.

DRIVER ELECTRICAL CHARACTERISTICS

over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
VIK Input clamp voltage II = –18 mA –1.5 V
IO = 0 2 VCC
|VOD| Differential output voltage (2) RL = 54 Ω, See Figure 1 1.5 V
Vtest = –7 V to 12 V, See Figure 2 1.5
Change in magnitude of differential output
Δ|VOD| See Figure 1 and Figure 2 –0.2 0.2 V
voltage
VOC(PP) Peak-to-peak common-mode output voltage 400 mV
VOC(SS) Steady-state common-mode output voltage 1.4 2.5 V
See Figure 3
Change in steady-state common-mode output –0.0
ΔVOC(SS) 0.05 V
voltage 5
IOZ High-impedance output current See receiver input currents
D –100 0
II Input current µA
DE 0 100
IOS Short-circuit output current –7 V ≤ VO ≤ 12 V –250 250 mA
C(OD) Differential output capacitance VOD = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 16 pF
RE at VCC,
Receiver disabled and
D & DE at VCC, 9 15.5 mA
driver enabled
No load
RE at VCC,
D at VCC, Receiver disabled and
ICC Supply current 1 5 µA
DE at 0 V, driver disabled (standby)
No load
RE at 0 V,
Receiver enabled and
D & DE at VCC, 9 15.5 mA
driver enabled
No load

(1) All typical values are at 25°C and with a 3.3-V supply.
(2) For TA > 85°C, VCC is ±5%.

Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009 .......................................................................................................................................... [Link]

DRIVER SWITCHING CHARACTERISTICS

over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
HVD10 5 8.5 16
tPLH Propagation delay time, low-to-high-level output HVD11 18 25 40 ns
HVD12 135 200 300
HVD10 5 8.5 16
tPHL Propagation delay time, high-to-low-level output HVD11 18 25 40 ns
HVD12 135 200 300
HVD10 3 4.5 10
RL = 54 Ω, CL = 50 pF,
tr Differential output signal rise time HVD11 10 20 30 ns
See Figure 4
HVD12 100 170 300
HVD10 3 4.5 10
tf Differential output signal fall time HVD11 10 20 30 ns
HVD12 100 170 300
HVD10 1.5
tsk(p) Pulse skew (|tPHL – tPLH|) HVD11 2.5 ns
HVD12 7
HVD10 6
tsk(pp) (2) Part-to-part skew HVD11 11 ns
HVD12 100
HVD10 31
Propagation delay time,
tPZH HVD11 55 ns
high-impedance-to-high-level output
HVD12 RL = 110 Ω, RE at 0 V, 300
HVD10 See Figure 5 25
Propagation delay time,
tPHZ HVD11 55 ns
high-level-to-high-impedance output
HVD12 300
HVD10 26
Propagation delay time,
tPZL HVD11 55 ns
high-impedance-to-low-level output
HVD12 RL = 110 Ω, RE at 0 V, 300
HVD10 See Figure 6 26
Propagation delay time,
tPLZ HVD11 75 ns
low-level-to-high-impedance output
HVD12 400
RL = 110 Ω, RE at 3 V,
tPZH Propagation delay time, standby-to-high-level output 6 µs
See Figure 5
RL = 110 Ω, RE at 3 V,
tPZL Propagation delay time, standby-to-low-level output 6 µs
See Figure 6

(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

4 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated

Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11

SN65HVD12, SN75HVD12
 SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
[Link] .......................................................................................................................................... SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009

RECEIVER ELECTRICAL CHARACTERISTICS

over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
VIT+ Positive-going input threshold voltage IO = –8 mA -0.01
Negative-going input threshold V
VIT– IO = 8 mA –0.2
voltage
Vhys Hysteresis voltage (VIT+ - VIT-) 35 mV
VIK Enable-input clamp voltage II = –18 mA –1.5 V
VOH High-level output voltage VID = 200 mV, IOH = –8 mA, See Figure 7 2.4 V
VOL Low-level output voltage VID = –200 mV, IOL = 8 mA, See Figure 7 0.4 V
IOZ High-impedance-state output current VO = 0 or VCC RE at VCC –1 1 µA
VA or VB = 12 V 0.05 0.11
VA or VB = 12 V, VCC = 0 V HVD11, HVD12, 0.06 0.13
mA
VA or VB = –7 V Other input at 0 V –0.1 –0.05
VA or VB = –7 V, VCC = 0 V –0.05 –0.04
II Bus input current
VA or VB = 12 V 0.2 0.5
VA or VB = 12 V, VCC = 0 V HVD10, 0.25 0.5
mA
VA or VB = –7 V Other input at 0 V –0.4 –0.2
VA or VB = –7 V, VCC = 0 V –0.4 –0.15
IIH High-level input current, RE VIH = 2 V –30 0 µA
IIL Low-level input current, RE VIL = 0.8 V –30 0 µA
CID Differential input capacitance VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 15 pF
RE at 0 V,
Receiver enabled and driver
D & DE at 0 V, 4 8 mA
disabled
No load
RE at VCC,
D at VCC, Receiver disabled and driver
ICC Supply current 1 5 µA
DE at 0 V, disabled (standby)
No load
RE at 0 V,
Receiver enabled and driver
D & DE at VCC, 9 15.5 mA
enabled
No load

(1) All typical values are at 25°C and with a 3.3-V supply.

Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009 .......................................................................................................................................... [Link]

RECEIVER SWITCHING CHARACTERISTICS

over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
tPLH Propagation delay time, low-to-high-level output HVD10 12.5 20 25
ns
tPHL Propagation delay time, high-to-low-level output HVD10 12.5 20 25
HVD11
tPLH Propagation delay time, low-to-high-level output 30 55 70 ns
HVD12
VID = –1.5 V to 1.5 V,
HVD11 CL = 15 pF,
tPHL Propagation delay time, high-to-low-level output 30 55 70 ns
HVD12 See Figure 8
HVD10 1.5
tsk(p) Pulse skew (|tPHL – tPLH|) HVD11 4 ns
HVD12 4
HVD10 8
tsk(pp) (2) Part-to-part skew HVD11 15 ns
HVD12 15
tr Output signal rise time CL = 15 pF, 1 2 5
ns
tf Output signal fall time See Figure 8 1 2 5
tPZH (1) Output enable time to high level 15
(1)
tPZL Output enable time to low level CL = 15 pF, DE at 3 V, 15
ns
tPHZ Output disable time from high level See Figure 9 20
tPLZ Output disable time from low level 15
tPZH (2) Propagation delay time, standby-to-high-level output CL = 15 pF, DE at 0, 6
µs
tPZL (2)
Propagation delay time, standby-to-low-level output See Figure 10 6

(1) All typical values are at 25°C and with a 3.3-V supply
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

THERMAL CHARACTERISTICS
(1)
over operating free-air temperature range unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Junction−to−ambient thermal High−K board (3), No airflow D pkg 121
θJA
resistance (2) No airflow (4) P pkg 93
Junction−to−board thermal High−K board D pkg 67
θJB °C/W
resistance See (4)
P pkg 57
Junction−to−case thermal D pkg 41
θJC
resistance P pkg 55
HVD10 198 250
(32 Mbps)
RL= 60 Ω, CL = 50 pF,
DE at VCC, RE at 0 V, HVD11 141 176
PD Device power dissipation mW
Input to D a 50% duty cycle square (10 Mbps)
wave at indicated signaling rate
HVD12 133 161
(500 kbps)
High−K board, No airflow D pkg –40 116
TA Ambient air temperature
No airflow (4) P pkg –40 123 °C
TJSD Thermal shutdown junction temperature 165

(1) See Application Information section for an explanation of these parameters.

(2) The intent of θJA specification is solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
(3) JSD51−7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
(4) JESD51−10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements.

6 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated

Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11

SN65HVD12, SN75HVD12
 SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
[Link] .......................................................................................................................................... SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009

PARAMETER MEASUREMENT INFORMATION

VCC 375 Ω ±1%

VCC
II DE IOA
A DE
A
0 or 3 V VOD 54 Ω ±1% D
0 or 3 V VOD 60 Ω ±1%
B IOB +
B _ −7 V < V(test) < 12 V
VI
375 Ω ±1%
VOB VOA

Figure 1. Driver VOD Test Circuit and Voltage and Figure 2. Driver VOD With Common-Mode Loading Test
Current Definitions Circuit

A VA
VCC
27 Ω ± 1%
DE B VB
A
D VOC(PP)
Input ∆VOC(SS)
27 Ω ± 1%
B VOC
CL = 50 pF ±20% VOC

CL Includes Fixture and

Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50 Ω

Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage

VCC 3V
VI 1.5 V 1.5 V
DE CL = 50 pF ±20%
A
D VOD CL Includes Fixture tPLH tPHL
and Instrumentation ≈2V
Input RL = 54 Ω Capacitance 90% 90%
VI 50 Ω B
Generator ± 1% VOD
0V 0V
10% 10%
≈ –2 V
tr tf

Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω

Figure 4. Driver Switching Test Circuit and Voltage Waveforms

A 3V
D S1
VO VI 1.5 V 1.5 V
3V
B 0V
DE 0.5 V
CL = 50 pF ±20% RL = 110 Ω tPZH
Input ± 1% VOH
Generator VI 50 Ω CL Includes Fixture
and Instrumentation
Capacitance VO 2.3 V
≈0V
tPHZ
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω

Figure 5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms

Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009 .......................................................................................................................................... [Link]

PARAMETER MEASUREMENT INFORMATION (continued)

3V

RL = 110 Ω ≈3V
± 1%
A
S1 VI 1.5 V 1.5 V
D VO
3V
0V
B tPZL tPLZ
DE
Input CL = 50 pF ±20% ≈3V
Generator VI 50 Ω 0.5 V
CL Includes Fixture
and Instrumentation VO 2.3 V
Capacitance VOL

Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω

Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms

IA
A
IO
VA R
VID
B
VB
VIC IB VO
VA + VB
2

Figure 7. Receiver Voltage and Current Definitions

A
R VO
Input
Generator VI 50 Ω B
1.5 V CL = 15 pF ±20%
RE
0V CL Includes Fixture
and Instrumentation
Capacitance

Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω

3V

VI 1.5 V 1.5 V
0V
tPLH tPHL
VOH
90% 90%
VO 1.5 V 1.5 V
10% 10% V
OL
tr tf

Figure 8. Receiver Switching Test Circuit and Voltage Waveforms

8 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated

Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11

SN65HVD12, SN75HVD12
 SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
[Link] .......................................................................................................................................... SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009

PARAMETER MEASUREMENT INFORMATION (continued)

3V 3V

DE A A
R VO 1 kΩ ± 1%
D S1
0 V or 3 V B CL = 15 pF ±20%
RE B
CL Includes Fixture
and Instrumentation
Input Capacitance
Generator VI 50 Ω

Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω

3V
VI
1.5 V 1.5 V
0V
tPZH(1) tPHZ
VOH D at 3 V
VOH –0.5 V
S1 to B
VO 1.5 V
≈0V

tPZL(1) tPLZ
≈3V
D at 0 V
VO 1.5 V S1 to A
VOL +0.5 V
VOL

Figure 9. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled

Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009 .......................................................................................................................................... [Link]

PARAMETER MEASUREMENT INFORMATION (continued)

3V
A A
0 V or 1.5 V R VO 1 kΩ ± 1%
S1
B
1.5 V or 0 V RE CL = 15 pF ±20%
B
CL Includes Fixture
Input and Instrumentation
Capacitance
Generator VI 50 Ω

Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω

3V

VI 1.5 V
0V
tPZH(2)
VOH
A at 1.5 V
VO 1.5 V B at 0 V
S1 to B
GND

tPZL(2)
3V
A at 0 V
B at 1.5 V
VO 1.5 V
S1 to A
VOL

Figure 10. Receiver Enable Time From Standby (Driver Disabled)

0 V or 3 V
RE
A
R
B
100 Ω
± 1%
Pulse Generator,
15 µs Duration, + D
1% Duty Cycle _
tr, tf ≤ 100 ns
DE
3 V or 0 V

NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.

Figure 11. Test Circuit, Transient Over Voltage Test

10 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated

Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11

SN65HVD12, SN75HVD12
 SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
[Link] .......................................................................................................................................... SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009

PARAMETER MEASUREMENT INFORMATION (continued)

FUNCTION TABLES

DRIVER (1)
OUTPUTS
INPUT ENABLE A B
D DE
H H H L
L H L H
X L Z Z
Open H H L

(1) H = high level

L = low level
Z = high impedance
X = irrelevant
? = indeterminate

RECEIVER (1)
DIFFERENTIAL INPUTS ENABLE OUTPUT
VID = VA – VB RE R
VID ≤ –0.2 V L L
–0.2 V < VID < –0.01 V L ?
−0.01 V ≤ VID L H
X H Z
Open Circuit L H
Short circuit L H

(1) H = high level

L = low level
Z = high impedance
X = irrelevant
? = indeterminate

Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009 .......................................................................................................................................... [Link]

EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

D and RE Inputs DE Input

VCC VCC

100 kΩ
1 kΩ 1 kΩ
Input Input

9V 100 kΩ
9V

A Input B Input

VCC VCC

16 V 16 V
R1 R1
R3 R3
Input Input

16 V R2 16 V R2

A and B Outputs R Output

VCC VCC

16 V

5Ω
Output
Output
9V
16 V

R1/R2 R3
SN65HVD10 9 kΩ 45 kΩ
SN65HVD11 36 kΩ 180 kΩ
SN65HVD12 36 kΩ 180 kΩ

12 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated

Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11

SN65HVD12, SN75HVD12
 SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
[Link] .......................................................................................................................................... SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009

TYPICAL CHARACTERISTICS
HVD10 HVD11
RMS SUPPLY CURRENT RMS SUPPLY CURRENT
vs vs
SIGNALING RATE SIGNALING RATE
70 70
TA = 25°C RL = 54 Ω TA = 25°C RL = 54 Ω
RE at VCC CL = 50 pF RE at VCC CL = 50 pF VCC = 3.6 V

I CC − RMS Supply Current − mA

DE at VCC DE at VCC
I CC − RMS Supply Current − mA

60 VCC = 3.6 V 60

50 50
VCC = 3 V
VCC = 3 V

VCC = 3.3 V VCC = 3.3 V

40 40

30 30
0 5 10 15 20 25 30 35 40 0 2.5 5 7.5 10
Signaling Rate − Mbps Signaling Rate − Mbps
Figure 12. Figure 13.

HVD12 HVD10
RMS SUPPLY CURRENT BUS INPUT CURRENT
vs vs
SIGNALING RATE BUS INPUT VOLTAGE
70 300
TA = 25°C RL = 54 Ω TA = 25°C
RE at VCC CL = 50 pF 250 DE at 0 V
DE at VCC
I CC − RMS Supply Current − mA

VCC = 3.6 V 200

I I − Bus Input Current − µ A

60
150 VCC = 0 V
VCC = 3.3 V
100

50 50
VCC = 3 V
VCC = 3.3 V
0
−50
40
−100

−150

30 −200
100 400 700 1000 −7 −6−5 −4−3 −2−1 0 1 2 3 4 5 6 7 8 9 10 11 12
Signaling Rate − kbps VI − Bus Input Voltage − V
Figure 14. Figure 15.

Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009 .......................................................................................................................................... [Link]

TYPICAL CHARACTERISTICS (continued)

HVD11 OR HVD12
BUS INPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
vs vs
BUS INPUT VOLTAGE DRIVER HIGH-LEVEL OUTPUT VOLTAGE
90 150
80 TA = 25°C TA = 25°C

IOH − High-Level Output Current − mA

70 DE at 0 V DE at VCC
100
D at VCC
60 VCC = 3.3 V
I I − Bus Input Current − µ A

50 50
VCC = 0 V
40
30
0
20
10
0 VCC = 3.3 V −50

−10
−20 −100
−30
−40 −150
−50
−60 −200
−7−6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 11 12 −4 −2 0 2 4 6
VI − Bus Input Voltage − V VOH − Driver High-Level Output Voltage − V
Figure 16. Figure 17.

LOW-LEVEL OUTPUT CURRENT DRIVER DIFFERENTIAL OUTPUT

vs vs
DRIVER LOW-LEVEL OUTPUT VOLTAGE FREE-AIR TEMPERATURE
200 2.5

180 TA = 25°C VCC = 3.3 V

DE at VCC 2.4
DE at VCC
I OL − Low-Level Output Current − mA

VOD − Driver Differential Output − V

160 D at 0 V D at VCC
2.3
VCC = 3.3 V
140
2.2
120
2.1
100
2.0
80
1.9
60
1.8
40

20 1.7

0 1.6

−20 1.5
−4 −2 0 2 4 6 8 −40 −15 10 35 60 85
VOL − Driver Low-Level Output Voltage − V TA − Free-Air Temperature − °C
Figure 18. Figure 19.

14 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated

Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11

SN65HVD12, SN75HVD12
 SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
[Link] .......................................................................................................................................... SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009

TYPICAL CHARACTERISTICS (continued)

DRIVER OUTPUT CURRENT ENABLE TIME

vs vs
SUPPLY VOLTAGE COMMON-MODE VOLTAGE (SEE Figure 22)
−40 600
TA = 25°C
DE at VCC
−35
D at VCC 500
I O − Driver Output Current − mA

RL = 54 Ω
−30 HVD12

400

Enable Time − ns
−25
HVD11

−20 300

−15 HVD10
200
−10

100
−5

0 0
0 0.50 1 1.50 2 2.50 3 3.50 -7 -2 3 8 13
VCC − Supply Voltage − V V(TEST) − Common-Mode Voltage − V
Figure 20. Figure 21.
375 W ± 1%

Y -7 V < V(TEST) < 12 V

D VOD 60 W
0 or 3 V ± 1%

Z
DE
375 W ± 1%
Input V 50 W
Generator

50%

tpZH(diff)
VOD (high)
1.5 V

0V

tpZL(diff)
-1.5 V
VOD (low)

Figure 22. Driver Enable Time From DE to VOD

The time tpZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.

Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009 .......................................................................................................................................... [Link]

APPLICATION INFORMATION

RT Stub RT

Device Number of Devices on Bus

HVD10 64
HVD11 256
HVD12 256

NOTE: The line should be terminated at both ends with its characteristic impedance (RT = ZO). Stub lengths off the main line
should be kept as short as possible.

Figure 23. Typical Application Circuit

Driver Input

Driver Output

Receiver Input

Receiver Output

Figure 24. HVD12 Input and Output Through 2000 Feet of Cable

length of Commscope 5524 category 5e+ twisted pair

An example application for the HVD12 is illustrated in cable. The bus is terminated at each end by a 100-Ω
Figure 23. Two HVD12 transceivers are used to resistor, matching the cable characteristic impedance.
communicate data through a 2000 foot (600 m) Figure 24 illustrates operation at a signaling rate of
250 kbps.

16 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated

Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11

SN65HVD12, SN75HVD12
 SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
[Link] .......................................................................................................................................... SLLS505J – FEBRUARY 2002 – REVISED FEBRUARY 2009

THERMAL CHARACTERISTICS OF IC θJC (Junction-to-Case Thermal Resistance) is

PACKAGES defined as difference in junction temperature to case
divided by the operating power. It is measured by
θJA (Junction-to-Ambient Thermal Resistance) is putting the mounted package up against a copper
defined as the difference in junction temperature to block cold plate to force heat to flow from die, through
ambient temperature divided by the operating power. the mold compound into the copper block.
θJA is not a constant and is a strong function of: θJC is a useful thermal characteristic when a heatsink
• the PCB design (50% variation) is applied to package. It is not a useful characteristic
• altitude (20% variation) to predict junction temperature because it provides
• device power (5% variation) pessimistic numbers if the case temperature is
measured in a nonstandard system and junction
θJA can be used to compare the thermal performance temperatures are backed out. It can be used with θJB
of packages if the specific test conditions are defined in 1-dimensional thermal simulation of a package
and used. Standardized testing includes specification system.
of PCB construction, test chamber volume, sensor
locations, and the thermal characteristics of holding θJB (Junction-to-Board Thermal Resistance) is
fixtures. θJA is often misused when it is used to defined as the difference in the junction temperature
calculate junction temperatures for other installations. and the PCB temperature at the center of the
package (closest to the die) when the PCB is
TI uses two test PCBs as defined by JEDEC clamped in a cold-plate structure. θJB is only defined
specifications. The low-k board gives average in-use for the high-k test card.
condition thermal performance, and it consists of a
single copper trace layer 25 mm long and 2-oz thick. θJB provides an overall thermal resistance between
The high-k board gives best case in-use condition, the die and the PCB. It includes a bit of the PCB
and it consists of two 1-oz buried power planes with a thermal resistance (especially for BGA’s with thermal
single copper trace layer 25 mm long and 2-oz thick. balls) and can be used for simple 1-dimensional
A 4% to 50% difference in θJA can be measured network analysis of package system, see Figure 25.
between these two test cards.

Figure 25. Thermal Resistance

Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
 PACKAGE OPTION ADDENDUM

[Link] 17-Jun-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN65HVD10D OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 85 VP10

SN65HVD10DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP10 Samples

SN65HVD10DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP10 Samples

SN65HVD10P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 65HVD10 Samples

SN65HVD10QDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VP10Q Samples

SN65HVD11DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP11 Samples

SN65HVD11DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP11 Samples

SN65HVD11P LIFEBUY PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 65HVD11
SN65HVD11QDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VP11Q Samples

SN65HVD12DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP12 Samples

SN65HVD12DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP12 Samples

SN65HVD12P LIFEBUY PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 65HVD12
SN75HVD10P NRND PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 75HVD10
SN75HVD12P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 75HVD12 Samples

SN75HVD12PE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 75HVD12 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 17-Jun-2023

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN65HVD10, SN65HVD11, SN65HVD12 :

• Enhanced Product : SN65HVD10-EP, SN65HVD12-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 17-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65HVD10DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD10QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD11DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD11QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD12DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 17-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD10DR SOIC D 8 2500 356.0 356.0 35.0
SN65HVD10QDR SOIC D 8 2500 356.0 356.0 35.0
SN65HVD11DR SOIC D 8 2500 356.0 356.0 35.0
SN65HVD11QDR SOIC D 8 2500 356.0 356.0 35.0
SN65HVD12DR SOIC D 8 2500 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 17-Jun-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN65HVD10P P PDIP 8 50 506 13.97 11230 4.32
SN65HVD11P P PDIP 8 50 506 13.97 11230 4.32
SN65HVD12P P PDIP 8 50 506 13.97 11230 4.32
SN75HVD10P P PDIP 8 50 506 13.97 11230 4.32
SN75HVD12P P PDIP 8 50 506 13.97 11230 4.32
SN75HVD12PE4 P PDIP 8 50 506 13.97 11230 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

[Link]
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
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