Question Paper
Exam Date & Time: 27-Sep-2023 (08:00 AM - 10:00 AM)
MANIPAL ACADEMY OF HIGHER EDUCATION
III SEMESTER [Link] (IT/CCE)
MID SEMESTER EXAMINATIONS, SEP 2023
DIGITAL SYSTEMS AND COMPUTER ORGANIZATION [ICT 2123]
Marks: 30 Duration: 120 mins.
A
Answer all the questions. Section Duration: 20 mins
1) Two 3x8 decoder can be combined to form a (0.5)
16x4 2x16 4x16 2x16
decoder decoder decoder decoder
Correct option is: 3
2) Which of the following is the output "A1, A0" for an encoder with 4 - bits "Y0, Y1, Y2, Y3" as "0001"? (0.5)
00 01 10
11
Correct option is: 4
3) A RS latch is (0.5)
Combinational Synchronous sequential 1-bit memory
1-clock delay element
circuit circuit element
Correct option is: 3
4) Find the output Y of the given circuit (0.5)
1 0 X X'
Correct option is: 2
5) If a multiplier is designed using only full adders, how many full adders are required to design 3 - bit X 2 - bit binary multiplier? (0.5)
3 5 7 9
Correct option is: 4
6) If a MUX is constructed using only 2x1 MUX, how many 2x1 MUXs are used to design 16x1 MUX? (0.5)
15 13 11
9
Correct option is: 1
7) Which of the following is not a self-complimenting code? (0.5)
8421 code Excess 3 code 84-2-1 code 2421 code
Correct option is: 1
8) The equation for "equal to" in 1 - bit magnitude comparator with cascading input ((A>B)in ,(A=B)in, (A< B)in) andA and B as input is: (0.5)
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8) The equation for "equal to" in 1 - bit magnitude comparator with cascading input ((A>B)in ,(A=B)in, (A< B)in) andA and B as input is: (0.5)
(AB' + A'B) (AB + (AB)') (A'B' + (AB)')
(AB' + A'B)' (A=B)in
(A=B)in (A=B)in (A=B)in
Correct option is: 1
9) A 4-bit Carry Look ahead Adder is --------times faster than 4-bit Ripple Carry Adder. (0.5)
2 3 5 8
Correct option is: 2
10) F(a,b) is realized using a 2:1 MUX by connecting 'b' to selection input. F = a, if the selection input is zero. Else F=1. Identify the function F. (0.5)
AND NAND
OR EXOR
Correct option is: 2
B
Answer all the questions.
11) Design single digit BCD adder using 4 - bit binary adders and minimum external gates. (3)
12) Design a code converter using NAND gates only to convert a decimal digit represented in 8 4 2 1 code to a decimal digit represented in 8 4 -2 -1 code. (3)
13) Design 5-to-32-line decoder using only 74138ICs. (3)
14) Implement a Boolean function using 4x1 multiplexer and external gates: (2)
F(A,B,C,D) = (0,3,5,12,14)
Connect the inputs AB to selection lines. The input requirements for the four data lines will be a function of variables C and D.
15) Design a logic circuit to evaluate the arithmetic expression (A2 -B2 ) using Half Adders ONLY. Where A & B are 2-bit binary numbers. (4)
16) Design an arithmetic circuit using 7483ICs and minimum external NAND gates only to perform: (4)
F=4Y when A< B and
F=3Y when A>=B.
Where A,B are 4 - bit binary numbers
Y is a 2 - bit binary number
17) Write the function represented by the logic circuit given. Draw the simplified logic circuit of the logic diagram shown below with the minimum number of basic gates possible. (3)
18) Construct a Full subtractor using 74153IC and minimum external gates. (3)
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Question 14 Design a code converter using NAND gates only to convert a decimal
digit represented in 8 4 2 1 code to a decimal digit represented in 8 4 -2 -1 code.
FCA, B, c,D) 7Co, 3, 5, 12, 14)
2( 1,2.4,6, 7,9, 9, 10, |, 3, 15)
Iokuts
A B D
1
F= c'+ c
1
AB-01
1 1
1 1 AB = 10
1 1
F 1
1 1 1.
1 1
1 1 1. AB = 1I
1 1
1 1 1
|xh
17. Draw the simplified logic circuit of the logic diagram shown below with the minimum
number of logic gates possible.
OR.. Students can use K MAP also to get the final expression, as shown below