Faculty of Electrical and Electronic Engineering
Semiconductor Technology
Dr. Le Viet Thong Email: [Link]@[Link]
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Chapter V : CMOS Logic
Contents:
V.1. Introduction
V.2. CMOS structure
V.3. CMOS Logic
V.3.1. CMOS Inverter
V.3.2. NAND Gate
V.3.3. NOR Gate
V.3.4. CMOS Logic Gate
V.3.5. Compound Gates
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Goals
• Understand the fundamental structure and operation of CMOS logic circuits.
• Distinguish between NMOS and PMOS device behavior in digital
switching.
• Analyze the behavior of basic CMOS gates, including the inverter, NAND, and
NOR.
• Learn the pull-up and pull-down network design methodology for CMOS logic.
• Design combinational logic functions using CMOS technology.
• Evaluate performance parameters such as propagation delay, noise margins,
and power consumption.
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New words
CMOS = Complementary Metal– Công nghệ bán dẫn oxit kim loại bổ
Oxide–Semiconductor sung
Transistor hiệu ứng trường bán dẫn
NMOS = N-type Metal-Oxide- kênh N có cấu trúc kim loại–oxit–bán
Semiconductor transistor) dẫn.
PMOS = P-type Metal-Oxide- Transistor hiệu ứng trường bán dẫn
Semiconductor transistor kênh P có cấu trúc kim loại–oxit–bán
dẫn.
Logic High / Logic Low Mức logic cao / Mức logic thấp
Noise Margin Biên độ nhiễu cho phép
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V.1. Introduction
• Modern integrated circuits rely on logic families that balance performance,
power efficiency, and manufacturing scalability.
• CMOS (Complementary Metal-Oxide-Semiconductor) is a technology for
manufacturing integrated circuits (ICs) that uses complementary pairs of p-
type and n-type MOSFETs.
What is CMOS?
• CMOS = Complementary Metal-Oxide-Semiconductor
• A technology that uses both NMOS and PMOS transistors in a complementary
arrangement.
• Enables very high transistor density and low energy per operation.
• Forms the basis of most modern digital integrated circuits (microprocessors,
memory, ASICs).
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V.1. Introduction
Why CMOS is Important:
• Low static power consumption → only draws significant power during
switching.
• High noise immunity → better tolerance to electrical noise.
• High density → millions to billions of transistors on a single chip.
• Scalable → technology nodes from micrometers to nanometers.
Key Idea:
• When one transistor is ON, the other is OFF → output always strongly
driven to either VDD or GND.
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NMOS vs. PMOS Characteristics
• NMOS: Electrons form the inversion channel; higher mobility → faster switching.
• PMOS: Holes form the inversion channel; lower mobility → slower, wider devices
required for symmetric drive strength.
Threshold Voltage
• NMOS: Turns on when 𝑉𝐺𝑆 > 𝑉𝑇𝑁 .
• PMOS: Turns on when 𝑉𝑆𝐺 >∣𝑉𝑇𝑃∣.
• Typical magnitudes similar, but opposite polarity.
Conduction Behavior
• NMOS pulls down: Efficient at sinking current → strong logic “0” driver.
• PMOS pulls up: Efficient at sourcing current → strong logic “1” driver.
Performance Considerations
• Electron mobility ≈ 2–3× hole mobility → PMOS width is typically increased to balance
rise/fall times in CMOS logic.
• Leakage tends to increase differently between NMOS and PMOS due to bandstructure
asymmetry and doping profiles.
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Why Complementary Pairing Enables Low-Power Logic
Fundamental Principle
• CMOS logic pairs an NMOS pull-down network with a PMOS pull-up network.
• For any static input state, only one transistor conducts, ensuring no direct path from VDD
to ground.
Static Power Suppression
• When the output is logic “1”: PMOS ON, NMOS OFF → no DC current path.
• When the output is logic “0”: NMOS ON, PMOS OFF → again, no DC conduction.
• Static power is therefore dominated only by leakage currents, not bias currents.
Energy Consumption Mechanism
• Power is primarily consumed only during switching, when both devices transition and
charge/discharge the load capacitance.
2
• Dynamic power 𝑃 ≈ 𝛼𝐶𝐿 𝑉𝐷𝐷 𝑓 - directly tied to activity factor and voltage scaling.
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Why Complementary Pairing Enables Low-Power Logic (cont.)
Noise Immunity & Signal Integrity
• Complementary operation produces full logic swings (0 → VDD).
• Results in robust noise margins and predictable switching thresholds.
Consequences for VLSI
• Enables ultra-dense integration without prohibitive thermal loads.
• Supports high-frequency digital logic with manageable power budgets.
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NMOS vs. PMOS Inverters
NMOS Inverter PMOS Inverter
•NMOS Inverter: Input high pulls the output low; when the input is low, the pull-up load drives the output high.
•PMOS Inverter: Input low turns the PMOS on, pulling the output high; input high switches it off, allowing the
output to fall.
•Both NMOS and PMOS inverters require a load device, causing static power consumption.
•Output levels are not truly rail-to-rail due to threshold-voltage loss.
•Switching speed is limited by the resistive load.
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MOSFET-Based Switches: NMOS, Transmission Gate, and CMOS Switch
• NMOS Switch: Simple, gate-controlled switch; suffers from Vth drop when passing logic “1”.
• Transmission Gate: Parallel NMOS–PMOS pair with complementary control; enables near rail-to-rail, bidirectional
signal transfer.
• CMOS Switch: Complementary MOS configuration; low leakage, improved linearity, and robust switching for
digital/analog applications.
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NMOS, PMOS, and CMOS: Device Overview
• NMOS and PMOS operate with opposite gate–voltage
polarity, giving complementary conduction behavior.
• Their I–V characteristics follow the same three
modes: cut-off, linear, and saturation, governed by
threshold voltage and drain–source bias.
• Combining NMOS and PMOS in CMOS enables
complementary switching, low static power, and full-
swing logic levels.
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CMOS Inverter
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V.2. CMOS structure
• A CMOS structure primarily consists of two types of transistors: NMOS (and
PMOS, built on either a p-type or n-type substrate.
• These transistors are strategically paired to form logic gates, with NMOS
transistors acting as pull-down networks and PMOS transistors as pull-up
networks.
• A thin layer of silicon dioxide (SiO2) acts as an insulator between the gate and
the semiconductor, and a metallic or polysilicon gate controls current flow.
Cross section of two transistors in a CMOS gate, in an n-well CMOS process CMOS inverter (a NOT logic gate)
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Comparison of n-well and p-well CMOS region
Feature n-well CMOS p-well CMOS
Substrate type p-type n-type
Well type n-well p-well
pMOS location Inside n-well Directly in substrate
nMOS location Directly in p-substrate Inside p-well
Body Bias Flexibility Higher for PMOS Higher for NMOS
Typical Mobility NMOS (in p-substrate) None inherent; depends on
Advantage tuning
Advantages Compatible with NMOS processes, Lower junction capacitance for
better noise isolation PMOS
Disadvantages Higher body effect for PMOS Requires additional processing for
NMOS
Historical Adoption Earlier mainstream Less dominant
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V.2. CMOS structure
Operation Principle:
•Input = Low (0): PMOS ON → Output = High (VDD)
•Input = High (1): NMOS ON → Output = Low (GND)
•Only one transistor conducts at a time → nearly zero static power consumption.
Advantages:
•High input impedance.
•Rail-to-rail output swing.
•High noise margin.
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V.3. CMOS inverter
• CMOS inverter definition is a device that is used to generate logic
functions is known as CMOS inverter and is the essential component in all
integrated circuits
CMOS Inverter Schematic Diagram
CMOS Inverter Symbol & Truth Table and circuit
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V.3.1 CMOS inverter
CMOS Inverter Operation & Working
Output
Input (Vin) PMOS NMOS
(Vout)
Low (0) ON OFF High (1)
High (1) OFF ON Low (0)
•When the input is 0 (Low):
•PMOS conducts, NMOS is off.
•Output is pulled up to VDD → logic 1
•When the input is 1 (High):
•NMOS conducts, PMOS is off.
•Output is pulled down to GND → logic 0
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CMOS Inverter Characteristics
Voltage Transfer Characteristics (VTC) of CMOS inverter
Region I — PMOS On, NMOS Off (Input Low)
• 𝑉𝐼𝑁<𝑉𝑇𝑁
• Output is held near VDD.
• Slope is nearly zero → strong logic “1”.
Region II (region 3)— Transition Region (Both Partially Conducting)
• 𝑉𝑇𝑁 < 𝑉𝐼𝑁 < 𝑉𝐷𝐷− ∣𝑉𝑇𝑃∣
• Both transistors conduct; output drops rapidly.
• Steep slope indicates high gain → essential for noise rejection.
Region III (region 5)— PMOS Off, NMOS On (Input High)
• 𝑉𝐼𝑁 > 𝑉𝐷𝐷 − ∣𝑉𝑇𝑃∣
• Output driven close to ground.
• Strong logic “0”.
Switching Threshold 𝑉𝑀
• Defined where 𝐼𝐷𝑁𝑀𝑂𝑆=𝐼𝐷𝑃𝑀𝑂𝑆 .
• Ideally positioned near 𝑉𝐷𝐷/2 for symmetric noise margins.
• Adjusted through PMOS/NMOS sizing (PMOS typically wider).
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CMOS Fabrication and Layout
Inverter cross-section with well and substrate contacts.
•CMOS inverter uses nMOS in p-substrate and pMOS in an n-well.
•Well and substrate taps tie body terminals to GND and VDD.
•Six masks define the process: n-well, polysilicon, n+, p+, contacts, metal.
•Layout shows alignment of wells, gates, diffusions, and interconnects.
•Contacts link diffusion/poly to metal; metal completes circuit routing.
Inverter mask set
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Example of n well fabrication Process
•Begin with a clean p-type silicon substrate.
•Grow a thin SiO₂ layer on the surface.
•Apply and pattern photoresist to open the n-well region.
•Etch exposed oxide to create an opening for
implantation.
•Perform n-type ion implantation (e.g., phosphorus or
arsenic).
•Remove photoresist and anneal to drive-in dopants.
•Result: a formed n-well with proper depth and lateral
spread.
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Process Steps for Polysilicon Gate Patterning and n⁺ Diffusion
•Grow thin gate oxide and deposit polysilicon over
the wafer.
•Pattern and etch polysilicon to form transistor gates.
•Deposit oxide and pattern openings for n⁺ diffusion
regions.
•Perform n-type ion implantation aligned to the
polysilicon gates (self-aligned process).
•Anneal to activate dopants and form n⁺ source/drain
regions.
•Remove oxide as needed, leaving completed gate
and n⁺ diffusion structures.
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Process Steps for p⁺ Diffusion, Contacts, and Metal
•Pattern oxide openings and implant p⁺
dopants to form source/drain regions in
the n-well.
•Deposit thick field oxide and open
windows for contacts.
•Deposit metal layer over the wafer and
pattern it to form interconnects.
•Completed structure includes p⁺/n⁺
regions, contact holes, and metal
routing lines.
Cross-sections while manufacturing p-diffusion, contacts, and metal
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Layout Design Rules
❖Layout design rules define the minimum feature sizes and the minimum spacing required
to ensure reliable fabrication in a given CMOS process.
❖The parameter λ (lambda) is typically defined as half of the minimum channel length of
the process and is used to express scalable design rules.
• Metal and diffusion layers have a
minimum width = 4λ and minimum
spacing = 4λ.
• Contacts are 2λ × 2λ and must be
enclosed by ≥ 1λ overlap in both the
upper (metal) and lower (diffusion or
polysilicon) layers.
• Polysilicon wires use a minimum width =
2λ, with typical spacing of 2–3λ
depending on the process.
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V.3.2 CMOS NAND Gate
NAND = Not-AND = AND followed by Inverter
Truth table
Symbol
X = NAND(A, B)
Timing chart
• When both A and B are high, output is low.
• When either A or B is low, output is high.
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Circuit of NAND
• Pull-Up Network (PUN): Two PMOS transistors in parallel,
connecting output to VDD
• Pull-Down Network (PDN): Two NMOS transistors in series,
connecting output to GND.
• Inputs A and B control both PUN and PDN through the
transistor gates.
Device-Level Interpretation
• A or B = 0:
PMOS ON, at least one NMOS OFF → output = 1.
• A = 1 and B = 1:
PMOS OFF, both NMOS ON → output = 0.
Performance Implications
• Series NMOS stack increases pull-down resistance → slower fall time compared to inverter.
• Parallel PMOS improves pull-up strength → rise time less affected.
• Proper transistor sizing needed to balance propagation delays.e
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V.3.2 NOR Gate
NOR = Not-OR = OR followed by Inverter
Timing chart
Symbol Truth table
•Output is 1 only when both A and B are 0
•Output is 0 whenever either input is high
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Circuit of CMOS NOR
Structure
•Pull-Up Network (PUN): Two PMOS in series, connecting output to 𝑉𝐷𝐷 .
•Pull-Down Network (PDN): Two NMOS in parallel, connecting output to GND.
•Inputs A and B drive both PUN and PDN.
Device-Level Interpretation
•A = 0 and B = 0:
• Both PMOS ON → strong pull-up → output = 1
• NMOS OFF → no pull-down path
•A = 1 or B = 1:
• At least one NMOS ON → strong pull-down → output
=0
• At least one PMOS OFF → PUN cut off
Performance Implications
•Series PMOS stack → higher pull-up resistance → slower rise time
•Parallel NMOS → strong pull-down → faster fall time
•Transistor sizing must compensate (PMOS wider) to balance delays.
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V.3.3 Compound Gate
What is a Compound Gate?
•A CMOS logic gate that implements multiple logic operations in a single stage.
•Built by combining series and parallel PMOS/NMOS networks to directly implement
complex Boolean expressions.
•More efficient than composing multiple simple gates (fewer transistors, smaller delay).
CMOS Principle for Compound Gates
•Pull-Up Network (PUN):
• PMOS transistors implement the dual of the logic function.
• Parallel = OR behavior; series = AND behavior.
•Pull-Down Network (PDN):
• NMOS transistors implement the direct logic function.
• Series = AND behavior; parallel = OR behavior.
•PUN and PDN must be complementary to guarantee correct logic levels.
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Compound Gate (cont.)
Why Use Compound Gates?
•Reduces number of stages → lower propagation delay
•Fewer transistors compared to cascading NAND/NOR → smaller area &
lower power
•Enables direct implementation of complex logic equations
Typical Designs
•AOI (AND-OR-Inverter) gates
•OAI (OR-AND-Inverter) gates
•Complex multiplexer logic
•Arithmetic building blocks (adders, decoders,
multiplexers)e
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Summary:
•CMOS combines NMOS pull-down and PMOS pull-up devices for full-swing, low-power logic.
•NMOS passes strong ‘0’, PMOS passes strong ‘1’ → complementary switching with near-zero static
power.
•CMOS inverter is the fundamental gate: high noise margins, steep VTC, balanced by transistor sizing.
•CMOS fabrication uses n-well/p-well, poly, n⁺/p⁺ diffusion, contacts, metal with λ-based layout rules.
•NAND gate: PMOS parallel, NMOS series → output low only when A = B = 1.
•NOR gate: PMOS series, NMOS parallel → output high only when A = B = 0.
•Compound gates integrate multiple logic operations in one stage using complementary PUN/PDN
networks.
•AOI/OAI structures reduce stages → lower delay, area, and power compared to cascading simple gates.
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