Microprocessors — Complete Answers (Q1–Q6)

Q1 (a) Design 8086 microprocessor-based on following Specifications:

MP 8086 working at 10MHz minimum mode. 32 KB ROM using 8 KB Devices. 16 KB RAM using 4KB chips.
Answer:
Requirements & assumptions: 8086 in Minimum Mode (MN/MX■ = 1). 20-bit address bus (A19..A0). Use
four 8KB ROM chips (4×8KB=32KB) and four 4KB RAM chips (4×4KB=16KB).
Memory map (example):
ROM (32 KB): 00000h — 07FFFh | RAM (16 KB): 08000h — 0BFFFh
Device addressing:
• 8 KB = 2^13 bytes → uses address bits A12..A0 internally. Use A14..A13 to select which 8KB chip within
the 32KB block. • 4 KB = 2^12 bytes → uses A11..A0 internally. Use A13..A12 to select which 4KB chip
within the 16KB block.
Chip-select decoding (logical scheme):
• ROM block placed at 00000h–07FFFh. ROM chip selects: - ROM0 selected when A19..A15 = 00000 and
A14..A13 = 00 → 00000h–01FFFh - ROM1 when A14..A13 = 01 → 02000h–03FFFh - ROM2 when A14..A13
= 10 → 04000h–05FFFh - ROM3 when A14..A13 = 11 → 06000h–07FFFh
• RAM block at 08000h–0BFFFh. RAM chip selects using A13..A12: - RAM0: 08000h–08FFFh
(A13..A12=00) - RAM1: 09000h–09FFFh (A13..A12=01) - RAM2: 0A000h–0AFFFh (A13..A12=10) - RAM3:
0B000h–0BFFFh (A13..A12=11)
Decoder & glue logic:
Use small TTL decoders (e.g., 74xx138/74xx139): feed appropriate high address lines to detect region and
low select lines to generate CS signals. Gate decoder outputs with region detect using AND logic so each
chip CS is active only when address is in region. Connect ALE to an address latch to demultiplex AD0..AD15.
Byte-lane selection:
Use BHE■ and A0 to select high/low byte in 16-bit data transfers. Tie CPU RD■/WR■ to memory control
logic and enable data transceivers with DEN■.
Reset/Boot note:
Typical 8086 boots from the reset vector at physical FFFF0h (systems often map ROM at top of memory). If
ROM is placed at 00000h in this design, the bootstrap must be arranged (remap or initial loader) so CPU
finds a valid reset vector. Examiner will accept either arrangement if explanation given.
Q1 (b) Draw and explain Write operation and Read operation Timing diagram of 8086
Processor in Maximum mode
Context: Maximum mode (MN/MX■ = 0). External bus controller 8288 generates MEMR■/MEMW■/IO
control lines. Bus cycle phases: T1, T2, T3, optional Tw (wait), T4.
Key signals: ALE, AD15..AD0 (multiplexed address/data), A16..A19 (high address), S2..S0 (status), DEN■,
DT/R■, MEMR■, MEMW■ (from 8288), BHE■, RD■, WR■.
Read cycle (sequence):
1. T1: CPU places address on AD lines; ALE high pulses to latch low address bits. Status S2..S0 indicate
memory read. 2. T2: 8288 decodes and asserts MEMR■; DEN■ enables data transceivers. 3. T3: Memory
drives valid data; CPU samples data. 4. T4: MEMR■ and DEN■ deassert; end of cycle. If memory slow, Tw
(wait) states inserted between T3 and T4.
Read timing ASCII diagram (simplified):
CLK: |■■|__|■■|__|■■|__|■■|__|
AD : [ADDR during T1]----(float)------[DATA during T3]
ALE : __/■■■\_______\_____/_______\_____
MEMR■: ------\________/-----------------
DEN■: ----\_________/-------------------
DT/R■: ----\--1(read)--\----------------
Write cycle (sequence):
1. T1: Address on AD bus; ALE latches address. 2. T2: CPU places data on AD lines; DT/R■ indicates CPU
drives bus, DEN■ asserted, 8288 asserts MEMW■. 3. T3: Memory latches data while MEMW■ active. 4. T4:
MEMW■ and DEN■ deassert; end of write. Tw wait states may be inserted if needed.
Write timing ASCII diagram (simplified):
CLK: |■■|__|■■|__|■■|__|■■|__|
AD : [ADDR during T1] [DATA during T2]
ALE : __/■■■\_____/_____
MEMW■: ------\________/---
DEN■: ----\_________/----
DT/R■: ----\--0(write)--\--
Notes: • BHE■ and A0 control byte-lane selection. • In maximum mode 8288 decodes status to generate
MEMR■/MEMW■. • QS0/QS1 are queue status; RQ/GT lines for bus arbitration.
Q2 (a) Explain the Initialization command words (ICWs) and Operational command
words (OCWs) of the 8259 PIC
Overview: 8259A PIC uses ICWs during initialization and OCWs during normal operation. ICW1..ICW4
configure vector base, cascade and mode. OCW1..OCW3 used to mask/unmask and control EOI and read
registers.
ICW details:
ICW1: Starts initialization. Important bits: IC4 (1=ICW4 will follow), SNGL (1=single controller), LTIM (level
triggered), and '1' bit to indicate init. ICW2: Interrupt vector base (high byte) — sets base vector address for
IRQs. ICW3: Cascade info (for master: bitmap of which IR lines have slaves; for slave: ID of slave). ICW4:
Optional (if IC4=1) — 8086/8080 mode selection, Automatic EOI, buffered mode, special fully nested mode.
OCW details:
OCW1: Interrupt Mask Register (IMR). OCW2: EOI and priority commands (specific/non-specific EOI, rotate
priorities). OCW3: Read register selection (IRR/ISR), polling mode and special mask mode.
Initialization sequence: write ICW1 → ICW2 → (ICW3 if cascade) → (ICW4 if requested). During operation
use OCW1/OCW2/OCW3 for masking and EOI handling.
Q2 (b) Explain the interrupt structure of the 8086 processor (IVT) and differentiate
between Hardware and Software interrupts
IVT (Interrupt Vector Table):
Located at physical addresses 00000h–003FFh (1 KB). Contains 256 vectors (0–255); each vector is 4
bytes: offset (word at 4×n) and segment (word at 4×n+2). On interrupt, CPU pushes FLAGS, CS, IP then
loads new CS:IP from IVT entry.
Hardware vs Software interrupts:
Hardware interrupts: originate from external devices via INTR or NMI. INTR is maskable by IF; NMI is
non-maskable and edge-triggered. Software interrupts: generated by INT n instruction or exceptions
(synchronous). Key differences: source (external vs instruction), timing (asynchronous vs synchronous),
masking behavior, and how vector is supplied (PIC may supply vector for hardware).
Q3 (a) Comparison 80386, Pentium 1, Pentium 2 and Pentium 3 Processor
80386 (386): - Intro: mid-1980s. 32-bit IA-32 architecture, protected mode and paging, simple pipeline (~6
stages), no on-chip L1 cache in early models. Pentium (P5): - Intro: early 1990s. Superscalar (dual pipelines
U and V), on-chip L1 cache (split I/D), improved integer performance and pipelining. Pentium II (P6 family): -
Intro: late 1990s. P6 microarchitecture: out-of-order execution, dynamic scheduling, reorder buffer, register
renaming, better branch prediction, MMX support, improved L2/cache subsystem. Pentium III: - Intro: ~1999.
P6 core enhancements + SSE instructions for SIMD floating-point, larger caches and improved clock scaling.

Q3 (b) Write an assembly language program for searching a Character in a Given

String and explain XLAT, DAA, LAHF, AAA
Assumptions: ES:DI -> string start, AL = character to find, CX = length (bytes). Returns DI pointing to found
char (ZF=1) or sets AX=0FFFFh if not found.

SEARCH_CHAR:
PUSH CX
PUSH DI
CLD
REPNE SCASB ; Compare AL with [ES:DI] until found or CX=0
JNZ NOT_FOUND
DEC DI ; adjust to point to found character
POP DI
POP CX
RET

NOT_FOUND:
POP DI
POP CX
MOV AX, 0FFFFh
RET
XLAT: AL ← [BX + AL]. Uses AL as index into a 256-byte table at BX. Handy for lookup tables. DAA: Decimal
Adjust AL after Addition. After adding two packed BCD digits, DAA adjusts AL (adds 6 or 60) so result is valid
packed BCD; updates AF/CF accordingly. LAHF: Load AH from Flags. Copies SF, ZF, 0, AF, 0, PF, 1, CF
into AH for quick flag testing. AAA: ASCII Adjust after Addition. Adjust AL/AH after adding two unpacked
ASCII digits (0-9) to form correct unpacked BCD result.
Q4 (a) Draw and explain Pentium 4: NetBurst microarchitecture
NetBurst (Pentium 4) — Key points: - Very deep pipeline (long pipelines to enable high clock rates; early P4
~20 stages). - Trace Cache: stores decoded micro-operations (uops) so frequently executed instruction
streams avoid re-decoding. - Front End: instruction fetch, branch predictor, trace cache. - Out-of-order
execution engine with register renaming and ROB; multiple execution units (integer, FP/SSE, address
generation). - Rapid Execution Engine: some integer units optimized for higher throughput. - Memory
subsystem: aggressive hardware prefetching, L1/L2 caches, front-side bus to memory. - Tradeoffs: deep
pipeline increases branch mispredict penalty, mitigated by advanced branch prediction and trace cache.

Q4 (b) Explain MESI Protocol

MESI states: M - Modified: cache line dirty, only this cache has valid data; memory stale. E - Exclusive: only
this cache has a clean copy; memory up-to-date. S - Shared: clean copy possibly in multiple caches. I -
Invalid: not valid. Transitions: - Read miss with no sharers -> E. - Read miss with sharers -> S. - Write miss
-> issue Read-For-Ownership (BusRdX), other caches invalidate -> M. - Write hit in S -> BusUpgr to
invalidate others -> M. - Write hit in E -> locally become M (no bus). Purpose: maintain coherent memory
view across multiple caches with minimal bus traffic.
Q5 (a) Draw and explain architecture of 8086
Major blocks: - Bus Interface Unit (BIU): handles address generation (segment*16 + offset), multiplexed AD
bus, ALE, prefetch queue (6 bytes). - Execution Unit (EU): decodes and executes instructions from the
prefetch queue; contains ALU, registers, flags. - Registers: AX,BX,CX,DX (general), SI,DI,BP,SP
(index/pointer), CS,DS,SS,ES (segments), IP, FLAGS. - Prefetch queue keeps EU fed; on branches the
queue is flushed. Operation: - BIU fetches instruction bytes into prefetch queue; EU consumes them. BIU
also performs memory and I/O bus cycles on behalf of CPU.

Q5 (b) Differentiate between Real Mode, Virtual 8086 Mode and Protected Mode of
80386 Processor
Real Mode: - 20-bit physical addressing via segment:offset, no protection, no paging, backward compatible
with 8086/DOS. Protected Mode: - 32-bit addressing with GDT/LDT descriptors, privilege levels (rings 0-3),
hardware memory protection, paging (virtual memory), multitasking support (TSS). Virtual 8086 Mode: - A
special sub-mode inside Protected Mode that allows execution of real-mode programs in a protected
multitasking environment. Each v86 task runs like real mode but privileged operations trap to OS. Summary:
- Real: simple, no protection. Protected: full OS-level protection and features. V86: supports legacy 16-bit
apps within protected OS.

Q5 (c) Explain the Floating point Pipeline of Pentium Processor

Floating-point (x87) pipeline overview: - x87 is stack-based (ST0..ST7); many complex ops are microcoded. -
Pentium introduced pipelined execution for some FP ops: separate adder and multiplier pipelines; division
and transcendental functions are multi-cycle/microcoded and have larger latencies. - SSE (in later Pentiums)
introduced XMM registers and SIMD FP pipelines for packed single-precision, improving throughput for
vector workloads. - Typical stages: fetch -> decode -> micro-op generation -> issue to FP unit -> execution
(multi-cycle) -> writeback/retire.
Q6 (a) Explain Modes of 8255 with a neat block diagram. Show the CWR
initialization.
8255 PPI overview: - Ports: Port A (8-bit), Port B (8-bit), Port C (8-bit, can be split into PC7..PC4 and
PC3..PC0). Modes: - Mode 0 (Basic I/O): simple input/output; Port C used as I/O bits. - Mode 1 (Strobed I/O):
Port A or B with handshake using PC lines (STB, IBF, OBF, ACK). - Mode 2 (Bidirectional): Port A as
bidirectional bus with handshake (uses Port C); Port B may be Mode 0 or Mode 1. Control Word Register
(CWR): - Two formats: 1) Mode set (D7=1): sets modes and directions. Bits (D7..D0): 1, D6(Port A mode
msb), D5(D4 Port A mode lsb), D4 Port A direction (1=in,0=out), D3 PortC upper dir, D2 PortB mode msb, D1
PortB mode lsb, D0 PortB/PC lower dir. 2) Bit Set/Reset (D7=0): set/reset single bit of Port C. Example: To
set Port A input (Mode0), Port B output (Mode0), PC upper input, PC lower output: - Mode set control word
(example): 1000 1010b = 8Ah (verify against datasheet mapping in exam).

Q6 (b) Write an ALP for 8086 to transfer the block of data

Word-wise transfer (addresses must be word-aligned):

; DS:SI = source, ES:DI = destination, CX = number of words
BLOCK_MOVE_WORDS:
CLD
REP MOVSW
RET

Byte-wise transfer:
; DS:SI = source, ES:DI = destination, CX = number of bytes
BLOCK_MOVE_BYTES:
CLD
REP MOVSB
RET

Aligned routine with odd-byte handling (summary):

- If SI and DI are even, use MOVSW (CX = bytecount >> 1); if original bytecount odd, handle last byte with
MOVSB.
End of Document. All answers include questions and detailed solutions for Q1–Q6.