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A-Level Computer Science CPU Concepts

The document contains a series of questions and answers related to CPU architecture and operations, including CPU registers, stages of instruction processing, cache memory, and different architectures. It discusses concepts such as clock speed, pipelining, and the advantages and disadvantages of multi-core processors. The content is structured into two sections, with Section A posing questions and Section B providing detailed answers.

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4 views2 pages

A-Level Computer Science CPU Concepts

The document contains a series of questions and answers related to CPU architecture and operations, including CPU registers, stages of instruction processing, cache memory, and different architectures. It discusses concepts such as clock speed, pipelining, and the advantages and disadvantages of multi-core processors. The content is structured into two sections, with Section A posing questions and Section B providing detailed answers.

Uploaded by

iuliaroxanaapostol
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

OCR A-Level Computer Science

Processor Questions and Answers

Section A: Questions
1. Name four CPU registers and state their purpose.
2. Describe the fetch stage.
3. Describe the decode stage.
4. Describe the execute stage.
5. What is clock speed?
6. Give two advantages of more CPU cores.
7. Give one disadvantage of more CPU cores.
8. What is cache memory?
9. Explain the difference between L1, L2, L3 cache.
10. What is pipelining?
11. What is the Von Neumann architecture?
12. Why can the Von Neumann architecture create bottlenecks?
13. What is a Harvard architecture?
14. What is the ALU?
15. What is the Control Unit?
16. What does the address bus do?
17. What does the data bus do?
18. What does the control bus do?
19. What is an interrupt?
20. Explain one advantage and one disadvantage of very high clock speed.

Section B: Answers
1. PC, MAR, MDR, CIR, ACC (any four) with their purposes.
2. PC → MAR; address bus used; read signal sent; MDR receives instruction; MDR → CIR; PC
increments.
3. Control Unit decodes instruction into opcode and operand and prepares hardware.
4. ALU executed instruction; registers/memory updated; flags may update.
5. Cycles per second; higher speed means more instructions per second.
6. More tasks at same time; parallel processing.
7. Not all software uses multiple cores; more heat/power.
8. Very fast memory storing frequently used data close to CPU.
9. L1 fastest smallest; L2 bigger slower; L3 biggest slowest; improves hit rate.
10. Pipelining overlaps FDE stages to increase throughput.
11. One memory for instructions and data; single shared bus.
12. Shared bus causes delays when fetching instructions and data.
13. Separate memory and buses for instructions and data.
14. Performs arithmetic and logic operations.
15. Manages FDE cycle and sends control signals.
16. Carries memory addresses from CPU to RAM.
17. Carries data between CPU and memory (two-way).
18. Carries control signals (read/write/interrupt).
19. Signal that pauses CPU to run service routine.
20. Advantage: faster. Disadvantage: more heat/power.

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