instruction fetch and instruction execution.
The instruction execution may involve
several operations and depends on the nature of the instruction.
The processing required for a single instruction is called an instruction cycle.
The instruction cycle is depicted in Figure 2-4. The two steps are referred to as the Fetch
cycle and the Execute cycle. Program execution halts only if,
1. the machine is turned off,
2. some sort of unrecoverable error occurs, or
3. a program instruction that halts the computer is encountered.
Figure 2-4: Basic Instruction Cycle
Running Example 2.1: Program Execution
The 1st Cycle
Instruction Fetch
Below we have a representation of a CPU and main memory. The registers where data
can be temporarily stored are shown, as are the execution unit components (ALU and
control unit) and memory locations.
Figure 2-5: Representation of a CPU and main memory
At the beginning of each instruction cycle, the processor fetches an instruction from
memory. How does the processor know where to start? In a typical processor, a register
called the program counter (PC) holds the address of the instruction to be fetched next.
In the example, the Program Counter (PC) starts at 0000. This means that the first
address in main memory where the computer will look for an instruction is at 0000.
Figure 2-6: Loading of PC
The computer needs somewhere to store the current address in main memory that it is
looking for. This is what the Memory Address Register (MAR) is for. 0000 is therefore
copied into the MAR.
Figure 2-7: Loading of MAR
A signal is now sent down through the Address bus to the main memory. The Control
Unit sends out a memory read signal, and the contents of the address 0000 are copied
through the data bus to the Memory Data Register (MDR), which is also called a Memory
Buffer Register (MBR).
Figure 2-8: Loading of MDR
As the data fetched during the fetch stage is an instruction, it is copied into the Instruction
Register (IR).
Figure 2-9: Loading of IR
As the first instruction has been fetched, the system is at the end of the Fetch stage of
the cycle. Unless told otherwise, the processor always increments the PC after each
instruction fetch so that it will fetch the next instruction in sequence (i.e., the instruction
located at the next higher memory address). The program counter can be incremented
by 1, so the system is ready to read the next instruction when the next Fetch cycle starts.
Figure 2-10: Incrementing PC
Instruction Execute
First the instruction needs to be decoded. It is sent via the data bus to the control unit,
where it is split into two parts. The first part is the operation code or opcode, which in this
example CPU is the first 4 bits. This is the command that the computer will carry out. The
second part, in this case the second 4 bits, is the operand. This is an address in main
memory where data will be read from or written to, depending on the operation. The
Control Unit can translate opcodes into instructions. So here the Control Unit translates
the opcode 0101 into a LOAD FROM main memory instruction.
Figure 2-11: Decoding Op
Now the command will be executed. The operand is copied to the MAR, as this is the
address of the data that needs to be loaded. The data at address 0100 is then fetched
from main memory and passed up the data bus to the MDR. As it is not an instruction but
simply data, it is then passed to the Accumulator (Acc).
Figure 2-12: Loading Acc
This is a complete Fetch Decode Execute Cycle.
The 2nd cycle
so we next fetch, decode and execute the instruction at that address.
1. The PC is at 0001, so this is the next instruction to be fetched.
2. The instruction opcode and address operand are placed in the IR, and the PC
increased by 1 again.
3. First the instruction is decoded, while the address of the data to be acted upon is
placed in the MAR. The instruction turns out to be ADD, which adds two pieces of
data together.
4. The new data is fetched from the address and eventually ends up in the
accumulator, along with the results of the previous cycle.
5. To finish off this stage, the two values in the accumulator are passed into the ALU,
where they can be added together, as was instructed by the opcode.
6. The result is then placed back into the accumulator.
The 3rd cycle
1. The last cycle is for the instruction at 0010. It uses the opcode 0011 which is
STORE and the operand 0110, which is the last address in the main memory
shown.
2. So this cycle takes the results of the addition in the accumulator and stores it back
into main memory at address 0110, as requested.
To recap, the example program used three instructions to add two numbers and store
the result in memory:
1. The first instruction LOADed a piece of data from a specified address.
2. The second ADDed this to the data found in another address.
3. The final instruction STOREd the result of the addition back into a specified
address in memory.
There is a lot of information to take in to understand the Fetch, Decode, Execute cycle.
Many people find it confusing when following it for the first time. You may find it helpful to
run through this activity a 2nd time.
2.7 Interrupts
To understand more clearly the nature of the instruction cycle, it is important to introduce
a key concept called Interrupts.