Principles of digital electronics (Answer key)
PART-A
UNIT – I
1. (c) 16
2. (d) 0110
3. (b) 0 to 9
4. (c) voltage controlled current device
5. (d) Gray
6. (d) All of the above
7. (b) 1001001
8. (c) 13
UNIT – II
1. (c) 4
2. (b) A + A = A, A · A = A
3. (c) EX-OR gate and AND gate
4. (b) 16
5. (d) 4
6. (b) A′B′ + AB
7. (d) 16
8. (a) 3
UNIT – III
1. (a) 1
2. (a) 1
3. (a) 5 States
4. (c) Change the output to the opposite state
5. (d) None of the above
6. (b) JK
7. (a) 8 bit data
8. (d) 7
UNIT – IV
1. (c) 16
2. (d) Synchronous counter
3. (c) 8
4. (a) 1110
5. (a) One bit
6. (a) The output word decreases by 1
7. (a) Race condition
8. (d) None of the above
UNIT – V
1. (b) module
2. (d) All the above
3. (a) lowercase
4. (a) Transition from 0 to 1, x or z
5. (d) X
6. (a) 0
7. (a) Unary
PART B
UNIT – I
1. Types of Binary Codes (based on positional weighting):
o Weighted codes: 8421, 2421, Excess-3
o Non-weighted codes: Gray code, ASCII, BCD
2. De Morgan’s Theorem:
o (A + B)’ = A’B’
o (AB)’ = A’ + B’
3. TTL vs CMOS:
o TTL: Uses bipolar transistors, higher power, faster.
o CMOS: Uses MOSFETs, low power, slower but high noise immunity.
4. Weighted vs Non-weighted Codes:
o Weighted: Each bit has positional weight (e.g., 8421).
o Non-weighted: No fixed weights (e.g., Gray, Excess-3).
5. Excess-3 Code is Self-Complementing:
o 9’s complement in decimal equals 1’s complement in Excess-3.
6. Conversions:
a) (7526.75)₁₀ = (16636.6)₈
b) (1856.959)₁₀ ≈ (740. F5C3)₁₆
7. Number Systems in Digital Systems:
o Binary, Octal, Decimal, Hexadecimal.
8. Characteristics of Digital ICs:
o Fan-in, Fan-out, Power dissipation, Noise margin, Speed, Propagation delay.
UNIT – II
1. SOP and POS:
o SOP: Sum of products (OR of AND terms).
o POS: Product of sums (AND of OR terms).
2. Canonical SOP of Y = AB + A’C + BC’:
Y = Σm(1,3,5,6,7)
3. EX-OR using NAND:
Y = (A NAND (A NAND B)) NAND (B NAND (A NAND B))
4. Canonical SOP of Y = AC + AB + BC:
Y = Σm(3,5,6,7)
5. Simplify Z = AB + A·B·(A·C):
Z = AB
6. Simplify F = (X+Y)(X+Y’):
F=X
7. 4:1 MUX Block Diagram:
o 4 data inputs, 2 select lines, 1 output.
8. Principle of Duality:
o Interchanging + ↔ · and 0 ↔ 1 in a Boolean expression.
UNIT – III
1. Synchronous vs Asynchronous:
o Synchronous: Clock controlled.
o Asynchronous: No common clock, event-driven.
2. JK to T Flip-Flop:
o Connect J = K = T.
3. Clocked SR Flip-Flop:
o Truth Table:
S=0,R=0 → No change
S=0,R=1 → 0
S=1,R=0 → 1
S=1,R=1 → Invalid
4. Ripple vs Synchronous Counter:
o Ripple: Asynchronous, sequential triggering.
o Synchronous: All flip-flops triggered by same clock.
5. Sequential vs Combinational:
o Sequential: Depends on past & present inputs.
o Combinational: Depends only on present inputs.
6. Minimum Flip-Flops for Mod-60:
o 2⁶ = 64 → 6 flip-flops.
7. Moore vs Mealy:
o Moore: Output depends on state only.
o Mealy: Output depends on state and input.
8. Excitation Table of JK Flip-Flop:
Qn Qn+1 J K
0 0 0X
0 1 1X
1 0 X1
1 1 X0
UNIT – IV
1. Hazards:
o Static-1, Static-0, Dynamic hazards.
2. PLA Structure:
o Programmable AND array + Programmable OR array.
3. ROM Implementation:
F₁ = Σm(1,2,3); F₂ = Σm(0,1,3) → ROM programmed with outputs for those minterms.
4. Critical Race:
o Occurs when two state variables change simultaneously causing instability.
5. Fundamental vs Pulse Mode:
o Fundamental: Input changes after circuit stabilizes.
o Pulse Mode: Inputs are pulses of short duration.
6. Pulse Mode Not Popular:
o Sensitive to pulse width, timing errors, instability.
7. PAL vs PLA:
PAL: Fixed OR, programmable AND.
o
PLA: Both AND & OR are programmable.
o
8. SRAM vs DRAM:
o SRAM: Flip-flop based, faster, costlier.
o DRAM: Capacitor based, slower, cheaper, needs refreshing.
UNIT – V
1. Verilog Code for EXOR:
2. module exor(a,b,y);
3. input a,b; output y;
4. assign y = a ^ b;
5. endmodule
6. Verilog Code for ENOR (XNOR):
7. module enor(a,b,y);
8. input a,b; output y;
9. assign y = ~(a ^ b);
10. endmodule
11. CPLD vs FPGA:
o CPLD: Coarse-grained, non-volatile, faster interconnects.
o FPGA: Fine-grained, SRAM-based, more flexible and larger.
12. Purpose of HDL:
o To describe, simulate, and implement digital circuits.
13. Operators in Verilog:
o Arithmetic, Relational, Logical, Bitwise, Reduction, Shift, Conditional.
14. Blocking vs Non-blocking:
o Blocking (=): Executes sequentially.
o Non-blocking (<=): Executes concurrently.
15. Always vs Initial:
o Always: Repeats throughout simulation.
o Initial: Executes once at start.
16. Half Adder (Gate Level):
17. module half_adder(a,b,sum,carry);
18. input a,b; output sum,carry;
19. xor(sum,a,b);
20. and(carry,a,b);
21. endmodule
PART C
Unit 1
1. Number System Conversions
(i) (147.3)₈ → (?)₁₆
Step 1: Convert octal → binary
1 → 001
4 → 100
7 → 111
.3 → .011
So,
(147.3)₈ = (001 100 111.011)₂ = (1100111.011)₂
Step 2: Group binary into 4 bits for hexadecimal
= 0110 0111 .0110 (add zeros if needed)
→ 6 7 .6
✅ Answer: (147.3)₈ = (67.6)₁₆
---
(ii) (010010101000)₂ → (?)₁₆
Group into 4 bits:
0100 1010 1000
Now convert each:
0100 = 4
1010 = A
1000 = 8
✅ Answer: (010010101000)₂ = (4A8)₁₆
---
(iii) (38.21)₁₀ → (?)₂
Step 1: Integer part: 38 → divide by 2
38 ÷ 2 = 19 R0
19 ÷ 2 = 9 R1
9 ÷ 2 = 4 R1
4 ÷ 2 = 2 R0
2 ÷ 2 = 1 R0
1 ÷ 2 = 0 R1
→ 38 = 100110₂
Step 2: Fractional part: 0.21 × 2 repeatedly
0.21×2=0.42 (0)
0.42×2=0.84 (0)
0.84×2=1.68 (1)
0.68×2=1.36 (1)
0.36×2=0.72 (0)
0.72×2=1.44 (1)
→ approx .001101₂
✅ Answer: (38.21)₁₀ ≈ (100110.001101)₂
---
(iv) (231.3)₁₀ → (?)₈
Integer part: 231 → divide by 8 231 ÷ 8 = 28 R7
28 ÷ 8 = 3 R4
3 ÷ 8 = 0 R3
→ (231)₁₀ = (347)₈
Fractional part: 0.3 × 8 = 2.4 → 2
→ .2₈
✅ Answer: (231.3)₁₀ = (347.2)₈
---
2. Arithmetic and Binary-to-Octal
(i) (756)₈ - (437)₈ + (725)₁₆ → express in octal
Step 1: Convert all to decimal
(756)₈ = 7×64 + 5×8 + 6 = 448 + 40 + 6 = 494
(437)₈ = 4×64 + 3×8 + 7 = 256 + 24 + 7 = 287
(725)₁₆ = 7×256 + 2×16 + 5 = 1792 + 32 + 5 = 1829
Now perform:
= 494 - 287 + 1829 = 2036
Step 2: Convert 2036₁₀ → octal
2036 ÷ 8 = 254 R4
254 ÷ 8 = 31 R6
31 ÷ 8 = 3 R7
3 ÷ 8 = 0 R3
→ (3674)₈
✅ Answer: (3674)₈
---
(ii) (1001001110101101)₂ → octal
Group by 3 bits (from right):
001 001 001 110 101 101
→111655
✅ Answer: (11655)₈
For (10010001011.00101110)₂ → octal
Integer: 010010001011 → 100 100 010 11 → (add 0s) → 010 010 001 011
→ 2 2 1 3 → (2213)₈
Fraction: .00101110 → group as .001 011 100 → .134₈
✅ Answer: (10010001011.00101110)₂ = (2213.134)₈
---
3. Error Detection & Correction
i) Error Detection and Correction Codes
Error Detection: identifies errors in data transmission.
Example: Parity Bit Method
Add 1 extra bit to make total 1’s even (even parity) or odd (odd parity).
E.g., data = 1011 → even parity = 10111
Error Correction: locates and corrects single-bit errors.
Example: Hamming Code
Adds parity bits at positions 1, 2, 4, 8, etc.
Can correct single-bit errors.
---
ii) Alphanumeric Codes
Represent both letters (A–Z) and numbers (0–9) in binary.
Examples:
ASCII: American Standard Code for Information Interchange (7-bit)
EBCDIC: 8-bit IBM mainframe code
Unicode: Universal 16-bit/32-bit encoding
---
4. Hamming Code & Conversions
(i) Hamming Code Words
Given 12-bit code = 8 data + 4 parity bits
A) 101110010100 → Error detection by parity bit positions
B) 111111110100 → Similar check
👉 Detailed step-by-step syndrome detection can be expanded if required
(too lengthy here).
But generally, identify error bit using parity positions (1,2,4,8) and flip it.
---
(ii) Convert Decimal to Hex, Octal, Binary
(A) (1259)₁₀
→ Hex: 1259 ÷16 = 78 R11 (B) → 78÷16=4R14(E) → (4EB)₁₆
→ Octal: 1259 ÷8 → (2353)₈
→ Binary: 10011101011₂
✅ (1259)₁₀ = (4EB)₁₆ = (2353)₈ = (10011101011)₂
(B) (5768)₁₀
→ Hex: 5768 ÷16 = 360 R8 → 360÷16=22R8 →22÷16=1R6 →1÷16=0R1
→ (1688)₁₆
→ Octal: (13030)₈
→ Binary: 1011010001000₂
✅ (5768)₁₀ = (1688)₁₆ = (13030)₈ = (1011010001000)₂
---
5. Codes
(i) 7-bit Hamming code for 1011
Data bits (positions 3,5,6,7):
1011
Hamming code arrangement:
Positions: 1(p1),2(p2),3(d1),4(p4),5(d2),6(d3),7(d4)
So: _ _ 1 _ 0 1 1
Compute parity bits:
p1 covers bits 1,3,5,7 → 1+0+1=2 (even) → p1=0
p2 covers bits 2,3,6,7 → 1+1+1=3 (odd) → p2=1
p4 covers bits 4,5,6,7 → 0+0+1+1=2 (even) → p4=0
✅ Hamming Code = 0 1 1 0 0 1 1 = (0110011)
---
(ii) Excess-3 & Gray Code
Hex F = (1111)₂ → Excess-3 = 1111 + 0011 = 10010 → (ignore carry) → (0010)₂ =
2
Hex A = (1010)₂ → +3 = (1101)₂ → D
Hex B = (1011)₂ → +3 = (1110)₂ → E
✅ (F)₁₆ = (1111)₂ → Gray = 1000
✅ (AB)₁₆ = (10101011)₂ → Gray = 11111110
---
6. Weighted & Non-Weighted Codes
Type Example Explanation
Weighted Binary (8421), BCD Each bit has fixed weight. Ex: 8421 →
0101 = 5
Non-Weighted Excess-3, Gray No fixed weights; used for error
detection and reflection properties
9. Subtraction Using Complements
Given X=1010100, Y=1000011
(a) X–Y (using 2’s complement)
Y = 1000011 → 1’s complement = 0111100
+1 = 0111101 → 2’s complement
Add to X:
1010100 + 0111101 = 10010001 → discard carry → 0010001
X–Y = +10001₂ = 17₁₀
(b) Y–X (using 2’s complement)
X’s 2’s complement = 0101100
Y + 0101100 = 1000011 + 0101100 = 1101111 (no carry → negative)
→ Take 2’s complement of result: 0010001 → -17₁₀
X–Y = +17, Y–X = -17
10.
i)
ii)
Unit 2
1)
i)
ii)
2) i)
ii)
3)i)
A Binary to Gray code converter converts binary numbers into their equivalent
Gray code, where only one bit changes between successive numbers.
ii)
4)i)
ii)
5)i)
ii)
6)i)
ii) 4 to 2 encoder
7) i)
ii)
8) i) 8 to3 encoder
ii) 1to8 demultiplexer
9) i)
ii)
10) i)
ii)
Unit 3
1)Mod-10 counter counts from 0 (0000) to 9 (1001).
That means we need to represent 10 states, and .
⇒ (since )
✅ So, we need 4 JK flip-flops.
Let the outputs be Qó, Q1, Q2,Q3,Q4
Q3= MSB, Q0 = LSB
Decimal Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
Next → 0 0 0 0 0
After 1001 (9), it resets
We’ll use the JK flip-flop excitation table:
Present (Q) Next (Q⁺) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
(i) For Q₀ (LSB)
Q₀ toggles on every clock pulse.
So, 👉 ,
ii) For Q₁
Q₁ changes state whenever Q₀ = 1 (on every alternate count).
From sequence:
Q₁ toggles when Q₀ changes from 1→0 (i.e., when Q₀=1 before clock).
2)
3) Let’s design a sequence detector for the sequence “101” using JK flip-flops — step by step
and clearly
🔹 Type of sequence detector
We will design a Moore machine (output depends only on the present state).
🔹 sequence to detect
We want to detect: 1 → 0 → 1
Input symbol: X (can be 0 or 1)
Output: Z = 1 when sequence “101” is detected, else Z = 0
🔹 states
State Meaning Output (Z)
A Initial state (no match yet) 0
B 1st ‘1’ received 0
C “10” received 0
D “101” detected 1
🔹 State transition table
Present State Input X=0 Next State Input X=1 Next State Output
A A B 0
B C B 0
Present State Input X=0 Next State Input X=1 Next State Output
C A D 0
D C B 1
(We loop back to proper previous states to allow overlapping sequences like “10101”.)
🔹 binary state codes
State Q1 Q0
A 0 0
B 0 1
C 1 0
D 1 1
🔹Next state table
Present (Q1 Q0) Input X Next (Q1⁺ Q0⁺) Output Z
00 (A) 0 00 0
00 1 01 0
01 (B) 0 10 0
01 1 01 0
10 (C) 0 00 0
10 1 11 0
11 (D) 0 10 1
11 1 01 1
🔹 excitation equations for JK flip-flops
We have two flip-flops: Q1 and Q0
Use JK excitation table:
Present Q Next Q⁺ J K
0 0 0X
0 1 1X
1 0 X1
1 1 X0
(a) For Q1 flip-flop
From next-state table:
Q1 Q0 X Q1⁺
000 0
001 0
010 1
011 0
100 0
101 1
110 1
111 0
We find where Q1⁺ = 1 → produce J1 = 1
and where Q1⁺ = 0, Q1 = 1 → produce K1 = 1
Simplifying (using K-map or observation):
J1 = \bar{Q1}Q0\bar{X} + Q1\bar{Q0}X
K1 = Q1(\bar{Q0}\bar{X} + Q0X)
(b) For Q0 flip-flop
From next-state table:
Q1 Q0 X Q0⁺
000 0
001 1
010 0
011 1
100 0
101 1
110 0
111 1
Here, Q0⁺ = X
Therefore:
J0 = X, K0 = \bar{X}
🔹Output equation
Output depends only on state D (Q1Q0 = 11):
Z = Q1 \cdot Q0
4)
5)
a Decade Counter
A decade counter counts from 0 to 9 (0000 → 1001) and then resets to 0000 on the next
clock pulse.
It is therefore a mod-10 synchronous counter (10 states out of the 16 possible 4-bit
combinations).
We need 4 D flip-flops, because
2^n > 10 n = 4
Let the flip-flops be D₃ (D for MSB), D₂, D₁, and D₀ (LSB) with outputs Q₃ Q₂ Q₁ Q₀.
valid states
Decimal Q₃ Q₂ Q₁ Q₀
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
Next (Reset) → 0000
Invalid (10–15) states should automatically return to 0000.
next-state table
Present State (Q₃ Q₂ Q₁ Q₀) Next State (Q₃⁺ Q₂⁺ Q₁⁺ Q₀⁺)
0000 0001
0001 0010
0010 0011
0011 0100
0100 0101
0101 0110
0110 0111
0111 1000
1000 1001
1001 0000
transition equations (from counting pattern)
We know:
Q₀ toggles on every clock → behaves like a binary LSB.
Q₁ toggles when Q₀ = 1.
Q₂ toggles when Q₁ Q₀ = 11.
Q₃ toggles when count = 7 (0111 → 8 1000) and resets after 9.
But because we use D flip-flops,
D_i = Q_i^+
simplified Boolean expressions
From the table:
Present Next
Q₃ Q₂ Q₁ Q₀ Q₃⁺
0000 0
0001 0
0010 0
0011 0
0100 0
0101 0
0110 0
0111 1
1000 1
1001 0
By inspection → Q₃⁺ = 1 when the next count is 8 or 9, i.e., present = 7 or 8.
Hence
\boxed{D₃ = Q₂Q₁Q₀ + Q₃(\overline{Q₁} + \overline{Q₀})}
Similarly:
For D₂
Observe Q₂ changes (toggles) at counts 3→4, 7→8, 9→0.
From K-map simplification
D3= Q2Q1Q0+ Q3(Q1’ + Q0’)
Reset for invalid states
The counter should reset when it tries to go beyond 9 → i.e., when it reaches 1010 (decimal
10) or higher.
So, detection condition for invalid states:
When RESET = 1 → force all D inputs = 0 → counter goes to 0000.
6)
8)
7)
State Diagram
There are 4 states labeled as
00, 01, 10, and 11.
The transitions are as follows (from the diagram):
Present State Input (X) Next State Output (Y)
00 0 00 0
00 1 01 0
01 0 11 1
01 1 10 0
10 0 11 0
10 1 00 0
11 0 10 1
11 1 01 1
Assign Flip-Flops
Let:
Q1 = Most Significant Bit (MSB)
Q0 = Least Significant Bit (LSB)
So,
State 00 → Q1=0, Q0=0
State 01 → Q1=0, Q0=1
State 10 → Q1=1, Q0=0
State 11 → Q1=1, Q0=1
We will find the expressions for D1 and D0 (inputs to the D flip-flops).
Transition Table
Present State | Input X | Next State | Output Y
00 | 0 | 00 | 0
00 | 1 | 01 | 0
01 | 0 | 11 | 1
01 | 1 | 10 | 0
10 | 0 | 11 | 0
10 | 1 | 00 | 0
11 | 0 | 10 | 1
11 | 1 | 01 | 1
D Flip-Flop Input Equations
For D Flip-Flop:
Q_1^+ = D_1 \quad \text{and} \quad Q_0^+ = D_0
We use the next state bits as the D inputs.
Q1 Q0 X Q1+ Q0+ Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 1 1
0 1 1 1 0 0
1 0 0 1 1 0
1 0 1 0 0 0
1 1 0 1 0 1
1 1 1 0 1 1
Output (Y)
From the table:
Q1 Q0 X Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
9)
10)