23ECT502

PRINCIPLES OF VLSI DESIGN

Unit TWO
by
Dr Veeraiyah Thangasamy
 What will you learn from unit TWO
UNIT II MOS TRANSISTOR
✓ Metal Oxide Semiconductor (MOS) Transistor: Structure, Operation &
Characteristics
✓ Threshold Voltage (VT0 & VT),
✓ Drain Current (ID).
✓ MOS Capacitances
✓ MOS Scaling
✓ Second Order & Non-Ideal Effects
✓ Modeling of MOS Transistor – SPICE Models
✓ Fabrication Cycle
✓ NMOS Fabrication Processes
✓ PMOS Fabrication Processes
✓ Layout Design Rules
✓ Full-Custom Mask Layout Design
✓ Stick Diagrams.

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 MOS Transistor Structure, Operation
& Characteristics
Structure
■ The MOS transistor is a fundamental building block of modern digital and
analog electronics, including microprocessors, memory chips, and various
integrated circuits.
■ It is a voltage-controlled device, meaning an electric field generated by a
voltage applied to its gate terminal controls the flow of current between
its other two terminals, the source and the drain.
■ MOSFET is typically a four-terminal device, although the fourth terminal
(Body or Substrate) is often connected to the source in common
configurations. The four terminals are:
■ Gate (G): The control terminal, usually made of polysilicon or metal.
■ Source (S): One of the main current-carrying terminals, where charge
carriers enter the channel.

■ Drain (D): The other main current-carrying terminal, where charge carriers
exit the channel.

■ Body/Bulk/Substrate (B): The underlying semiconductor material on

which the transistor is built.
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■ There are two types of MOSFET:
■ n-Channel Enhancement Mode MOSFET - NMOS), and
■ p-Channel Enhancement Mode MOSFET - PMOS)
n-Channel Enhancement Mode MOSFET
■ It consists of:
■ Substrate (Body): This is a lightly doped p-type silicon wafer. It
provides the base for the transistor.
■ Source and Drain Regions: Two heavily doped n+ regions are
diffused or implanted into the p-type substrate. These regions are
separated by a certain distance, which defines the channel length.
■ Gate Oxide (Insulator): A very thin layer of silicon dioxide (SiO2)
is grown on the surface of the substrate, covering the region between
the source and drain. This insulating layer is critical as it electrically
isolates the gate from the semiconductor channel.
■ Gate Electrode: A conductive layer (typically polysilicon in modern
ICs, or metal in older technologies) is deposited on top of the gate
oxide. This forms the gate terminal.

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p-Channel Enhancement Mode MOSFET
■ p-Channel Enhancement Mode MOSFET (PMOS) transistor has a
complementary structure to the NMOS.
■ It consists of:
■ Substrate (Body): This is a lightly doped n-type silicon wafer
■ It is an N-well within a P-type substrate in CMOS. We will discuss this
in 3rd Unit: CMOS inverter
■ Source and Drain Regions: Two heavily doped p+ regions are
diffused or implanted into the n-type substrate.
■ Gate Oxide: Same as NMOS, a thin layer of SiO2.
■ Gate Electrode: Same as NMOS, polysilicon or metal

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Operation of an n-Channel Enhancement Mode MOSFET (NMOS)
■ Let’s explain the operation of an NMOS transistor, assuming the body is
connected to the source (or ground).
■ Case 1: Cutoff Region
■ Condition: VGS<VT
■ That is, VGS is less than the threshold voltage VT
■ The threshold voltage (VT) is the minimum gate-source voltage
required to create a conductive channel.
■ For an NMOS, VT is typically a small positive voltage.
■ Under the above condition, there are insufficient positive charges on
the gate to attract enough electrons to form a channel under the gate
oxide.
■ Therefore, virtually no current (ID≈0) flows from drain to source.
■ Thus, in cutoff region, the transistor acts like an open switch.

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■ Case 2: Linear (or Triode) Region
■ Condition: VGS>VT and VDS<(VGS−VT)
■ That is, VGS is greater than VT, and the drain-source voltage (VDS) is
less than the overdrive voltage (VGS−VT).
■ Under the above condition, a positive voltage on the gate attracts
electrons from the p-type substrate to the region directly beneath the
gate oxide. These accumulated electrons form a thin layer called the
inversion layer or channel.
■ This channel is n-type, providing a conductive path between the
n+ source and n+ drain regions.
■ When a small positive VDS is applied, these electrons in the channel
flow from the source (lower potential) to the drain (higher potential),
constituting the drain current (ID).
■ Thus, in linear region, the transistor acts like a variable resistor,
whose resistance is controlled by VGS.
■ The drain current equation is approximated as:

■ Where:
■ μn: Electron mobility in the channel
■ Cox: Gate oxide capacitance per unit area
■ W: Channel width
■ L: Channel length
■ (VGS​−VT​): Overdrive voltage
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■ Case 3: Saturation Region
■ Condition: VGS>VT and VDS≥(VGS−VT)
■ That is, VGS is greater than VT, and VDS is equal to or greater than the
overdrive voltage (VGS−VT).
■ As VDS increases beyond (VGS−VT), the voltage drop along the channel
becomes significant. The effective gate-to-channel voltage (VGC)
decreases as we move from the source end to the drain end.
■ At the drain end, the channel effectively pinches off. This means the
inversion layer at the drain end narrows down significantly or
disappears.
■ Once pinched off, the drain current becomes almost independent of
further increases in VDS.
■ Thus, in saturation region, the transistor acts like a current source,
where the current value is controlled by VGS.
■ The drain current equation is approximated as:

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Operation of an p-Channel Enhancement Mode MOSFET (PMOS)
■ The operation of a PMOS is complementary to that of an NMOS. Holes are
the majority carriers in the channel.
■ Threshold Voltage (VT) for PMOS is typically a negative voltage.
■ Cutoff: VGS>VT
■ VGS is less negative than VT.
■ No channel. ID≈0.
■ Linear: VGS<VT and ∣VDS∣<∣VGS−VT∣.
■ A p-type channel is formed by attracting holes to the region under the
gate.
■ Current flows from source to drain (conventional current direction,
holes flow from source to drain if source is higher potential than
drain).
■ The channel behaves as a voltage-controlled resistor.
■ Saturation: VGS<VT and ∣VDS∣≥∣VGS−VT∣.
■ The channel pinches off near the drain.
■ Current becomes largely independent of VDS and is controlled by VGS

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MOSFET Symbols
■ NMOS:
■ Arrow on body pointing inward (towards the gate/channel)
■ Arrow on source pointing out from the device (conventional current
flow)
■ PMOS:
■ Arrow on body pointing outward (away from the gate/channel)
■ Arrow on source pointing in to the device (conventional current flow).
■ Often has a circle (inverter bubble) on the gate to signify its
complementary operation to NMOS.

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■Threshold
T
Voltage (VT0 & VT)
■ To explain what is threshold voltage, we need to RECALL the channel
formation in MOSFET
■ RECALL Channel Formation:
■ When a positive voltage (VGS) is applied to the gate of an n-channel
MOSFET (with respect to the source, which is often tied to the body), it
attracts electrons from the p-type substrate towards the SiO2
semiconductor interface.
■ Initially, with a small positive VGS, the electric field repels the majority
carriers (holes) from the surface, creating a depletion region.
■ As VGS increases further, minority carriers (electrons) are attracted to
the interface (see the Figure on next slide)
■ When a critical voltage is reached, the concentration of electrons at the
surface becomes comparable to or even exceeds the concentration of
holes in the bulk.
■ This phenomenon is called inversion, and the thin layer of electrons
formed at the interface constitutes the conductive channel.
■ This channel provides a path for current flow between the source and
drain.
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■ Therefore, the threshold voltage (VT) is defined as the minimum gate-
to-source voltage (VGS) required to create a conducting channel between
the source and drain terminals of a MOSFET.
■ Below VT, the MOSFET is in the cutoff region (ideally no current
flows).
■ Above VT, the MOSFET is in the on-state, allowing current (ID) to
flow between the drain and source.
■ VTO (Threshold Voltage with Zero Body Bias) is defined as the
minimum gate-to-source voltage (VGS) required to create a conducting
channel between the source and drain terminals of a MOSFET when the
source and body (bulk) terminals are at the same potential (VSB=0).
■ This is the baseline threshold voltage, and it is a crucial parameter
determined by the manufacturing process and material properties.
■ For enhancement-mode MOSFETs (which are normally OFF when
VGS=0), a gate voltage greater than VT (positive for n-MOS, negative for
p-MOS) is required to turn them ON and create a channel. As such:
■ n-channel enhancement-mode: VT>0
■ p-channel enhancement-mode: VT<0

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■ The threshold voltage is a complex parameter influenced by several
physical phenomena and material properties. For an n-channel MOSFET, it
can be expressed as:

■ where
■ VFB (Flat-band voltage): This is the gate voltage required to make
the energy bands of the semiconductor flat, meaning there is no band
bending and no electric field at the semiconductor surface.
■ ϕF (Fermi Potential): This term represents the surface potential
required to achieve strong inversion
■ Qox: Charge density in the gate oxide
■ Cox: Gate oxide capacitance per unit area
■ QB:Depletion region charge
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■Drain
T
Current (ID)
■ RECALL from the earlier slides that the MOSFET have three possible
operating modes: cutoff, triode and saturation.
■ In cutoff, the gate-to-source voltage is not greater than the threshold
voltage, and the MOSFET is inactive.
■ In triode, the gate-to-source voltage is high enough to allow current flow
from drain to source, and the nature of the induced channel is such that
the magnitude of the drain current is influenced by the gate-to-source
voltage and the drain-to-source voltage.
■ As the drain-to-source voltage increases, the triode region transitions to
the saturation region, in which drain current is (ideally) independent of
drain-to-source voltage and thus influenced only by the physical
characteristics of the FET and the gate-to-source voltage.
■ The saturation-region relationship between gate-to-source voltage (VGS)
and drain current (ID) is expressed as follows:

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■ The transition to saturation mode occurs because the channel gets
“pinched off” at the drain end as shown in the Figure.
■ Increasing drain-to-source voltage, continue to affect the channel because
the pinch-off point moves closer to the source.
■ The resistance of the channel is inversely proportional to its width-to-
length ratio; reducing the length leads to decreased resistance and hence
higher current flow. Thus, in the saturation-region, the drain current will
increase slightly as the drain-to-source voltage increases. This is called
channel-length modulation.

■ So by incorporating the incremental channel-length reduction into the

original expression:

■ By assuming that the incremental change is much less than the length of
the physical channel, we can rearrange the above equation as follows:

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■ Defining the channel length modulation parameter as lambda, the
modified drain current becomes as follows.

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 This diagram is to
understand the “Pinch-off”
mechanism. NOT required
to draw in exam unless
explicitly asked.

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 MOS Capacitances
■ In a MOS transistor, there is an inter-electrode capacitance between the
terminals. These capacitances are non-linear and are dependent on
voltage.
■ These capacitances can be approximated as simple capacitance models.
These models are used for estimating delay and power consumption of
transistors and mainly used for circuit simulation.
■ Gate overlap capacitance
■ It can be seen that the gate electrode overlaps both the source region and
the drain region at the edges.
■ The two overlap capacitances that arise as a result of this structural
arrangement are called CGD (overlap) and CGS (overlap), respectively.
■ Assuming that both the source and the drain diffusion regions have the
same width W, the overlap capacitances can be found as:

■ Where
■ Note that both of these overlap capacitances do not depend on the bias
conditions, i.e., they are voltage-independent.
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■ Gate-to-Channel Capacitance
■ Now consider the capacitances which result from the interaction between
the gate voltage and the channel charge. Since the channel region is
connected to the source, the drain, and the substrate, we can identify
three capacitances between the gate and these regions, i.e., Cgs, Cgd
and Cgb respectively. Notice that in reality, the gate-to-channel
capacitance is distributed and voltage-dependent.
■ Then, the gate-to-source capacitance Cgs is actually the capacitance seen
between the gate and the source terminals; the gate-to-drain capacitance
Cgd is actually the capacitance seen between the gate and the drain
terminals. A simplified view of their bias-dependence can be obtained by
observing the conditions in the channel region during cut-off, linear, and
saturation modes.
■ In cut-off mode (see Fig. a), there is no conducting channel that links the
surface to the source and to the drain.
■ Therefore, the gate-to-source and the gate-to-drain capacitances are
both equal to zero: Cgs = Cgd= 0.
■ The gate-to-substrate capacitance can be approximated by

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■ In linear-mode (see Fig. b), the channel extends across the MOSFET,
between the source and the drain.
■ Therefore, the distributed gate-to-channel capacitance is shared
equally between the source and the drain, yielding

■ And the conducting channel layer on the surface effectively shields the
substrate from the gate electric field; thus, Cgb = 0.
■ In saturation mode (see Fig. c), the channel layer on the surface does not
extend to the drain, but it is pinched off.
■ Therefore, the gate-to-drain capacitance component is therefore equal to
zero. That is Cgd = 0 .
■ And since the source is still linked to the conducting channel, its shielding
effect also forces the gate-to-substrate capacitance to be zero, Cgb = 0.
■ Finally, the distributed gate-to-channel capacitance as seen between the
gate and the source can be approximated by

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Figure: Schematic representation of MOSFET oxide capacitances during (a) cut-off, (b) linear,
and (c) saturation modes.
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■ Therefore, the complete approximate capacitance values for three operating modes
of the MOS becomes as shown in Table below:

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■MOS
T
Scaling
■ The reduction of the size that is, the dimensions of MOSFETs, is
commonly referred to as scaling.
■ The scaling down of size of MOSFET leads to an improved performance of
VLSI design and higher packing density of circuit on a chip.
■ Dennard's Scaling Law predicts that the basic operational characteristics
of a MOS transistor can be preserved and the performance is improved if
the critical parameters of a device are scaled by a dimensionless factor .
■ These parameters include the following:
■ All dimensions (in the x, y and z directions).
■ Device voltages, and
■ Doping concentration densities
■ Scaling technology has the following three objectives:
■ Increase the transistor density.
■ Reduce the gate delay.
■ Reduce the power consumption.
■ Over the past many years to till date, much effort has been focused
towards the evolution of fabrication process technology and scaling down
of the devices and feature size. So, scaling is an important factor and it is
essential for a VLSI designer to know the scaling of MOS devices

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■ There are two different models available for scaling:
■ Constant electric field (or) full scaling model, and
■ Constant (or) fixed voltage scaling model
■ In full scaling model, all the dimensions of the MOS devices are scaled
by the same factors, keeping the electric field as constant.
■ In fixed voltage scaling, the voltage VDD is kept constant and the
process is scaled.
■ If you ask how scaling is achieved?, the answer is:
■ All the device dimensions (lateral and vertical) are reduced by 1/ S.
■ Concentration densities are increased by S.
■ Device voltages reduced by l/S (not in all scaling methods).
■ Typically l/S = 0.7 (30% reduction in the dimensions)

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■ The following Table summarizes the effect of Full scaling of MOSFET on
dimensions, potentials, and doping densities.

■ The following Table summarizes the

effect of Full scaling of MOSFET
upon key device characteristics.

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■ The following Table summarizes the effect of Constant voltage scaling
of MOSFET on dimensions, potentials, and doping densities.

■ The following Table summarizes the effect of Constant voltage scaling

of MOSFET upon key device characteristics.

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 This diagram is to
understand the Scaling
mechanism. NOT
required to draw in
exam.

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 Second Order & Non-Ideal Effects
■ The long-channel, or ideal, or first-order, or Shockley model relates the
current and voltage for a nMOS transistor in each of the three operating
regions.
■ This model assumes that the channel length is long enough and the
lateral electric field (the field between source and drain) is relatively low,
which is no longer in the case of nanometer devices.
■ The long-channel I-V model equations neglects many effects that are
important to devices with channel lengths below 1 micron (short
channel). Some of these effects includes:
■ (i) Mobility degradation and velocity saturation,
■ (ii) Channel Length Modulation,
■ (ii) Threshold Voltage Effects,
■ (iv) Leakage,
■ (v) Temperature Dependence, and
■ (vi) Geometry Dependence.

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[i] Mobility Degradation and Velocity Saturation
■ Mobility degradation and velocity saturation are two phenomena that
affect the performance of transistors, particularly in MOSFETs, at higher
voltages and shorter channel lengths.
■ Mobility degradation refers to the decrease in carrier mobility due to
increased scattering events caused by stronger electric fields.
■ Velocity saturation occurs when the carrier velocity reaches a maximum
value and no longer increases linearly with the electric field.
■ These effects lead to reduced drain current and impact the overall
performance of integrated circuits
[ii] Channel Length Modulation (CLM)
■ Channel length modulation is a phenomena that affect the performance of
transistors, particularly in MOSFETs, in shorter channel lengths.
■ In the saturation region, the channel in a MOSFET is ideally "pinched-off"
at the drain end, meaning the drain current (IDS) should theoretically be
independent of VDS.
■ However, in reality, as VDS increases further, the electric field from the
drain side pushes the pinch-off point closer to the source. This effectively
shortens the channel length (L).
■ Since channel resistance is proportional to its length, a reduction in length
translates to a decrease in resistance and, consequently, an increase in
IDS. This phenomenon is known as channel length modulation
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[iii] Threshold Voltage Effects
■ Threshold Voltage Effects is a phenomena that affect the performance of
transistors, particularly in MOSFETs, in shorter channel lengths. The
following are such effects:
■ Body Effect
■ The variation of the threshold voltage due to source to substrate
voltage Vsb, is referred to as body effect (or) substrate-bias effect.
■ When a voltage V is applied between the source and body, it increases
the amount of charge required to invert the channel which in tern
increases the threshold voltage
■ Drain- Induced Barrier Lowering (DIBL)
■ The drain voltage Vds, creates an electric field that affects the
threshold voltage. This is called as DIBL effect, especially in short-
channel transistors.
■ DIBL increases the sub threshold leakage at high Vds.
■ Short Channel Effect
■ The threshold voltage typically increases with respect to channel
length. For small channel length L, where the source and drain
depletion regions extend into a significant portion of the channel and
it is called as short channel effect or threshold voltage rolloff.

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[iv] Temperature dependence
■ Threshold voltage typically decreases as temperature increases due to the
effect of temperature on factors like the Fermi-level and band gap energy.
■ This temperature sensitivity can cause variations in circuit performance
and reliability in environments with fluctuating temperatures.
[v] Leakage
■ Leakage current in MOSFETs is the unintended flow of current between
different terminals, primarily between the drain and source when the
device is supposed to be off: The different components are:
■ Subthreshold leakage:
■ This occurs when the gate voltage is below the threshold voltage
(Vth) but still allows a small amount of current to flow due to the
formation of a weak inversion channel.
■ It is a major contributor to leakage in modern devices.
■ Gate oxide tunneling leakage:
■ In short-channel devices with thin gate oxides, electrons can tunnel
through the oxide layer, creating a leakage current between the gate
and the substrate.
■ Reverse bias junction leakage:
■ The drain/source and substrate junctions are reverse-biased during
operation, leading to a small leakage current due to minority carrier
diffusion and drift.

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 Modeling of MOS Transistor – SPICE
Models

Figure . Equivalent circuit structure of the

LEVEL I MOSFET model in SPICE.
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LEVEL I MOSFET model
■ It is based on the square-law equation relating drain current to gate-
source voltage.
■ This model offers a first-order approximation of MOSFET behavior,
assuming the device operates in either the linear or saturation regions.
■ Limitations: It lacks the accuracy needed for modern applications,
particularly those involving short-channel devices, as it doesn't account
for effects like:
■ Channel length modulation
■ Substrate bias
■ Temperature effects
■ Velocity saturation
■ Mobility degradation

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LEVEL 2 MOSFET model
■ To obtain a more accurate model for the drain current, it is necessary to
eliminate some of the simplifying assumptions made in the original LEVEL
1 analysis.
■ Specifically, the bulk depletion charge must be calculated by taking into
account its dependence on the channel voltage.
■ Solving the drain current equation using the voltage-dependent bulk
charge term, the following current-voltage characteristics can be
obtained:

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LEVEL 3 MOSFET model
■ The LEVEL 3 model has been developed for simulation of short-channel
MOS' transistors; it can represent the characteristics of MOSFETs quite
precisely for channel lengths down to 2 um.
■ The current-voltage equations are formulated in the same way as for the
LEVEL 2 model. However, the current equation in the linear region has
been simplified with a Taylor series expansion.
■ This approximation allows the development of more manageable basic
current equations compared to those for the LEVEL 2 model.

■ BSIM - Berkeley Short-Channel IGFET Model

■ The recently developed LEVEL 4 (Berkeley Short-Channel IGFET Model,
or BSIM) model is analytically simple and is based on a small number of
parameters, which are normally extracted from experimental data.
■ Its accuracy and efficiency make it one of the most popular SPICE
MOSFET models at present, especially in the microelectronics industry.
■ Currently, the BSIM3 version is widely used by many companies to
accurately model the electrical behavior of sub-micron MOSFETs
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 NMOS Fabrication Processes
■ NMOS (N-channel Metal-Oxide-Semiconductor) transistors are
fundamental building blocks in integrated circuits. Their fabrication
involves a series of precisely controlled steps to create the various layers
and regions that form the device. The following are the sequence of steps
involved in the NMOS fabrication process
1. Substrate Preparation:
■ The process begins with a highly pure, single-crystal silicon wafer,
typically p-type (doped with boron) to serve as the substrate.
■ This p-type material will form the body of the NMOS transistor.
2. Oxidation (Field Oxide Growth):
■ A relatively thick layer of silicon dioxide (SiO₂) is grown over the
entire wafer surface.
■ This layer, known as the field oxide, acts as an insulator to isolate
different active regions of the chip and prevent unwanted parasitic
transistors.
■ This is typically done through thermal oxidation (heating the wafer in
an oxygen-rich environment).

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3. Photolithography (Masking for Active Areas):
■ The wafer is coated with a uniform layer of a light-sensitive material
called photoresist.
■ A photomask (a transparent plate with opaque patterns) is placed
over the photoresist.
■ The wafer is then exposed to ultraviolet (UV) light. For positive
photoresist, the exposed areas become soluble, while for negative
photoresist, the exposed areas become insoluble.
4. Etching (Field Oxide Etch):
■ The exposed silicon dioxide is etched away using a chemical etchant
(e.g., hydrofluoric acid).
■ This creates "windows" in the field oxide, exposing the bare p-type
silicon substrate in the active areas.
■ The remaining photoresist is then stripped off.

5. Gate Oxidation:
■ A very thin, high-quality layer of silicon dioxide is grown over the
exposed silicon areas. This forms the crucial gate oxide, which will
act as the dielectric insulator for the transistor's gate.
■ The thickness of this oxide is critical for device performance.
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6. Polysilicon Deposition and Patterning (Gate Formation):
■ A layer of polycrystalline silicon (polysilicon) is deposited over the
entire wafer, including the thin gate oxide and the remaining field
oxide. Polysilicon is used as the gate electrode material.
■ Another photolithography step is performed, using a new mask to
define the shape of the gate.
■ The polysilicon layer is then etched, leaving behind the patterned
polysilicon gates for each transistor.
■ This step is "self-aligned" because the gate itself acts as a mask for
the subsequent source/drain doping.
7. N-type Doping (Source and Drain Formation):
■ The entire wafer is then subjected to a heavy n-type doping process,
typically using ion implantation (e.g., phosphorus or arsenic ions).
■ Since the polysilicon gate and the thick field oxide act as masks, the
n-type dopants only penetrate the exposed p-type silicon regions
adjacent to the gate.
■ These highly doped n-type regions become the source and drain
terminals of the NMOS transistor.

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8. Interlayer Dielectric (ILD) Deposition:
■ Another insulating layer, often silicon dioxide (SiO₂) or phosphosilicate
glass (PSG/BPSG), is deposited over the entire wafer, covering the
gate, source, and drain regions.
■ This layer electrically isolates the active regions from subsequent
metal interconnects.
9. Contact Hole Etching:
■ A new photolithography step and etching are performed to create
contact holes or "vias" through the interlayer dielectric layer.
■ These openings expose specific areas of the source, drain, and gate,
where electrical connections need to be made.
10. Metallization:
■ A layer of metal, typically aluminum, is deposited over the entire
wafer, filling the contact holes and covering the ILD.
■ A final photolithography step is used to pattern the metal layer,
creating the desired interconnection lines (wires) that connect
different transistors and form the circuit.
■ The unwanted metal is then etched away.
11. Passivation:
■ A final protective insulating layer, called a passivation layer (often
silicon nitride), is deposited over the entire chip surface.
■ This layer protects the device from contamination, moisture, and
mechanical damage.
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1. Substrate Preparation


2. Oxidation (Field Oxide Growth)


3. Photolithography (Masking for Active Areas)


4. Etching (Field Oxide Etch):

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 
5. Gate Oxidation:

6. Polysilicon Deposition and


Patterning (Gate Formation):


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7. N-type Doping (Source and Drain Formation)


8. Interlayer Dielectric (ILD) Deposition


9. Contact Hole Etching

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 11. Passivation

10. Metallization
NOTE: Advised that
1. The diagram on 4 slides describe
the complete fabrication steps.

2. In EXAM, you draw only those

diagrams with tick () mark is
enough

3. If asked in 8 marks, only

theoretical steps will suffice.

 4. If asked in 16 marks, then write

both theoretical steps along with
diagrams

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 PMOS Fabrication Processes
■ PMOS fabrication process is same as NMOS fabrication process explained
as above in the previous 8 slides EXCEPT the following simple changes in
two steps:
■ In step1: Substrate Preparation – “n-type” substrate is taken
■ In step 7: Source and Drain formation – “p-type” doping is performed.
■ And, make corresponding changes for all the diagrams: especially for,
substrate materials as “n-type” and doping as “p-type”

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 Layout Design Rules
■ Layout design is a schematic of Integrated Circuit (1C), which describes
the exact placement of the components for fabrication.
■ The design rules (or) set of layout rules are required for a ready
translation of circuit concepts which is usually in stick diagram (or)
symbolic form into an actual mask layout in silicon.
■ Layout design rules describes how small features can be and how closely
they can be reliably packed in a particular manufacturing process.
■ Design Rule Check (DRC) program looks for design rule violations in the
layout. It checks for minimum spacing and minimum size which ensures
the combinations of layers from legal components
■ Designer often describes a process by its feature size which refers to
minimum transistor length, so Lambda (λ) is half the feature size. The
transistor dimensions always specified by Width/Length ratio.
■ This length (i.e. transistor channel length) is the distance between the
source and drain of a transistor and it is set by the minimum width of a
polysilicon wire.
■ The following Table shows the Lambda-based layout rules for any custom
design

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 This diagram is a sample illustration
showing the intra-layer design rules
(widths and spacing) for your
understanding. OPTIONAL to draw/show
in exam.

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 Full-Custom Mask Layout Design
■ The physical (mask layout) design of CMOS logic gates is an iterative
process which starts with the circuit topology (to realize the desired logic
function) and the initial sizing of the transistors (to realize the desired
performance specifications).
■ At this point, the designer can only estimate the total parasitic load at the
output node, based on the fanout, the number of devices, and the
expected length of the interconnection lines.
■ If the logic gate contains more than 4 to 6 transistors, the topological
graph representation and the Euler-path method allow the designer to
determine the optimum ordering of the transistors.
■ A simple stick diagram layout can now be drawn, showing the locations of
the transistors, the local interconnections between the transistors, and the
locations of the contacts.
■ After a topologically feasible layout is found, the mask layers are drawn
(using a layout editor tool) according to the layout design rules.
■ This procedure may require several small iterations in order to
accommodate all the design rules, but the basic topology should not
change very significantly.

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■ Following the final DRC (Design Rule Check), a circuit extraction procedure
is performed on the finished layout to determine the actual transistor
sizes, and more importantly, the parasitic capacitances at each node.
■ The result of the extraction step is usually a detailed SPICE input file,
which is automatically generated by the extraction tool.
■ Now, the actual performance of the circuit can be determined by
performing a SPICE simulation, using the extracted net-list.
■ If the simulated circuit performance (e. g., transient response times or
power dissipation) do not match the desired specifications, the layout
must be modified and the whole process must be repeated.
■ The layout modifications are usually concentrated on the (W/L) ratios of
the transistors (transistor resizing), since the width-to-length ratios of the
transistors determine the device transconductance and the parasitic
source/drain capacitances.
■ The designer may also decide to change parts or all of the circuit topology
in order to reduce the parasitics.
■ The flow diagram of this iterative process is shown in FIGURE.

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 Stick Diagrams
■ VLSI design aims to translate circuit concepts onto silicon. The stick
diagrams are a means of capturing topography and layer information
using simple diagrams.
■ Stick diagram are used to convey the layer information through the use of
colour code and it resembles the actual layout.
■ Stick diagrams uses 'sticks' or lines' to represent the devices and
conductors.
■ Stick diagrams acts as an interface between the symbolic circuit and
actual layout.
■ The need of stick diagram are:
■ To minimize the time required for layout
■ To estimate an area before committing to a full layout
■ To find out whether there is any problem in the layout and we can
resolve the problem if any and can save time
■ Stick diagrams the basic building block for designing complex circuits, and
easy to draw because they do not need to be drawn to scale.
■ Stick diagram are useful in planning the layout and routing of integrated
circuits.
■ In a stick diagram, every line of a conducting material layer is
represented by a line of a distinct colour.
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■ The following Table summarizes encoding of stick diagram for CMOS

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■ In a stick diagram, nMOS transistor is formed whenever poly crosses n-
diffusion and pMOS transistor is formed whenever poly crosses p-
diffusion.

■ You will learn more Stick diagram exercises (for complex circuits!) in unit
3 as per the syllabus flow.

Advise you to Remember the terms, understand the underlying concepts,

prepare and speak/practise yourself.
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