Computer Architecture
TPC 4 0 4
Prof. (Dr.) Mahesh M
SENSE
VIT-AP
Mahesh.m@[Link]
Course Pre-requisites
Digital logic design
Chap. 1: Digital Logic Circuits
• Logic Gates, • Boolean Algebra
• K-Map Simplification, • Combinational Circuits
• Filp-Flops, • Sequential Circuits
Chap. 2: Digital Components
• Integrated Circuits, • Decoders, • Multiplexers
• Registers, • Shift Registers, • Binary Counters
• Memory Unit
Chap. 3: Data Representation
• Data Types, • Complements Please refer M. Morris Mano, Computer System
• Fixed Point Representation Architecture, Pearson Education, Third Edition
• Floating Point Representation
• Other Binary Codes
Text Book:
William Stallings, Computer Organization and
Architecture: Designing for Performance,
Pearson Education, Tenth Edition,2013
Reference Books:
1. M. Morris Mano, Rajib Mall, Computer System Architecture, Pearson Education Third Edition,2017.
2. Carl Hamacher, Zvonkovranesic, Safwat Zaky , Computer Organization, McGraw Hill, Fifth Edition,2011.
Structure of Computing Device
• The Computer
• CPU
• Controls the operation of the
computer and performs its data
processing functions.
• Main memory
• Stores data
• Fast Page Mode RAM
• Synchronous DRAM
• Extended data output) RAM
• I/O
• Moves data between the computer
and its external environment
• System interconnection
• Provides for communication among
CPU, main memory, and I/O
There are four main structural components of the
computer:
CPU – controls the operation of
the computer and performs its data
processing functions
Main Memory – stores data
I/O – moves data between the
computer and its external
environment
System Interconnection – some
mechanism that provides for
communication among CPU, main
memory, and I/O
MOTHERBOARD
Main memory chips
Processor
I/O chips chip
Multi-Core Core
PROCESSOR CHIP
Core Core Core
Processor
L3 cache L3 cache
Core Core Core Core
Structure CORE
Arithmetic
Instruction and logic Load/
logic unit (ALU) store logic
L1 I-cache L1 data cache
L2 instruction L2 data
cache cache
Figure 1.2 Simplified View of Major Elements of a Multicore Computer
Figure 1.3
Motherboard with Two Intel Quad-Core Xeon Processors
Figure 1.4
zEnterprise EC12
Processor Unit (PU)
Chip Diagram
Computer Architecture
Computer Organization
• Attributes of a • Instruction set,
system visible to number of bits
the programmer used to represent
• Have a direct various data types,
impact on the I/O mechanisms,
logical execution of techniques for
a program addressing
Architectural memory
Computer
attributes
Architecture
include:
Organizational
Computer
attributes
• Hardware details Organization
include:
transparent to the
programmer, • The operational units
control signals, and their
interfaces between interconnections that
the computer and realize the
peripherals, architectural
memory specifications
technology used
Function
• There are four basic functions that a computer can perform:
• Data processing
• Data may take a wide variety of forms and the range of processing requirements is broad
• Data storage
• Short-term
• Long-term
• Data movement
• Input-output (I/O) - when data are received from or delivered to a device (peripheral) that is
directly connected to the computer
• Data communications – when data are moved over longer distances, to or from a remote
device
• Control
• A control unit manages the computer’s resources and orchestrates the performance of its
functional parts in response to instructions
Function
• All computer functions are:
• Data processing
• Data storage
• Data movement
• Control
Operations (1) Data movement
Operations (2) Storage
Operation (3) Processing from/to storage
Operation (4) Processing from storage to I/O
Structure
• The Computer
• CPU
• Controls the operation of the
computer and performs its data
processing functions.
• Main memory
• Stores data
• Fast Page Mode RAM
• Synchronous DRAM
• Extended data output) RAM
• I/O
• Moves data between the computer
and its external environment
• System interconnection
• Provides for communication among
CPU, main memory, and I/O
History of Computers
First Generation: Vacuum Tubes
IAS-1952
• Vacuum tubes were used for digital logic
elements and memory
• IAS computer
• Fundamental design approach was the stored program
concept
• Attributed to the mathematician John von Neumann ENIAC-1940
• First publication of the idea was in 1945 for the EDVAC
• Design began at the Princeton Institute for Advanced
Studies
• Completed in 1952
• Prototype of all subsequent general-purpose computers
Turning Computer-1936
Central processing unit (CPU)
Arithmetic-logic unit (CA)
AC MQ
Input-
Arithmetic-logic output
circuits
equipment
(I, O)
MBR
Instructions
and data
Instructions
and data
M(0)
M(1)
M(2)
M(3) PC IBR
M(4) AC: Accumulator register
MQ: multiply-quotient register
MBR: memory buffer register
IBR: instruction buffer register
MAR IR PC: program counter
MAR: memory address register
Main
IR: insruction register
memory
(M)
Control
Control
circuits
signals
M(4092)
M(4093)
M(4095)
Program control unit (CC)
Addresses
Figure 1.6 IAS Structure
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
0 1 39
sign bit (a) Number word
left instruction (20 bits) right instruction (20 bits)
0 8 20 28 39
opcode (8 bits) address (12 bits) opcode (8 bits) address (12 bits)
(b) Instruction word
Figure 1.7 IAS Memory Formats
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights
reserved.
Registers
Memory buffer register • Contains a word to be stored in memory or sent to the I/O unit
(MBR) • Or is used to receive a word from memory or from the I/O unit
Memory address register • Specifies the address in memory of the word to be written from or
(MAR) read into the MBR
Instruction register (IR) • Contains the 8-bit opcode instruction being executed
Instruction buffer register • Employed to temporarily hold the right-hand instruction from a
(IBR) word in memory
• Contains the address of the next instruction pair to be fetched from
Program counter (PC) memory
Accumulator (AC) and • Employed to temporarily hold operands and results of ALU
multiplier quotient (MQ) operations
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reserved.
History of Computers
Second Generation: Transistors
• Smaller
• Cheaper
• Dissipates less heat than a vacuum tube
• Is a solid state device made from silicon
• Was invented at Bell Labs in 1947
• It was not until the late 1950’s that fully transistorized computers
were commercially available
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reserved.
Table 1.2
Computer Generations
Approximate Typical Speed
Generation Dates Technology (operations per second)
1 1946–1957 Vacuum tube 40,000
2 1957–1964 Transistor 200,000
3 1965–1971 Small and medium scale 1,000,000
integration
4 1972–1977 Large scale integration 10,000,000
5 1978–1991 Very large scale integration 100,000,000
6 1991- Ultra large scale integration >1,000,000,000
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights
reserved.
Second Generation Computers
• Introduced:
• More complex arithmetic and logic units and control
units
• The use of high-level programming languages
• Provision of system software which provided the
ability to:
• Load programs
• Move data to peripherals
• Libraries perform common computations
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reserved.
IBM 7094 computer Peripheral devices
Mag tape
units
CPU
Card
punch
Data
channel Line
printer
Card
reader
Drum
Multi- Data
plexor channel
Disk
Data
Disk
channel
Hyper-
tapes
Memory Data Teleprocessing
channel equipment
Figure 1.9 An IBM 7094 Configuration
History of Computers
Third Generation: Integrated Circuits
• 1958 – the invention of the integrated circuit
• Discrete component
• Single, self-contained transistor
• Manufactured separately, packaged in their own
containers, and soldered or wired together onto
masonite-like circuit boards
• Manufacturing process was expensive and
cumbersome
• The two most important members of the third generation were the
IBM System/360 and the DEC PDP-8
Wafer
Chip
Gate
Packaged
chip
Figure 1.11 Relationship Among Wafer, Chip, and Gate
Moore’s Law
t
ui
g
ed of
rc
or in
ga w
d
st rk
ci
ul la
at n
te
gr tio
si o
’s
an w
om re
te n
tr irst
in ve
p r oo
In
M
F
100 bn
10 bn
1 bn
100 m
10 m
100,000
10.000
1,000
100
10
1
1947 50 55 60 65 70 75 80 85 90 95 2000 05 11
Figure 1.12 Growth in Transistor Count on Integrated Circuits
(DRAM memory)
Boolean Binary
Input logic Output Input storage Output
function cell
Read
Activate Write
signal
(a) Gate (b) Memory cell
Figure 1.10 Fundamental Computer Elements
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reserved.
IBM System/360
• Announced in 1964
• Product line was incompatible with older IBM
machines
• Was the success of the decade and cemented
IBM as the overwhelmingly dominant computer
vendor
• The architecture remains to this day the
architecture of IBM’s mainframe computers
• Was the industry’s first planned family of
computers
• Models were compatible in the sense that a program
written for one model should be capable of being
executed by another model in the series
Console Main I/O I/O
CPU
controller memory module module
Omnibus
Figure 1.13 PDP-8 Bus Structure
+ LSI
Large
Scale
Later Integration
Generations
VLSI
Very Large
Scale
Integration
ULSI
Ultra Large
Semiconductor Memory Scale
Microprocessors Integration
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Semiconductor Memory
In 1970 Fairchild produced the first relatively capacious semiconductor memory
Chip was about the size of a Could hold 256 bits of
Non-destructive Much faster than core
single core memory
In 1974 the price per bit of semiconductor memory dropped below the price per bit of core
memory
There has been a continuing and rapid decline in memory
Developments in memory and processor technologies
cost accompanied by a corresponding increase in physical
changed the nature of computers in less than a decade
memory density
Since 1970 semiconductor memory has been through 13 generations
Each generation has provided four times the storage density of the previous generation, accompanied by declining cost per
bit and declining access time
Microprocessors
• The density of elements on processor chips
continued to rise
• More and more elements were placed on each chip so that
fewer and fewer chips were needed to construct a single
computer processor
• 1971 Intel developed 4004
• First chip to contain all of the components of a CPU on a
single chip
• Birth of microprocessor
• 1972 Intel developed 8008
• First 8-bit microprocessor
• 1974 Intel developed 8080
• First general purpose microprocessor
• Faster, has a richer instruction set, has a large addressing
capability © 2016 Pearson Education, Inc., Hoboken, NJ. All rights
reserved.
Evolution of Intel Microprocessors
4004 8008 8080 8086 8088
Introduced 1971 1972 1974 1978 1979
Clock speeds 108 kHz 108 kHz 2 MHz 5 MHz, 8 MHz, 10 5 MHz, 8 MHz
MHz
Bus width 4 bits 8 bits 8 bits 16 bits 8 bits
Number of 2,300 3,500 6,000 29,000 29,000
transistors
Feature size 10 8 6 3 6
(µm)
Addressable 640 Bytes 16 KB 64 KB 1 MB 1 MB
memory
(a) 1970s Processors
Evolution of Intel Microprocessors
80286 386TM DX 386TM SX 486TM DX
CPU
Introduced 1982 1985 1988 1989
Clock speeds 6 MHz - 12.5 16 MHz - 33 16 MHz - 33 25 MHz - 50
MHz MHz MHz MHz
Bus width 16 bits 32 bits 16 bits 32 bits
Number of transistors
134,000 275,000 275,000 1.2 million
Feature size (µm) 1.5 1 1 0.8 - 1
Addressable 16 MB 4 GB 16 MB 4 GB
memory
Virtual
1 GB 64 TB 64 TB 64 TB
memory
Cache — — — 8 kB
(b) 1980s Processors
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reserved.
Evolution of Intel Microprocessors
486TM SX Pentium Pentium Pro Pentium II
Introduced 1991 1993 1995 1997
16 MHz - 33 60 MHz - 166 150 MHz - 200 200 MHz - 300
Clock speeds
MHz MHz, MHz MHz
Bus width 32 bits 32 bits 64 bits 64 bits
Number of
1.185 million 3.1 million 5.5 million 7.5 million
transistors
Feature size (µm) 1 0.8 0.6 0.35
Addressable
4 GB 4 GB 64 GB 64 GB
memory
Virtual memory 64 TB 64 TB 64 TB 64 TB
512 kB L1 and 1
Cache 8 kB 8 kB 512 kB L2
MB L2
(c) 1990s Processors
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reserved.
Evolution of Intel Microprocessors
Core 2 Duo Core i7 EE
Pentium III Pentium 4
4960X
Introduced 1999 2000 2006 2013
Clock speeds 450 - 660 MHz 1.3 - 1.8 GHz 1.06 - 1.2 GHz 4 GHz
Bus
wid 64 bits 64 bits 64 bits 64 bits
th
Number of
9.5 million 42 million 167 million 1.86 billion
transistors
Feature size (nm) 250 180 65 22
Addressable
64 GB 64 GB 64 GB 64 GB
memory
Virtual memory 64 TB 64 TB 64 TB 64 TB
Cache 512 kB L2 256 kB L2 2 MB L2 1.5 MB L2/15
MB L3
Number of cores 1 1 2 6
(d) Recent Processors
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reserved.
The Evolution of the Intel x86 Architecture
• Two processor families are the Intel x86 and the ARM architectures
• Current x86 offerings represent the results of decades of design effort
on complex instruction set computers (CISCs)
• An alternative approach to processor design is the reduced
instruction set computer (RISC)
• ARM architecture is used in a wide variety of embedded systems and
is one of the most powerful and best-designed RISC-based systems on
the market
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reserved.
RISC Attributes
The main characteristics of CISC microprocessors are:
• Extensive instructions.
• Complex and efficient machine instructions.
• Microencoding of the machine instructions.
• Extensive addressing capabilities for memory operations.
• Relatively few registers.
In comparison, RISC processors are more or less the opposite of the above:
• Reduced instruction set.
• Less complex, simple instructions.
• Hardwired control unit and machine instructions.
• Few addressing schemes for memory operands with only two basic instructions, LOAD and
• STORE
• Many symmetric registers which are organised into a register file.
CISC versus RISC
CISC RISC
Emphasis on hardware Emphasis on software
Includes multi-clock Single-clock,
complex instructions reduced instruction only
Memory-to-memory: Register to register:
"LOAD" and "STORE" "LOAD" and "STORE"
incorporated in instructions are independent instructions
Small code sizes, Low cycles per second,
high cycles per second large code sizes
Transistors used for storing Spends more transistors
complex instructions on memory registers
More Details about IAS
Von Neumann/Turing
• Stored Program concept
• Main memory storing programs and data
• ALU operating on binary data
• Control unit interpreting instructions from memory and executing
• Input and output equipment operated by control unit
• Princeton Institute for Advanced Studies (IAS)
• Completed 1952
Structure of von Neumann machine
CA: Central Arithmetic
CC: Central Control
IAS – Memory format
• 1000 --- 40 bit words
• Binary number Main memory
• 2 x 20 bit instructions
Structure of IAS – detail
• Set of registers (storage in CPU)
• Memory Buffer Register
• Memory Address Register
• Instruction Register
• Instruction Buffer Register
• Program Counter
• Accumulator
• Multiplier Quotient
• Memory buffer register (MBR): Contains a word to be stored in memory or sent to the I/O unit, or is
used to receive a word from memory or from the I/O unit.
• Memory address register (MAR): Specifies the address in memory of the word to be written from or
read into the MBR.
• Instruction register (IR): Contains the 8-bit opcode instruction being executed.
• Instruction buffer register (IBR): Employed to hold temporarily the right hand instruction from a
word in memory.
• Program counter (PC): Contains the address of the next instruction-pair to be fetched from memory.
• Accumulator (AC) and multiplier quotient (MQ): Employed to hold temporarily operands and results
of ALU operations. For example, the result of multiplying two 40-bit numbers is an 80-bit number; the
most significant 40 bits are stored in the AC and the least significant in the MQ.
IAS Instruction set (21 instructions)
The IAS computer had a total of 21 instructions, which
are listed in Table.
These can be grouped as follows:
• Data transfer: Move data between memory and ALU
registers or between two ALU registers.
• Unconditional branch: Normally, the control unit
executes instructions in sequence from memory. This
sequence can be changed by a branch instruction,
which facilitates repetitive operations.
• Conditional branch: The branch can be made
dependent on a condition, thus allowing decision
points.
• Arithmetic: Operations performed by the ALU.
• Address modify: Permits addresses to be computed in
the ALU and then inserted into instructions stored in
memory. This allows a program considerable
addressing flexibility.
J. Robert Oppenheimer and John von Neumann in front of the
IAS machine
P1
1. MAR<--PC
Example of
2. MBR<--M[MAR]
3. IBR<--MBR[20:39]
addition
4. IR<--MBR[0:7] 1. 1. LOAD M(X) 500, ADD M(X) 501 (PC=1)
5. MAR<--MBR[8:19] 2. 2. STOR M(X) 500, Other instruction (PC=2)
6. MBR<--M[MAR] 3. …..
7. AC<--MBR 4. 500= 3
8. IR<--IBR[0:7] 5. 501= 4
9. MAR<--IBR[8:19]
[Link]<--PC+1 PC
[Link]<--M[MAR]
MAR
[Link]<--AC+MBR
[Link]<--PC MBR
[Link]<--M[MAR] IR
[Link]<--MBR[20:39] IBR
[Link]<--MBR[0:7] AC
[Link]<--MBR[8:19]
[Link]<--AC
19.M[MAR]<--MBR
Explanation of instruction cycle
• The IAS operates by repetitively performing an instruction cycle, as shown in
last Figure. Each instruction cycle consists of two subcycles.
• During the fetch cycle, the opcode of the next instruction is loaded into the IR
and the address portion is loaded into the MAR. This instruction may be taken
from the IBR, or it can be obtained from memory by loading a word into the
MBR, and then down to the IBR, IR, and MAR.
• Once the opcode is in the IR, the execute cycle is performed.
• Control circuitry interprets the opcode and executes the instruction by sending
out the appropriate control signals to cause data to be moved or an operation
to be performed by the ALU.
Instruction cycle
P2
OPCODE OPERAND
00000001 000000000010
First, the CPU must make access memory to fetch the instruction. The
instruction contains the address of the data we want to load. During the execute
phase accesses memory to load the data value located at that address for a total
of two trips to memory.
P3
P3
The vectors A, B, and C are each
stored in 1,000 continuous
locations in memory, beginning
at locations 1001, 2001, and
3001, respectively. The program
begins with the left half of
location 3. A counting variable N
is set to 999 and decremented
after each step until it reaches -1.
Thus, the vectors are processed
from high location to low
location.
0 15 a
Example 3 15 b
2c
3 begin
4 . If (a >=b)
main () {
4 load M(0)
int a=15, b=5, c; 5 sub M(1)
if (a >= b) 6 jump+ M(8)
7 jump M(12)
c = a – b;
8 .true, c=a-b
else 8 load M(0)
c = a + b; 9 sub M(1)
10 stor M(2)
} 11 jump M(15)
12 .false c = a+b
12 load M(0)
13 add M(1)
14 stor M(2)
15 halt
01
1 10
Example 6 (continued) 22
32
a
b
4i
5 begin
main () { 6 . I =1
7 load M(0)
int a=2, b=2, I; 8 stor M(4)
I = 1; 9 . while (I < 10)
10 load M(4)
while (I < 10) { 11 sub M(1)
12 jump+ M(22)
a = a +b; 13 . a = a +b
I = I +1; 14 load M(2)
15 add M(3)
} 16 stor M(2)
} 17 . I=I+1
18 load M(4)
19 add M(0)
20 stor M(4)
21 jump M(10)
22 halt
0 15 a
Example 3 15 b
2c
3 begin
// If (a >b)
main () {
4 load M(0)
int a=15, b=5, c; 5 sub M(1)
if (a > b) 6 jump+ M(8)
7 jump M(11)
c = a;
// true, c=a-b
} 8 load M(0)
9 stor M(2)
10 jump M(15)
11 halt