Rectifier Circuit Characteristics Explained
Rectifier Circuit Characteristics Explained
1T
T 0
Vdc Vd (wt)
The effective (or) R.M.S. current squared ofa periodic function of time is given by the area of one cycle
of the curve, which represents the square of the function divided by the base.
1T 2
T 0
Vrms V d (wt)
peakvalue
Peak factor =
rmsvalue
iv) Form factor:
Rmsvalue
Form factor=
averagevalue
v) Ripple Factor ( ) :
It is defined as ration of R.M.S. value of a.c. component to the d.c. component in the output is known
as “Ripple Factor”.
Vac
Vdc
Vac Vrms
2
Vdc2
vi) Efficiency ( ):
It is the ratio of d.c output power to the a.c. input power. It signifies, how efficiently the rectifier circuit
converts a.c. power into d.c. power.
o / p power
i / p power
The d.c. power to be delivered to the load in a rectifier circuit decides the rating of the
Transformer used in the circuit. So, transformer utilization factor is defined as
Pdc
TUF
pac(rated)
ix) % Regulation:
The variation of the d.c. output voltage as a function of d.c. load current is called regulation. The
percentage regulation is defined as
VNL VFL
% Re gulation *100
VFL
CLASSIFICATION OF RECTIFIERS
Using one or more diodes in the circuit, following rectifier circuits can be designed.
1) Half - Wave Rectifier
2) Full – Wave Rectifier
3) Bridge Rectifier
HALF-WAVE RECTIFIER:
A Half – wave rectifier as shown in fig 1.2 is one, which converts a.c. voltage into a pulsating voltage
using only one half cycle of the applied a.c. voltage.
Operation:
For the positive half-cycle of input a.c. voltage, the diode D is forward biased and hence it conducts.
Now a current flows in the circuit and there is a voltage drop across RL. The waveform of the diode
current (or) load current is shown in fig 3.
For the negative half-cycle of input, the diode D is reverse biased and hence it does not
Conduct. Now no current flows in the circuit i.e., i=0 and Vo=0. Thus for the negative half- cycle no
power is delivered to the load.
Analysis:
1. DC output current
2. DC Output voltage
3. R.M.S. Current
4. R.M.S. voltage
5. Rectifier Efficiency (η )
6. Ripple factor (γ )
7. Peak Factor
8. % Regulation
9. Transformer Utilization Factor (TUF)
10. form factor
11. o/p frequency
i) AVERAGE VOLTAGE
1T
Vdc Vd (wt)
T0
1 2
Vdc
T V ( )d
0
1 2
Vdc V ( )d
2
1
Vdc
2 0
V m sin(wt)
Vm
Vdc
ii).AVERAGE CURRENT:
Im
I dc
iii) RMS VOLTAGE:
1T
Vrms
T 0
V 2 d (wt)
2
1
2
Vrms (Vmsim(wt)) d2 (wt)
0
Vm
Vrms
2
IV) RMS CURRENT
Im
I rms
V) PEAK FACTOR
peakvalue
Peak factor =
rmsvalue
Vm
Peak Factor =
(Vm / 2)
Peak Factor =2
Rmsvalue
Form factor=
averagevalue
(Vm / 2)
Form factor=
Vm /
Form Factor =1.57
Vac
vii) Ripple Factor:
Vdc
Vac Vrms
2
Vdc2
V 2 V 2
rms dc
Vac
2
Vrms
1
Vdc2
1.21
viii) Efficiency ( ):
o / ppower
*100
i / ppower
pac
= *100
Pdc
=40.8
It is defined as the maximum reverse voltage that a diode can withstand without destroying the
junction. The peak inverse voltage across a diode is the peak of the negative half- cycle. For half-wave
rectifier, PIV is Vm.
i) AVERAGEVOLTAGE
1T
Vrms
T 0
V 2 d (wt)
2
1
2
Vrms (Vmsim(wt)) d2 (wt)
0
IV) RMS CURRENT
2Im
I rms
V) PEAK FACTOR
peakvalue
Peak factor =
rmsvalue
Vm
Peak Factor =
(Vm / 2)
Peak Factor =2
Rms value
Form factor=
averagevalue
viii) Efficiency ( ):
o / ppower
*100
i / ppower
ix) Transformer Utilization Factor (TUF):
The d.c. power to be delivered to the load in a rectifier circuit decides the rating of the transformer
used in the circuit. So, transformer utilization factor is defined as
pdc
TUF
Pac(rated)
.
Advantages
BRIDGE RECTIFIER.
Another type of circuit that produces the same output waveform as the full wave rectifier circuit
above, is that of the Full Wave Bridge Rectifier. This type of single phase rectifier uses four individual
rectifying diodes connected in a closed loop "bridge" configuration to produce the desired output. The
main advantage of this bridge circuit is that it does not require a special centre tapped transformer,
thereby reducing its size and cost. The single secondary winding is connected to one side of the diode
bridge network and the load to the other side as shown below.
During the negative half cycle of the supply, diodes D3 and D4 conduct in series (fig 8), but diodes D1
and D2 switch "OFF" as they are now reverse biased. The current flowing through the load is the same
direction as before.
As the current flowing through the load is unidirectional, so the voltage developed across the load is
also unidirectional the same as for the previous two diode full-wave rectifier, therefore the average DC
voltage across the load is 0.637Vmax. However in reality, during each half cycle the current flows
through two diodes instead of just one so the amplitude of the output voltage is two voltage drops ( 2
x 0.7 = 1.4V ) less than the input V MAX amplitude. The ripple frequency is now twice the supply
frequency (e.g. 100Hz for a 50Hz supply)
FILTERS
The output of a rectifier contains dc component as well as ac component. Filters are used to minimize
the undesirable ac i.e., ripple leaving only the dc component to appear at the output.
VT
U
SY
N
C
.IN
VT
U
SY
N
C
.IN
VT
U
SY
N
C
.IN
VT
U
SY
N
C
.IN
Coupling Schemes
The resistor RL is used as a load impedance. The input capacitor C in present at the initial
stage of the amplifier couples AC signal to the base of the transistor. The capacitor C C is the
coupling capacitor that connects two stages and prevents DC interference between the
stages and controls the shift of operating point. The figure below shows the circuit diagram
of RC coupled amplifier.
The important point that has to be noted here is that the total gain is less than the product
of the gains of individual stages. This is because when a second stage is made to follow the
first stage, the effective load resistance of the first stage is reduced due to the shunting
As we consider a two stage amplifier here, the output phase is same as input. Because the
phase reversal is done two times by the two stage CE configured amplifier circuit.
From the above graph, it is understood that the frequency rolls off or decreases for the
frequencies below 50Hz and for the frequencies above 20 KHz. whereas the voltage gain
for the range of frequencies between 50Hz and 20 KHz is constant.
We know that,
XC=1/2πfc
It means that the capacitive reactance is inversely proportional to the frequency.
At High frequencies (i.e. above 20 KHz):Again considering the same point, we know that
the capacitive reactance is low at high frequencies. So, a capacitor behaves as a short
The circuit is simple and has lower cost because it employs resistors and capacitors
which are cheap.
The voltage and power gain are low because of the effective load resistance.
Due to poor impedance matching, RC coupling is rarely used in the final stages.
When they are coupled to make a multistage amplifier, the high output impedance of one
stage comes in parallel with the low input impedance of next stage. Hence, effective load
resistance is decreased. This problem can be overcome by a transformer coupled
amplifier.
The coupling transformer T1 is used to feed the output of 1ststage to the input of 2nd stage.
The collector load is replaced by the primary winding of the transformer. The secondary
winding is connected between the potential divider and the base of 2 ndstage, which
provides the input to the 2nd stage. Instead of coupling capacitor like in RC coupled
amplifier, a transformer is used for coupling any two stages, in the transformer coupled
amplifier circuit.
The figure below shows the circuit diagram of transformer coupled amplifier.
The potential divider network R1 and R2 and the resistor Re together form the biasing and
stabilization network. The emitter by-pass capacitor Ce offers a low reactance path to the
signal. The resistor RL is used as a load impedance. The input capacitor C in present at the
initial stage of the amplifier couples AC signal to the base of the transistor. The capacitor
The transformer which is used as a coupling device in this circuit has the property of
impedance changing, which means the low resistance of a stage (or load) can be reflected
as a high load resistance to the previous stage. Hence the voltage at the primary is
transferred according to the turns ratio of the secondary winding of the transformer.
This transformer coupling provides good impedance matching between the stages of
amplifier. The transformer coupled amplifier is generally used for power amplification.
At low frequencies, the reactance of primary begins to fall, resulting in decreased gain. At
high frequencies, the capacitance between turns of windings acts as a bypass condenser to
reduce the output voltage and hence gain.
So, the amplification of audio signals will not be proportionate and some distortion will also
get introduced, which is called as Frequency distortion.
Though the gain is high, it varies considerably with frequency. Hence a poor
frequency response.
Applications
The following are the applications of a transformer coupled amplifier −
The other type of coupling amplifier is the direct coupled amplifier, which is especially used
to amplify lower frequencies, such as amplifying photo-electric current or thermo-couple
current or so.
As no coupling devices are used, the coupling of the amplifier stages is done directly and
hence called as Direct coupled amplifier.
Construction
The figure below indicates the three stage direct coupled transistor amplifier. The output
of first stage transistor T1 is connected to the input of second stage transistor T2.
Operation
The input signal when applied at the base of transistor T1, it gets amplified due to the
transistor action and the amplified output appears at the collector resistor Rc of transistor
T1. This output is applied to the base of transistor T2 which further amplifies the signal. In
this way, a signal is amplified in a direct coupled amplifier circuit.
Advantages
The advantages of direct coupled amplifier are as follows.
The circuit is of low cost because of the absence of expensive coupling devices.
Disadvantages
The disadvantages of direct coupled amplifier are as follows.
Under reverse bias condition the capacitance at the junction is called transition or space
charge capacitance.
Under forward bias condition the capacitance is called diffusion or storage capacitance.
At high frequencies, BJT cannot be analysed by h-parameters.
Giacolleto model - hybrid π equivalent ckt
Desirable fractures of hybrid π equivalent circuit (ckt)
(1) The value of components in the equivalent ckt. are independent of frequencies.
(2) The values of all the resistive components in the equivalent ckt. can be determined
from the known or Specified values of h-parameters at low frequencies.
(3) The results obtained by using this equivalent ckt. Agrees with the experimental
result.
The components of the equivalent ckt. exist in the form of π hence the name.
For small signal behaviour the transistor at its input port behaves as a resistor.
Because the base (B) is lightly doped all the depletion region lies entirely in the Base region.
So, when the collector.
voltage is increased the depletion region in the base increases.
The High frequency model parameters of a BJT in terms of low frequency hybrid parameters
is given below
Transconductance gm = Ic/Vt
Internal Base node to emitter resistance rb’e = hfe/ gm = (hfe* Vt )/ Ic
Internal Base node to collector resistance rb’e = (hre* rb’c) / (1- hre) assuming hre << 1 it
reduces to rb’e = (hre* rb’c)
Base spreading resistance rbb’ = hie – rb’e = hie – (hfe* Vt )/ Ic
Collector to emitter resistance rce = 1 / ( hoe – (1+ hfe)/rb’c)
(1) is in shunt with short circuit and behaves as open circuit and hence is removed from
the equivalent circuit.
(2) rb’e | | rb’c rb’e
At f = 0, Ai = - hfe
|Ai| = at f = fT
Assumptions :
1) Both input and output loop contain RC ckt. the RC product of input loop is larger than
that of output loop and
determines the bandwidth of (3dB frequency) of the amplifier. Consequently the
rce = 80K
(4) C = Ce + CC (1-K)
= Ce + CC (1 + gm)
Final equivalent ckt.
At f = 0, AI = -hfe
For f = 0, jωc
C = Ce + CC (1 + gm RL) -------------(5)
(b) Taking source resistance into account
C = Ce + CC (1 + gmRL) --------(9)
Voltage gain taking source resistance into consideration
Problem - = fH = 50 * 106Hz, RL= 500Ω, hfe = 100, gm = 100mA/V, rbb’ = 100Ω, CC = 1PF,
fT = 400MHz, find RS = ?
C = Ce + CC (1 + gmRL)
RS = 449 Ω
Bandwidth (BW) = fH – fL ~ fH
n
2
1 f
f n 2
L
L
1 L 2 n
f L n
2
fL 1
2 n 1
f L n
Taking square root on both sides
2 1
n
n
2
1 f H n 2
f
H
1 H 2 n
fH
f H n
2 1
2 n 1
fH
Taking square root on both sides
f H n 1
2 n 1
fH
1
f H n f H 2 1
n
An amplifier circuit simply increases the signal strength. But while amplifying, it just
increases the strength of its input signal whether it contains information or some noise
along with information. This noise or some disturbance is introduced in the amplifiers
because of their strong tendency to introduce hum due to sudden temperature changes or
stray electric and magnetic fields. Therefore, every high gain amplifier tends to give noise
along with signal in its output, which is very undesirable.
The noise level in the amplifier circuits can be considerably reduced by using negative
feedback done by injecting a fraction of output in phase opposition to the input signal.
From the above figure, the gain of the amplifier is represented as A. the gain of the
amplifier is the ratio of output voltage Vo to the input voltage Vi. the feedback network
extracts a voltage Vf = β Vo from the output Vo of the amplifier.
This voltage is added for positive feedback and subtracted for negative feedback, from the
signal voltage Vs. Now,
Vi=Vs+Vf=Vs+βVo
Vi=Vs−Vf=Vs−βVo
The quantity β = Vf/Vo is called as feedback ratio or feedback fraction.
Let us consider the case of negative feedback. The output V omust be equal to the input
voltage (Vs - βVo) multiplied by the gain A of the amplifier.
Let Af be the overall gain (gain with the feedback) of the amplifier. This is defined as the
ratio of output voltage Vo to the applied signal voltage Vs, i.e.,
A
Af
1 A
The equation of gain of the feedback amplifier, with positive feedback is given by
A
Af
1 A
These are the standard equations to calculate the gain of feedback amplifiers.
Types of Feedbacks
The process of injecting a fraction of output energy of some device back to the input is
known as Feedback. It has been found that feedback is very useful in reducing noise and
making the amplifier operation stable.
Depending upon whether the feedback signal aids or opposes the input signal, there are
two types of feedbacks used.
Positive Feedback
The feedback in which the feedback energy i.e., either voltage or current is in phase with
the input signal and thus aids it is called asPositive feedback.
Both the input signal and feedback signal introduces a phase shift of 180 o thus making a
360o resultant phase shift around the loop, to be finally in phase with the input signal.
Though the positive feedback increases the gain of the amplifier, it has the disadvantages
such as
Instability
It is because of these disadvantages the positive feedback is not recommended for the
amplifiers. If the positive feedback is sufficiently large, it leads to oscillations, by which
oscillator circuits are formed.
Negative Feedback
The feedback in which the feedback energy i.e., either voltage or current is out of phase
with the input and thus opposes it, is called as negative feedback.
In negative feedback, the amplifier introduces a phase shift of 180 o into the circuit while
the feedback network is so designed that it produces no phase shift or zero phase shift.
Thus the resultant feedback voltage Vf is 180o out of phase with the input signal Vin.
Though the gain of negative feedback amplifier is reduced, there are many advantages of
negative feedback such as
Reduction in distortion
Reduction in noise
While the output energy is being applied to the input, for the voltage energy to be taken as
feedback, the output is taken in shunt connection and for the current energy to be taken as
feedback, the output is taken in series connection.
There are two main types of negative feedback circuits. They are −
Voltage-series feedback
Voltage-shunt feedback
Negative Current Feedback
In this method, the voltage feedback to the input of amplifier is proportional to the output
current. This is further classified into two types.
Current-series feedback
Current-shunt feedback
Voltage-Series Feedback
In the voltage series feedback circuit, a fraction of the output voltage is applied in series
with the input voltage through the feedback circuit. This is also known as shunt-driven
series-fed feedback, i.e., a parallel-series circuit.
The following figure shows the block diagram of voltage series feedback, by which it is
evident that the feedback circuit is placed in shunt with the output but in series with the
input.
As the feedback circuit is connected in shunt with the output, the output impedance is
decreased and due to the series connection with the input, the input impedance is
increased.
The below figure shows the block diagram of voltage shunt feedback, by which it is evident
that the feedback circuit is placed in shunt with the output and also with the input.
As the feedback circuit is connected in shunt with the output and the input as well, both
the output impedance and the input impedance are decreased.
Current-Series Feedback
In the current series feedback circuit, a fraction of the output voltage is applied in series
with the input voltage through the feedback circuit. This is also known as series-driven
series-fed feedback i.e., a series-series circuit.
The following figure shows the block diagram of current series feedback, by which it is
evident that the feedback circuit is placed in series with the output and also with the input.
As the feedback circuit is connected in series with the output and the input as well, both
the output impedance and the input impedance are increased.
The below figure shows the block diagram of current shunt feedback, by which it is evident
that the feedback circuit is placed in series with the output but in parallel with the input.
As the feedback circuit is connected in series with the output, the output impedance is
increased and due to the parallel connection with the input, the input impedance is
decreased.
Let us now tabulate the amplifier characteristics that get affected by different types of
negative feedbacks.
AvVi RL
Vo AV I i Ri AVVi
Ro RL
AV RL
Where AV
Ro RL
Av represents the open circuit voltage gain without feedback
AV represents the open circuit voltage gain without feedback taking the load R L into account.
Vs=IiRi+βAvIiRi
V
Rif S =Ri+βAvRi
Ii
Rif=Ri(1+βAv)
Oscillators
Take a look at the following illustration. It clearly shows how an amplifier takes energy
from d.c. power source and converts it into a.c. energy at signal frequency. An oscillator
produces an oscillating a.c. signal on its own.
The following points highlight the differences between an alternator and an oscillator −
Oscillators can also be considered as opposite to rectifiers that convert a.c. to d.c. as these
convert d.c. to a.c.
Classification of Oscillators
Electronic oscillators are classified mainly into the following two categories −
Sinusoidal Oscillators
Sinusoidal oscillators can be classified in the following categories −
RC Oscillators − There oscillators use resistors and capacitors and are used to
generate low or audio-frequency signals. Thus they are also known as audio-
frequency (A.F.) oscillators. Such oscillators are Phase –shift and Wein-bridge
oscillators.
Crystal Oscillators − These oscillators use quartz crystals and are used to generate
highly stabilized output signal with frequencies up to 10 MHz. The Piezo oscillator is
an example of a crystal oscillator.
Damped Oscillations
The electrical oscillations whose amplitude goes on decreasing with time are called
as Damped Oscillations. The frequency of the damped oscillations may remain constant
depending upon the circuit parameters.
Damped oscillations are generally produced by the oscillatory circuits that produce power
losses and doesn’t compensate if required.
Undamped oscillations are generally produced by the oscillatory circuits that produce no
power losses and follow compensation techniques if any power losses occur.
An amplifier with positive feedback produces its output to be in phase with the input and
increases the strength of the signal. Positive feedback is also called as degenerative
feedback ordirect feedback. This kind of feedback makes a feedback amplifier, an
oscillator.
The use of positive feedback results in a feedback amplifier having closed-loop gain greater
than the open-loop gain. It results in instability and operates as an oscillatory circuit. An
oscillatory circuit provides a constantly varying amplified output signal of any desired
frequency.
This voltage is added for positive feedback and subtracted for negative feedback, from the
signal voltage Vs.
Vi = Vs + Vf = Vs + β Vo
The output Vo must be equal to the input voltage (Vs + βVo) multiplied by the gain A of the
amplifier.
Hence,
(Vs+βVo)A=Vo
Or
AVs+AβVo=Vo
Or
AVs=Vo(1−Aβ)
Therefore
Vo A
Vs 1 A
Let Af be the overall gain (gain with the feedback) of the amplifier. This is defined as the
ratio of output voltage Vo to the applied signal voltage Vs, i.e.,
outputvoltage Vo
Af
inputsigna lvoltage Vs
If Aβ = 1, Af = ∞. Thus the gain becomes infinity, i.e., there is output without any input. In
another words, the amplifier works as an Oscillator.
RC-Phase–shift Oscillators
The output voltage V1’ across the resistor R leads the input voltage applied input V 1 by
some phase angle ɸo. If R were reduced to zero, V1’ will lead the V1 by 90o i.e., ɸo = 90o.
Each section produces a phase shift of 60o. Consequently, a total phase shift of 180 o is
produced, i.e., voltage V2 leads the voltage V1 by 180o.
Construction
The phase-shift oscillator circuit consists of a single transistor amplifier section and a RC
phase-shift network. The phase shift network in this circuit, consists of three RC sections.
At the resonant frequency f o, the phase shift in each RC section is 60o so that the total
phase shift produced by RC network is 180 o.
Where
Advantages
The advantages of RC phase shift oscillator are as follows −
Another type of popular audio frequency oscillator is the Wien bridge oscillator circuit.
This is mostly used because of its important features. This circuit is free from the circuit
fluctuations and the ambient temperature.
The main advantage of this oscillator is that the frequency can be varied in the range of
10Hz to about 1MHz whereas in RC oscillators, the frequency is not varied.
Construction
The circuit construction of Wien bridge oscillator can be explained as below. It is a two-
stage amplifier with RC bridge circuit. The bridge circuit has the arms R 1C1, R3, R2C2 and the
tungsten lamp Lp. Resistance R3 and the lamp Lp are used to stabilize the amplitude of the
output.
The transistor T1 serves as an oscillator and an amplifier while the other transistor T 2 serves
as an inverter. The inverter operation provides a phase shift of 180 o. This circuit provides
positive feedback through R1C1, C2R2 to the transistor T1 and negative feedback through the
voltage divider to the input of transistor T2.
The frequency of oscillations is determined by the series element R1C1 and parallel element
R2C2 of the bridge.
If R1 = R2 and C1 = C2 = C
Then,
The oscillator consists of two stages of RC coupled amplifier and a feedback network. The
voltage across the parallel combination of R and C is fed to the input of amplifier 1. The net
phase shift through the two amplifiers is zero.
The usual idea of connecting the output of amplifier 2 to amplifier 1 to provide signal
regeneration for oscillator is not applicable here as the amplifier 1 will amplify signals over
a wide range of frequencies and hence direct coupling would result in poor frequency
stability. By adding Wien bridge feedback network, the oscillator becomes sensitive to a
particular frequency and hence frequency stability is achieved.
Operation
When the circuit is switched ON, the bridge circuit produces oscillations of the frequency
stated above. The two transistors produce a total phase shift of 360 o so that proper
positive feedback is ensured. The negative feedback in the circuit ensures constant output.
This is achieved by temperature sensitive tungsten lamp Lp. Its resistance increases with
current.
If the amplitude of the output increases, more current is produced and more negative
feedback is achieved. Due to this, the output would return to the original value. Whereas, if
the output tends to decrease, reverse action would take place.
Advantages
The advantages of Wien bridge oscillator are as follows −
The amplitude stability of the output voltage can be maintained more accurately, by
replacing R2 with a thermistor.
Disadvantages
The disadvantages of Wien bridge oscillator are as follows −
Two transistors and number of components are required for the circuit construction.
LC Oscillators
An oscillatory circuit produces electrical oscillations of a desired frequency. They are also
known as tank circuits.
A simple tank circuit comprises of an inductor L and a capacitor C both of which together
determine the oscillatory frequency of the circuit.
To understand the concept of oscillatory circuit, let us consider the following circuit. The
capacitor in this circuit is already charged using a dc source. In this situation, the upper
plate of the capacitor has excess of electrons whereas the lower plate has deficit of
electrons. The capacitor holds some electrostatic energy and there is a voltage across the
capacitor.
When the switch S is closed, the capacitor discharges and the current flows through the
inductor. Due to the inductive effect, the current builds up slowly towards a maximum
value. Once the capacitor discharges completely, the magnetic field around the coil is
maximum.
Once the capacitor is fully charged, it starts to discharge to build up a magnetic field around
the coil, as shown in the following circuit diagram.
In an ideal circuit, where there are no losses, the oscillations would continue indefinitely. In
a practical tank circuit, there occur losses such as resistive and radiation losses in the coil
and dielectric losses in the capacitor. These losses result in damped oscillations.
Frequency of Oscillations
The frequency of the oscillations produced by the tank circuit are determined by the
components of the tank circuit, the L and the C. The actual frequency of oscillations is
the resonant frequency(or natural frequency) of the tank circuit which is given by
1
fr=
2 LC
Capacitance of the capacitor
Tank Circuit − The tank circuit consists of an inductance L connected in parallel with
capacitor C. The values of these two components determine the frequency of the oscillator
circuit and hence this is called as Frequency determining circuit.
Transistor Amplifier − The output of the tank circuit is connected to the amplifier
circuit so that the oscillations produced by the tank circuit are amplified here.
Hence the output of these oscillations are increased by the amplifier.
Feedback Circuit − The function of feedback circuit is to transfer a part of the output
energy to LC circuit in proper phase. This feedback is positive in oscillators while
negative in amplifiers.
The change in oscillator frequency may arise due to the following factors −
Operating point of the active device such as BJT or FET used should lie in the linear
region of the amplifier. Its deviation will affect the oscillator frequency.
The changes in d.c. supply voltage applied to the active device, shift the oscillator
frequency. This can be avoided if a regulated power supply is used.
A change in output load may cause a change in the Q-factor of the tank circuit,
thereby causing a change in oscillator output frequency.
The presence of inter element capacitances and stray capacitances affect the
oscillator output frequency and thus frequency stability.
Tuned circuit oscillators are the circuits that produce oscillations with the help of tuning
circuits. The tuning circuits consists of an inductance L and a capacitor C. These are also
known as LC oscillators, resonant circuit oscillators or tank circuit oscillators.
Hartley Oscillator
A very popular local oscillator circuit that is mostly used in radio receivers is the Hartley
Oscillator circuit. The constructional details and operation of a Hartley oscillator are as
discussed below.
Construction
In the circuit diagram of a Hartley oscillator shown below, the resistors R 1, R2 and Re provide
necessary bias condition for the circuit. The capacitor Ce provides a.c. ground thereby
providing any signal degeneration. This also provides temperature stabilization.
The capacitors Cc and Cb are employed to block d.c. and to provide an a.c. path. The radio
frequency choke (R.F.C) offers very high impedance to high frequency currents which
means it shorts for d.c. and opens for a.c. Hence it provides d.c. load for collector and keeps
a.c. currents out of d.c. supply source
Tank Circuit
The frequency determining network is a parallel resonant circuit which consists of the
inductors L1 and L2 along with a variable capacitor C. The junction of L 1 and L2 are earthed.
The coil L1 has its one end connected to base via C c and the other to emitter via Ce. So, L2 is
in the output circuit. Both the coils L1 and L2 are inductively coupled and together form
an Auto-transformer.
The following circuit diagram shows the arrangement of a Hartley oscillator. The tank circuit
is shunt fed in this circuit. It can also be a series-fed.
The auto-transformer made by the inductive coupling of L1 and L2 helps in determining the
frequency and establishes the feedback. As the CE configured transistor provides
180o phase shift, another 180o phase shift is provided by the transformer, which makes
360o phase shift between the input and output voltages.
This makes the feedback positive which is essential for the condition of oscillations. When
the loop gain |βA| of the amplifier is greater than one, oscillations are sustained in the
circuit.
Frequency
The equation for frequency of Hartley oscillator is given as
Advantages
The advantages of Hartley oscillator are
The amplitude of the output remains constant over a fixed frequency range.
Disadvantages
The disadvantages of Hartley oscillator are
Colpitts oscillator
A Colpitts oscillator looks just like the Hartley oscillator but the inductors and capacitors are
replaced with each other in the tank circuit. The constructional details and operation of a
colpitts oscillator are as discussed below.
The resistors R1, R2 and Re provide necessary bias condition for the circuit. The capacitor
Ce provides a.c. ground thereby providing any signal degeneration. This also provides
temperature stabilization.
The capacitors Cc and Cb are employed to block d.c. and to provide an a.c. path. The radio
frequency choke (R.F.C) offers very high impedance to high frequency currents which
means it shorts for d.c. and opens for a.c. Hence it provides d.c. load for collector and
keeps a.c. currents out of d.c. supply source.
Tank Circuit
The frequency determining network is a parallel resonant circuit which consists of variable
capacitors C1 and C2 along with an inductor L. The junction of C 1 and C2 are earthed. The
capacitor C1 has its one end connected to base via C c and the other to emitter via C e. the
voltage developed across C1 provides the regenerative feedback required for the sustained
oscillations.
Operation
When the collector supply is given, a transient current is produced in the oscillatory or tank
circuit. The oscillatory current in the tank circuit produces a.c. voltage across C 1 which are
If terminal 1 is at positive potential with respect to terminal 3 at any instant, then terminal
2 will be at negative potential with respect to 3 at that instant because terminal 3 is
grounded. Therefore, points 1 and 2 are out of phase by 180o.
As the CE configured transistor provides 180 o phase shift, it makes 360o phase shift
between the input and output voltages. Hence, feedback is properly phased to produce
continuous Undamped oscillations. When the loop gain |βA| of the amplifier is greater
than one, oscillations are sustained in the circuit.
Frequency
The equation for frequency of Colpitts oscillator is given as
Advantages
The advantages of Colpitts oscillator are as follows −
The amplitude of the output remains constant over a fixed frequency range.
The Colpitts oscillator is designed to eliminate the disadvantages of Hartley oscillator and is
known to have no specific disadvantages. Hence there are many applications of a colpitts
oscillator.
Applications
Clapp Oscillator
Another oscillator which is an advanced version of Colpitts oscillator is the Clapp Oscillator.
This circuit is designed by making a few changes to the Colpitts oscillator.
The circuit differs from the Colpitts oscillator only in one respect; it contains one additional
capacitor (C3) connected in series with the inductor. The addition of capacitor (C 3) improves
the frequency stability and eliminates the effect of transistor parameters and stray
capacitances.
The following circuit diagram shows the arrangement of atransistor Clapp oscillator.
Where
Usually, the value of C3 is much smaller than C1 and C2. As a result of this, C is approximately
equal to C3. Therefore, the frequency of oscillation,
It is understood that the Clapp oscillator is similar to the Colpitts oscillator, however they
differ in the way the inductances and capacitances are arranged. The frequency stability
though is good, can be variable in a Clapp oscillator.
One of the important features of an oscillator is that the feedback energy applied should be
in correct phase to the tank circuit. The oscillator circuits discussed so far has employed
inductor (L) and capacitor (C) combination, in the tank circuit or frequency determining
circuit.
We have observed that the LC combination in oscillators provide 180 o phase shift and
transistor in CE configuration provide 180° phase shift to make a total of 360 o phase shift
so that it would make a zero difference in phase.
Drawbacks of LC circuits
Though they have few applications, the LC circuits have fewdrawbacks such as
Frequency instability
Waveform is poor
Changes in temperature
In RC and LC oscillators the values of resistance, capacitance and inductance vary with
temperature and hence the frequency gets affected. In order to avoid this problem, the
piezo electric crystals are being used in oscillators.
Crystal Oscillators
The use of piezo electric crystals in parallel resonant circuits provide high frequency
stability in oscillators. Such oscillators are called as Crystal Oscillators.
Crystal Oscillators
The principle of crystal oscillators depends upon the Piezo electric effect. The natural
shape of a crystal is hexagonal. When a crystal wafer is cur perpendicular to X-axis, it is
called as X-cut and when it is cut along Y-axis, it is called as Y-cut.
The crystal used in crystal oscillator exhibits a property called as Piezo electric property. So,
let us have an idea on piezo electric effect.
Certain crystalline materials like Rochelle salt, quartz and tourmaline exhibit piezo electric
effect and such materials are called as Piezo electric crystals. Quartz is the most commonly
used piezo electric crystal because it is inexpensive and readily available in nature.
If an AC voltage is applied, the crystal starts vibrating at the frequency of the applied
voltage. However, if the frequency of the applied voltage is made equal to the natural
frequency of the crystal, resonance takes place and crystal vibrations reach a maximum
value. This natural frequency is almost constant.
The above equivalent circuit consists of a series R-L-C circuit in parallel with a capacitance
Cm. When the crystal mounted across the AC source is not vibrating, it is equivalent to the
capacitance Cm. When the crystal vibrates, it acts like a tuned R-L-C circuit.
The first one is the series resonant frequency (fs), which occurs when reactance of the
inductance (L) is equal to the reactance of the capacitance C. In that case, the impedance of
the equivalent circuit is equal to the resistance R and the frequency of oscillation is given
by the relation,
The second one is the parallel resonant frequency (fp), which occurs when the reactance of
R-L-C branch is equal to the reactance of capacitor Cm. At this frequency, the crystal offers a
very high impedance to the external circuit and the frequency of oscillation is given by the
relation.
Where
The following circuit diagram shows the arrangement of a transistor pierce crystal
oscillator.
In this circuit, the crystal is connected as a series element in the feedback path from
collector to the base. The resistors R1, R2 and RE provide a voltage-divider stabilized d.c.
bias circuit. The capacitor CE provides a.c. bypass of the emitter resistor and RFC (radio
frequency choke) coil provides for d.c. bias while decoupling any a.c. signal on the power
lines from affecting the output signal. The coupling capacitor C has negligible impedance at
the circuit operating frequency. But it blocks any d.c. between collector and base.
The circuit frequency of oscillation is set by the series resonant frequency of the crystal and
its value is given by the relation,
It may be noted that the changes in supply voltage, transistor device parameters etc. have
no effect on the circuit operating frequency, which is held stabilized by the crystal.
The frequency stability of an oscillator is defined as the ability of the oscillator to maintain
the required frequency constant over a long time interval as possible. Let us try to discuss
the factors that affect this frequency stability.
The operating of the active device used is adjusted to be in the linear portion of its
characteristics. This point is shifted due to temperature variations and hence the stability is
affected.
Variation in temperature
The tank circuit in the oscillator circuit, contains various frequency determining
components such as resistors, capacitors and inductors. All of their parameters are
temperature dependent. Due to the change in temperature, their values get affected. This
brings the change in frequency of the oscillator circuit.
In order to avoid this, the regulated power supply system is implemented. This is in short
called as RPS.
The inter element capacitors undergo change due to various reasons as temperature,
voltage etc. This problem can be solved by connecting swamping capacitor across offending
inter-element capacitor.
Value of Q
The value of Q (Quality factor) must be high in oscillators. The value of Q in tuned
oscillators determine the selectivity. As this Q is directly proportional to the frequency
stability of a tuned circuit, the value of Q should be maintained high.
While the voltage amplifier raises the voltage level of the signal, the power amplifier
raises the power level of the signal. Besides raising the power level, it can also be said that a
power amplifier is a device which converts DC power to AC power and whose action is
controlled by the input signal.
The DC power is distributed according to the relation,
DC power input = AC power output + losses
Power Transistor
For such Power amplification, a normal transistor would not do. A transistor that is
manufactured to suit the purpose of power amplification is called as a Power transistor.
A Power transistor differs from the other transistors, in the following factors.
It is larger in size, in order to handle large powers.
The collector region of the transistor is made large and a heat sink is placed at the
collector-base junction in order to minimize heat generated.
The emitter and base regions of a power transistor are heavily doped.
Due to the low input resistance, it requires low input power.
Hence there is a lot of difference in voltage amplification and power amplification. So,
let us now try to get into the details to understand the differences between a voltage
amplifier and a power amplifier.
Difference between Voltage and Power Amplifiers:Let us try to differentiate between
voltage and power amplifier.
Voltage Amplifier
The function of a voltage amplifier is to raise the voltage level of the signal. A voltage
amplifier is designed to achieve maximum voltage amplification.
The Power amplifiers amplify the power level of the signal. This amplification is done
in the last stage in audio applications. The applications related to radio frequencies employ
radio power amplifiers. But the operating point of a transistor plays a very important role
in determining the efficiency of the amplifier. The main classification is done based on this
mode of operation.
The classification is done based on their frequencies and also based on their mode
of operation.
Classification Based on Frequencies
Power amplifiers are divided into two categories, based on the frequencies they
handle. They are as follows.
Audio Power Amplifiers − The audio power amplifiers raise the power level of
signals that have audio frequency range (20 Hz to 20 KHz). They are also known
as Small signal power amplifiers.
Radio Power Amplifiers − Radio Power Amplifiers or tuned power amplifiers raise
the power level of signals that have radio frequency range (3 KHz to 300 GHz). They
are also known as large signal power amplifiers.
Class B Power amplifier − When the collector current flows only during the positive
half cycle of the input signal, the power amplifier is known as class B power
amplifier.
Class C Power amplifier − When the collector current flows for less than half cycle of
the input signal, the power amplifier is known as class C power amplifier.
There forms another amplifier called Class AB amplifier, if we combine the class A and
class B amplifiers so as to utilize the advantages of both. Before going into the details of
these amplifiers, let us have a look at the important terms that have to be considered to
determine the efficiency of an amplifier.
Terms Considering Performance
The primary objective of a power amplifier is to obtain maximum output power. In
order to achieve this, the important factors to be considered are collector efficiency, power
dissipation capability and distortion. Let us go through them in detail.
Collector Efficiency
This explains how well an amplifier converts DC power to AC power. When the DC
supply is given by the battery but no AC signal input is given, the collector output at such a
condition is observed as collector efficiency.
The collector efficiency is defined as
η=average a.c poweroutput / average d.c powerinputtotransisto
The main aim of a power amplifier is to obtain maximum collector efficiency. Hence the
higher the value of collector efficiency, the efficient the amplifier will be.
Power Dissipation Capacity
Every transistor gets heated up during its operation. As a power transistor handles large
currents, it gets more heated up. This heat increases the temperature of the transistor,
which alters the operating point of the transistor. So, in order to maintain the operating
point stability, the temperature of the transistor has to be kept in permissible limits. For
this, the heat produced has to be dissipated. Such a capacity is called as Power dissipation
capability.
Power dissipation capability can be defined as the ability of a power transistor to dissipate
the heat developed in it. Metal cases called heat sinks are used in order to dissipate the
heat produced in power transistors.
Distortion
A transistor is a non-linear device. When compared with the input, there occur few
variations in the output. In voltage amplifiers, this problem is not pre-dominant as small
A Class A power amplifier is one in which the output current flows for the entire
cycle of the AC input supply. Hence the complete signal present at the input is amplified at
the output. The following figure shows the circuit diagram for Class A Power amplifier.
From the above figure, it can be observed that the transformer is present at the collector as
a load. The use of transformer permits the impedance matching, resulting in the
transference of maximum power to the load e.g. loud speaker.
The output characteristics with operating point Q is shown in the figure above. Here
(Ic)Q and (Vce)Q represent no signal collector current and voltage between collector and
emitter respectively. When signal is applied, the Q-point shifts to Q1 and Q2. The output
current increases to (Ic)max and decreases to (Ic)min. Similarly, the collector-emitter voltage
increases to (Vce)max and decreases to (Vce)min.
Pin=voltage×current=VCC(IC)Q
PRC=(current)2×resistance=(IC)2QRC
Ptr=Pin−PRC=VCC−(IC)2QRC
When signal is applied, the power given to transistor is used in the following two parts −
A.C. Power developed across load resistors RC which constitutes the a.c. power
output.
Where I is the R.M.S. value of a.c. output current through load, V is the R.M.S. value
of a.c. voltage, and Vm is the maximum value of V.
The D.C. power dissipated by the transistor (collector region) in the form of heat, i.e.,
(PC)dc
The class A power amplifier as discussed in the previous chapter, is the circuit in which
the output current flows for the entire cycle of the AC input supply. We also have learnt
about the disadvantages it has such as low output power and efficiency. In order to
The construction of class A power amplifier can be understood with the help of below
figure. This is similar to the normal amplifier circuit but connected with a transformer in the
collector load.
Transformer Action:
The transformer used in the collector circuit is for impedance matching. R L is the load
connected in the secondary of a transformer. RL’ is the reflected load in the primary of the
transformer.
The number of turns in the primary are n1 and the secondary are n2. Let V1 and V2 be
the primary and secondary voltages and I 1 and I 2 be the primary and secondary currents
respectively. The below figure shows the transformer clearly.
Circuit Operation
If the peak value of the collector current due to signal is equal to zero signal collector
current, then the maximum a.c. power output is obtained. So, in order to achieve complete
amplification, the operating point should lie at the center of the load line.
The operating point obviously varies when the signal is applied. The collector voltage varies
in opposite phase to the collector current. The variation of collector voltage appears across
the primary of the transformer.
The efficiency of a class A power amplifier is nearly than 30% whereas it has got
improved to 50% by using the transformer coupled class A power amplifier.
Advantages
The advantages of transformer coupled class A power amplifier are as follows.
No loss of signal power in the base or collector resistors.
Excellent impedance matching is achieved.
Gain is high.
DC isolation is provided.
Disadvantages
The disadvantages of transformer coupled class A power amplifier are as follows.
Low frequency signals are less amplified comparatively.
The figure below shows the input and output waveforms during class B operation.
When the signal is applied, the circuit is forward biased for the positive half cycle of
the input and hence the collector current flows. But during the negative half cycle of the
input, the circuit is reverse biased and the collector current will be absent. Hence only the
positive half cycle is amplified at the output.
As the negative half cycle is completely absent, the signal distortion will be high.
Also, when the applied signal increases, the power dissipation will be more. But when
compared to class A power amplifier, the output efficiency is [Link], in order to
minimize the disadvantages and achieve low distortion, high efficiency and high output
power, the push-pull configuration is used in this class B amplifier.
Construction:
The circuit of a push-pull class B power amplifier consists of two identical transistors
T1 and T2 whose bases are connected to the secondary of the center-tapped input
transformer Tr1. The emitters are shorted and the collectors are given the V CC supply
through the primary of the output transformer Tr2.
The circuit arrangement of class B push-pull amplifier, is same as that of class A push-pull
amplifier except that the transistors are biased at cut off, instead of using the biasing
resistors. The figure below gives the detailing of the construction of a push-pull class B
power amplifier.
Operation
The circuit of class B push-pull amplifier shown in the above figure clears that both
the transformers are center-tapped. When no signal is applied at the input, the transistors
T1 and T2 are in cut off condition and hence no collector currents flow. As no current is
drawn from VCC, no power is wasted.
When input signal is given, it is applied to the input transformer Tr1 which splits the
signal into two signals that are 180 o out of phase with each other. These two signals are
given to the two identical transistors T1 and T2. For the positive half cycle, the base of the
transistor T1 becomes positive and collector current flows. At the same time, the transistor
T2 has negative half cycle, which throws the transistor T2 into cutoff condition and hence no
collector current flows. The waveform is produced as shown in the following figure.
The above circuit employs a NPN transistor and a PNP transistor connected in push
pull configuration. When the input signal is applied, during the positive half cycle of the
input signal, the NPN transistor conducts and the PNP transistor cuts off. During the
negative half cycle, the NPN transistor cuts off and the PNP transistor conducts.
In this way, the NPN transistor amplifies during positive half cycle of the input, while
PNP transistor amplifies during negative half cycle of the input. As the transistors are both
complement to each other, yet act symmetrically while being connected in push pull
configuration of class B, this circuit is termed as Complementary symmetry push pull class B
amplifier.
Advantages
The advantages of Complementary symmetry push pull class B amplifier are as follows.
As there is no need of center tapped transformers, the weight and cost are reduced.
Equal and opposite input signal voltages are not required.
Disadvantages
The disadvantages of Complementary symmetry push pull class B amplifier are as follows.
Cross-over Distortion:
In the push-pull configuration, the two identical transistors get into conduction, one
after the other and the output produced will be the combination of both.
When the signal changes or crosses over from one transistor to the other at the zero
voltage point, it produces an amount of distortion to the output wave shape. For a
transistor in order to conduct, the base emitter junction should cross 0.7v, the cut off
voltage. The time taken for a transistor to get ON from OFF or to get OFF from ON state is
called the transition period.
At the zero voltage point, the transition period of switching over the transistors from
one to the other, has its effect which leads to the instances where both the transistors are
OFF at a time. Such instances can be called as Flat spot or Dead band on the output wave
shape.
The above figure clearly shows the cross over distortion which is prominent in the output
waveform. This is the main disadvantage. This cross over distortion effect also reduces the
overall peak to peak value of the output waveform which in turn reduces the maximum
power output. This can be more clearly understood through the non-linear characteristic of
the waveform as shown below.
This idea leads to the invention of class AB amplifier, which is the combination of
both class A and class B amplifiers, as discussed below.
The cross over distortion is the problem that occurs when both the transistors are
OFF at the same instant, during the transition period. In order to eliminate this, the
condition has to be chosen for more than one half cycle. Hence, the other transistor gets
into conduction, before the operating transistor switches to cut off state. This is achieved
only by using class AB configuration, as shown in the following circuit diagram.
The small bias voltage given using diodes D1 and D2, as shown in the above figure,
helps the operating point to be above the cutoff point. Hence the output waveform of class
AB results as seen in the above figure. The crossover distortion created by class B is
overcome by this class AB, as well the inefficiencies of class A and B don’t affect the circuit.
So, the class AB is a good compromise between class A and class B in terms of
efficiency and linearity having the efficiency reaching about 50% to 60%. The class A, B and
AB amplifiers are called as linear amplifiers because the output signal amplitude and phase
are linearly related to the input signal amplitude and phase.
When the collector current flows for less than half cycle of the input signal, the
power amplifier is known as class C power amplifier. The efficiency of class C amplifier is
high while linearity is poor. The conduction angle for class C is less than 180 o. It is generally
around 90o, which means the transistor remains idle for more than half of the input signal.
So, the output current will be delivered for less time compared to the application of input
signal.
The following figure shows the operating point and output of a class C amplifier.
This kind of biasing gives a much improved efficiency of around 80% to the amplifier,
but introduces heavy distortion in the output signal. Using the class C amplifier, the pulses
produced at its output can be converted to complete sine wave of a particular frequency by
using LC circuits in its collector circuit.
The types of amplifiers that we have discussed so far cannot work effectively at radio
frequencies, even though they are good at audio frequencies. Also, the gain of these
amplifiers is such that it will not vary according to the frequency of the signal, over a wide
range. This allows the amplification of the signal equally well over a range of frequencies
and does not permit the selection of particular desired frequency while rejecting the other
frequencies.
UNIT 3
FIELD EFFECT TRANSISTOR
Part -1
FET BIASING:
(JFETs and Depletion –type FET) -Fixed-Bias, Self-Bias and Voltage-Divider Bias
Configurations (both n- and p-channel); Enhancement-Type MOSFETs-Feedback Biasing
Arrangement, Voltage –Divider Biasing Arrangement.
Part -2
Sampling Gates:
UJT, JFET and MOSFET Sampling gate, Sample & Hold circuits. Transistor bootstrap ramp
generator.
Part -1
3.1 INTRODUCTION …………………………………………………………………….. 2
3.2 CLASSIFICATION OF FET ……………………………………………………….. 3
3.3 CONSTRUCTION AND OPERATION OF N- CHANNEL FET ………… 4
3.4 CHARACTERISTICS OF N-CHANNEL JFET ……………………………….. 9
3.5 JFET PARAMETERS ………………………………………………………………... 13
3.6 THE FET SMALL SIGNAL MODEL ……………………………………………. 14
3.7 MOSFET ………………………………………………………………………………… 16
3.7.1 DEPLETION MOSFET
3.7.2 E-MOSFETS
3.8 APPLICATION OF MOSFET ……………………………………………………… 27
3.9 BIASING FET ……………………………………………………………………………27
3.9.1 SELF BIAS
3.9.2 VOLTAGE DIVIDER BIAS
UNIT 3
FIELD EFFECT TRANSISTOR
3.1 INTRODUCTION
1. The Field effect transistor is abbreviated as FET, it is a semiconductor device like a
BJT which can be used as an amplifier or switch.
2. The Field effect transistor is a voltage operated device, whereas bipolar junction
transistor is a current controlled device. Unlike BJT a FET requires virtually no input
current.
3. This gives it an extremely high input resistance, which is its most important
advantage over a bipolar transistor.
4. FET is also a three terminal device, labeled as source, drain and gate.
5. The source can be viewed as BJT’s emitter, the drain as collector, and the gate as the
counter part of the base.
6. The material that connects the source to drain is referred to as the channel.
7. FET operation depends only on the flow of majority carriers, therefore they are
called uni-polar devices. BJT operation depends on both minority and majority
carriers.
8. As FET has conduction through only majority carriers it is less noisy than BJT.
9. FETs are much easier to fabricate and are particularly suitable for ICs because they
occupy less space than BJTs.
10. FET amplifiers have low gain bandwidth product due to the junction capacitive
effects and produce more signal distortion except for small signal operation.
2. MOSFETs
MOSFETs are further classified as two types Depletion MOSFETs and Enhancement.
MOSFETs
When the channel is of N-type the JFET is referred to as an N-channel JFET ,when the
channel is of P-type the JFET is referred to as P-channel JFET.
The schematic symbols for the P-channel and N-channel JFETs are shown in the figure.
A piece of N- type material, referred to as channel has two smaller pieces of P-type
material attached to its sides, forming PN junctions. The channel ends are designated as
the drain and source . And the two pieces of P-type material are connected together and
their terminal is called the gate. Since this channel is in the N-type bar, the FET is known as N-
channel JFET.
The overall operation of the JFET is based on varying the width of the channel to
control the drain current.
A piece of N type material referred to as the channel, has two smaller pieces of P
type material attached to its sites, farming PN –Junctions. The channel’s ends are
designated the drain and the source. And the two pieces of P type material are connected
together and their terminal is called the gate. With the gate terminal not connected and the
potential applied positive at the drain negative at the source a drain current Id flows. When
the gate is biased negative with respective to the source the PN junctions are reverse
biased and depletion regions are formed. The channel is more lightly doped than the P type
gate blocks, so the depletion regions penetrate deeply into the channel. Since depletion
region is a region depleted of charge carriers it behaves as an Insulator. The result is that
the channel is narrowed. Its resistance is increased and Id is reduced. When the negative
gate bias voltage is further increased, the depletion regions meet at the center and Id is cut
off completely.
We can vary the width of the channel and in turn vary the amount of drain
current. This can be done by varying the value of Vgs. This point is illustrated in the fig
below. Here we are dealing with N channel FET. So channel is of N type and gate is of P
type that constitutes a PN junction. This PN junction is always reverse biased in JFET
operation .The reverse bias is applied by a battery voltage Vgs connected between the
gate and the source terminal i.e positive terminal of the battery is connected to the
source and negative terminal to gate.
1) When a PN junction is reverse biased the electrons and holes diffuse across junction
by leaving immobile ions on the N and P sides , the region containing these
immobile ions is known as depletion regions.
2) If both P and N regions are heavily doped then the depletion region extends
symmetrically on both sides.
3) But in N channel FET P region is heavily doped than N type thus depletion region
extends more in N region than P region.
4) So when no Vds is applied the depletion region is symmetrical and the conductivity
becomes Zero. Since there are no mobile carriers in the junction.
5) As the reverse bias voltage is increases the thickness of the depletion region also
increases. i.e. the effective channel width decreases .
6) By varying the value of Vgs we can vary the width of the channel.
1) When no voltage is applied to the gate i.e. Vgs=0 , Vds is applied between source and
drain the electrons will flow from source to drain through the channel constituting
drain current Id .
2) With Vgs= 0 for Id= 0 the channel between the gate junctions is entirely open .In
response to a small applied voltage Vds , the entire bar acts as a simple semi
conductor resistor and the current Id increases linearly with Vds .
3) The channel resistances are represented as rd and rs as shown in the fig.
4) This increasing drain current Id produces a voltage drop across rd which reverse
biases the gate to source junction,(rd> rs) .Thus the depletion region is formed
which is not symmetrical .
5) The depletion region i.e. developed penetrates deeper in to the channel near drain
and less towards source because Vrd >> Vrs. So reverse bias is higher near drain than
at source.
6) As a result growing depletion region reduces the effective width of the channel.
Eventually a voltage Vds is reached at which the channel is pinched off. This is the
voltage where the current Id begins to level off and approach a constant value.
7) So, by varying the value of Vds we can vary the width of the channel holding Vgs
constant.
It is of course in principle not possible for the channel to close Completely and there
by reduce the current Id to Zero for, if such indeed, could be the case the gate voltage Vgs is
applied in the direction to provide additional reverse bias
1) When voltage is applied between the drain and source with a battery Vdd, the
electrons flow from source to drain through the narrow channel existing between
the depletion regions. This constitutes the drain current Id, its conventional
direction is from drain to source.
2) The value of drain current is maximum when no external voltage is applied
between gate and source and is designated by Idss.
3) When Vgs is increased beyond Zero the depletion regions are widened. This
reduces the effective width of the channel and therefore controls the flow of drain
current through the channel.
4) When Vgs is further increased a stage is reached at which to depletion regions
touch each other that means the entire channel is closed with depletion region.
This reduces the drain current to Zero.
1) Drain or VI Characteristics
2) Transfer characteristics
1. Drain Characteristics:-
1) When Vds is applied and it is increasing the drain current ID also increases linearly
up to knee point.
2) This shows that FET behaves like an ordinary [Link] region is called as
ohmic region.
3) ID increases with increase in drain to source voltage. Here the drain current is
increased slowly as compared to ohmic region.
4)
5)
6)
4) It is because of the fact that there is an increase in VDS .This in turn increases the
reverse bias voltage across the gate source junction .As a result of this depletion
region grows in size thereby reducing the effective width of the channel.
5) All the drain to source voltage corresponding to point the channel width is reduced
to a minimum value and is known as pinch off.
6) The drain to source voltage at which channel pinch off occurs is called pinch off
voltage(Vp).
Id =Idss [1-Vgs/Vp]2
BREAKDOWN REGION:-
1) The region is shown by the curve .In this region, the drain current increases
rapidly as the drain to source voltage is increased.
2) It is because of the gate to source junction due to avalanche effect.
3) The avalanche break down occurs at progressively lower value of VDS because
the reverse bias gate voltage adds to the drain voltage thereby increasing
effective voltage across the gate junction
This causes
2. TRANSFER CHARACTERISTICS:-
These curves shows the relationship between drain current ID and gate to
source voltage VGS for different values of VDS.
1) First adjust the drain to source voltage to some suitable value , then increase
the gate to source voltage in small suitable value.
2) Plot the graph between gate to source voltage along the horizontal axis and
current ID on the vertical axis. We shall obtain a curve like this.
Transfer Characteristics
3) As we know that if Vgs is more negative curves drain current to reduce . where
Vgs is made sufficiently negative, Id is reduced to zero. This is caused by the
widening of the depletion region to a point where it is completely closes the
channel. The value of Vgs at the cutoff point is designed as Vgsoff
4) The upper end of the curve as shown by the drain current value is equal to Idss
that is when Vgs = 0 the drain current is maximum.
5) While the lower end is indicated by a voltage equal to Vgsoff
6) If Vgs continuously increasing , the channel width is reduced , then Id =0
7) It may be noted that curve is part of the parabola; it may be expressed as
Id=Idss[1-Vgs/Vgsoff]2
Vp is the value of Vgs that causes the JFET to become constant current component,
It is measured at Vgs =0V and has a constant drain current of Id =Idss .Where Vgsoff is the
value of Vgs that reduces Id to approximately zero.
The gate to source junction of a JFET is never allowed to become forward biased
because the gate material is not designed to handle any significant amount of current. If the
junction is allowed to become forward biased, current is generated through the gate
material. This current may destroy the component.
A C Drain resistance(rd):
It is also called dynamic drain resistance and is the [Link] between the drain and
source terminal,when the JFET is operating in the pinch off or saturation [Link] is given
by the ratio of small change in drain to source voltage ∆Vds to the corresponding change in
drain current ∆Id for a constant gate to source voltage Vgs.
It is also called forward transconductance . It is given by the ratio of small change in drain
current (∆Id) to the corresponding change in gate to source voltage (∆Vds)
gm=∆Id/∆Vds
It is given by the ratio of small change in drain to source voltage (∆Vds) to the
corresponding change in gate to source voltage (∆Vgs)for a constant drain current (Id).
µ=∆Vds/∆Vgs=gm rd
We can express the drain current iD as a function f of the gate voltage and drain voltage Vds.
Id =f(Vgs,Vds)------------------(1)
∆vgs=vgs
∆vds=vds
Id=gm v Vds→(1)
gm= |Vds
Is the mutual conductance or transconductance .It is also called as gfs or yfs common
source forward conductance .
rd= |Vgs
The reciprocal of the rd is the drain conductance gd .It is also designated by Yos
and Gos and called the common source output conductance . So the small signal equivalent
circuit for FET can be drawn in two different ways.
A small signal current –source model for FET in common source configuration can
be drawn satisfying Eq→(1) as shown in the figure(a)
This low frequency model for FET has a Norton’s output circuit with a dependent
current generator whose magnitude is proportional to the gate-to –source voltage. The
proportionality factor is the transconductance ‘gm’. The output resistance is ‘rd’. The input
resistance between the gate and source is infinite, since it is assumed that the reverse
biased gate draws no current. For the same reason the resistance between gate and drain is
assumed to be infinite.
This can be derived by finding the Thevenin’s equivalent for the output part of
fig(a) .
These small signal models for FET can be used for analyzing the three basic FET
amplifier configurations:
3. common gate(CG).
(a)Small Signal Current source model for FET (b)Small Signal voltage source model for FET
Here the input circuit is kept open because of having high input impedance and the output
circuit satisfies the equation for ID
3.7 MOSFET:-
We now turn our attention to the insulated gate FET or metal oxide semi conductor FET
which is having the greater commercial importance than the junction FET.
Most MOSFETS however are triodes, with the substrate internally connected to the source.
The circuit symbols used by several manufacturers are indicated in the Fig below.
D-MOSFETS can be operated in both the depletion mode and the enhancement mode.
E MOSFETS are restricted to operate in enhancement mode. The primary difference
between them is their physical construction.
The construction difference between the two is shown in the fig given below.
As we can see the D MOSFET have physical channel between the source and drain
terminals(Shaded area)
The E MOSFET on the other hand has no such channel physically. It depends on the
gate voltage to form a channel between the source and the drain terminals.
Both MOSFETS have an insulating layer between the gate and the rest of the
component. This insulating layer is made up of SIO2 a glass like insulating material. The
gate material is made up of metal conductor .Thus going from gate to substrate, we can
have metal oxide semiconductor which is where the term MOSFET comes from.
Since the gate is insulated from the rest of the component, the MOSFET is
sometimes referred to as an insulated gate FET or IGFET.
The foundation of the MOSFET is called the substrate. This material is represented in the
schematic symbol by the center line that is connected to the source.
In the symbol for the MOSFET, the arrow is placed on the substrate. As with JFET an arrow
pointing in represents an N-channel device, while an arrow pointing out represents p-
channel device.
The N- channel MOSFET consists of a lightly doped p type substance into which two
heavily doped n+ regions are diffused as shown in the Fig. These n+ sections , which will act
as source and drain. A thin layer of insulation silicon dioxide (SIO2) is grown over the
surface of the structure, and holes are cut into oxide layer, allowing contact with the source
and drain. Then the gate metal area is overlaid on the oxide, covering the entire channel
[Link] contacts are made to drain and source and the contact to the metal over the
channel area is the gate [Link] metal area of the gate, in conjunction with the
insulating dielectric oxide layer and the semiconductor channel, forms a parallel plate
capacitor. The insulating layer of sio2
Is the reason why this device is called the insulated gate field effect transistor. This
layer results in an extremely high input resistance (10 10 to 10power 15ohms) for
MOSFET.
1) The above fig shows the D-MOSFET operating conditions with gate and source
terminals shorted together(VGS=0V)
2) At this stage ID= IDSS where VGS=0V, with this voltage VDS, an appreciable drain
current IDSS flows.
3) If the gate to source voltage is made negative i.e. VGs is negative .Positive charges are
induced in the channel through the SIO2 of the gate capacitor.
4) Since the current in a FET is due to majority carriers(electrons for an N-type material)
, the induced positive charges make the channel less conductive and the drain current
drops as Vgs is made more negative.
6) That means biasing voltage Vgs depletes the channel of free carriers. This effectively
reduces the width of the channel, increasing its resistance.
7) Note that negative Vgs has the same effect on the MOSFET as it has on the JFET.
8) As shown in the fig above, the depletion layer generated by Vgs (represented by the
white space between the insulating material and the channel) cuts into the channel,
reducing its width. As a result ,Id<[Link] actual value of ID depends on the value of
Idss,Vgs(off) and Vgs.
1) This operating mode is a result of applying a positive gate to source voltage Vgs to
the device.
2) When Vgs is positive the channel is effectively widened. This reduces the resistance
of the channel allowing ID to exceed the value of IDSS
3) When Vgs is given positive the majority carriers in the p-type are holes. The holes
in the p type substrate are repelled by the +ve gate voltage.
4) At the same time, the conduction band electrons (minority carriers) in the p type
material are attracted towards the channel by the +gate voltage.
5) With the build up of electrons near the channel , the area to the right of the physical
channel effectively becomes an N type material.
6) The extended n type channel now allows more current, Id> Idss
The fig. shows the drain characteristics for the N channel depletion type MOSFET
1) The curves are plotted for both Vgs positive and Vgs negative voltages
.
2) When Vgs=0 and negative the MOSFET operates in depletion mode when Vgs is
positive ,the MOSFET operates in the enhancement mode.
3) The difference between JFET and D MOSFET is that JFET does not operate for
positive values of Vgs.
4) When Vds=0, there is no conduction takes place between source to drain, if Vgs<0
and Vds>0 then Id increases linearly.
5) But as Vgs,0 induces positive charges holes in the channel, and controls the channel
width. Thus the conduction between source to drain is maintained as constant, i.e. Id
is constant.
6) If Vgs>0 the gate induces more electrons in channel side, it is added with the free
electrons generated by source. again the potential applied to gate determines the
channel width and maintains constant current flow through it as shown in Fig
TRANSFER CHARACTERISTICS:-
1) Here in this curve it may be noted that the region AB of the characteristics similar to
that of JFET.
3) Note that Id=Idss for Vgs=0V when Vgs is negative, Id< Idss when Vgs= Vgs(off) ,Id
is reduced to approximately omA. Where Vgs is positive Id>Idss. So obviously Idss is
not the maximum possible value of Id for a MOSFET.
4) The curves are similar to JFET so thet the D MOSFET have the same
transconductance equation.
3.7.2 E-MOSFETS
The E MOSFET is capable of operating only in the enhancement [Link] gate potential
must be positive w.r.t to source.
1) when the value of Vgs=0V, there is no channel connecting the source and drain
materials.
2) As aresult , there can be no significant amount of drain current.
3) When Vgs=0, the Vdd supply tries to force free electrons from source to drain but
the presence of p-region does not permit the electrons to pass through it. Thus there
is no drain current at Vgs=0,
4) If Vgs is positive, it induces a negative charge in the p type substrate just adjacent to
the SIO2 layer.
5) As the holes are repelled by the positive gate voltage, the minority carrier electrons
attracted toward this voltage. This forms an effective N type bridge between source
and drain providing a path for drain current.
6) This +ve gate voltage forma a channel between the source and drain.
7) This produces a thin layer of N type channel in the P type substrate. This layer of
free electrons is called N type inversion layer.
8) The minimum Vgs which produces this inversion layer is called threshold voltage
and is designated by Vgs(th).This is the point at which the device turns on is called
the threshold voltage Vgs(th)
9) When the voltage Vgs is <Vgs (th) no current flows from drain to source.
10)How ever when the voltage Vgs > Vgs (th) the inversion layer connects the drain to
source and we get significant values of current.
CHARACTERISTICS OF E MOSFET:-
1. DRAIN CHARACTERISTICS
The volt ampere drain characteristics of an N-channel enhancement mode MOSFET are given in
the fig.
2. TRANSFER CHARACTERISTICS:-
1) The current Idss at Vgs≤ 0 is very small being of the order of a few nano amps.
2) As Vgs is made +ve , the current Id increases slowly at first, and then much more
rapidly with an increase in Vgs.
3) The standard trans-conductance formula will not work for the E MOSFET.
4) To determine the value of ID at a given value of VGs we must use the following
relation
Id =K[Vgs-Vgs(Th)]2
K=
From the data specification sheets, the 2N7000 has the following ratings.
Id(on)= 75mA(minimum).
And Vgs(th)=0.8(minimum)
This can be achieved by suitably selecting the gate to source voltage VGS and drain
current ID which is referred to as biasing
JFET biasing circuits are very similar to BJT biasing circuitsThe main
difference between JFET circuits and BJT circuits is the operation of the active
components themselves
1) Self bias
2) Voltage divider bias.
IS produces a voltage drop across RS and makes the source positive w.r.t ground. In any
JFET circuit all the source current passes through the device to the drain circuit .This is due
to the fact that there is no significant gate current.
In the following DC analysis, the N channel J FET shown in the fig. is used for illustration.
For DC analysis we can replace coupling capacitors by open circuits and we can also
replace the resistor RG by a short circuit equivalent: IG = [Link] relation between ID and
VGS is given by
Id=Idss[1- ]2
Id=Idss[1- ]2
Id=Idss[1+ ]2
Is produces a voltage drop across Rs and makes the source positive w.r.t ground in any
JFET circuit all the source current passes through the device to drain circuit this is due to
the fact that there is no significant gate current. Therefore we can define source current as
Is=Id and Vg=0 then
Vs= Is Rs =IdRs
Vgs=Vg-Vs=0-IdRs=-IdRs
Typical transfer characteristics for a self biased JFET are shown in the fig.
The maximum drain current is 6mA and the gate source cut off voltage is -3V. This
means the gate voltage has to be between 0 and -3V.
Now using the equation VGS = -IDRS and assuming RS of any suitable value we can draw
the self bias line.
for ID = 0
VGS = -ID RS
VGS = 0X (500.Ω) = 0V
( Id, VGS)
By plotting these two points, we can draw the straight line through the points. This
line will intersect the transconductance curve and it is known as self bias [Link]
intersection point gives the operating point of the self bias JFET for the circuit.
At Q point , the ID is slightly > than 2mA and VGS is slightly > -1V. The Q point for
the self bias JFET depends on the value of [Link] Rs is large, Q point far down on the
transconductance curve ,ID is small, when Rs is small Q point is far up on the curve , ID is
large.
The fig. shows N channel JFET with voltage divider bias. The voltage at the source of
JFET must be more positive than the voltage at the gate in order to keep the gate to source
junction reverse biased. The source voltage is
VS = IDRS
Vg= Vdd
For dc analysis
VG-VGS-VS =0
:: VGS = VG-Vs=VG-ISRS
VGS = VG-IDRS :: IS = ID
VDS+IDRD+VS-VDD =0
::VDS = VDD-IDRD-IDRS
b. In the JFET the transverse electric field across the reverse biased PN junction
controls the conductivity of the channel.
c. The gate leakage current in a MOSFET is of the order of 10-12A. Hence the input
resistance of a MOSFET is very high in the order of 1010 to 1015 Ω. The gate
leakage current of a JFET is of the order of 10-9A., and its input resistance is of
the order of 108Ω.
d. The output characteristics of the JFET are flatter than those of the MOSFET,
and hence the drain resistance of a JFET (0.1 to 1MΩ) is much higher than that
of a MOSFET (1 to 50kΩ).
e. JFETs are operated only in the depletion mode. The depletion type MOSFET
may be operated in both depletion and enhancement mode.
g. Special digital CMOS circuits are available which involve near zero power
dissipation and very low voltage and current requirements. This makes them
suitable for portable systems.
Students Note:
Refer standard textbooks in the subject for the in-depth detailed understanding of the concept. This
handout covers only the brief theoretical background and are not designed to cover the biasing
numericals and problems. For solving numerical refer the online video lectures by Dr. Samarth
Borkar, Goa College of Engineering. If any errors might have crept in inadvertently, kindly bring
them to my notice. samarthgec@[Link]
PART: 2 (Self-study)
Sampling Gates:
UJT, JFET and MOSFET Sampling gate,
Sample & Hold circuits.
Transistor bootstrap ramp generator.
[Link]
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