hange E hange E

XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

UNIT 6 : DESIGN OF COMBINATIONAL CIRCUITS

Introduction to Combinational circuits - Analysis and design procedures - Half
Adder, Full Adder-Half Subtractor, Full Subtractor- Parallel binary Adder, Parallel binary
Subtractor- Carry look ahead Adder- BCD Adder-Decoders- Encoders-Priority Encoder-
Multiplexers- MUX as universal combinational modules- Demultiplexers- Code
convertors- Magnitude Comparator.

6.1 Introduction to Combinational circuits

Combinational Logic Circuits are made from the basic and universal gates. The
output is defined by the logic and it is depend only the present input states not the
previous states.
Inputs and output(s) : logic 0 (low) or logic 1 (high).

Fig. Block diagram of a combinational circuits

Analysis and design procedures

The following are the basic steps to design a combinational circuits
1. Define the problem.
2. Determine the number of input and output variables.
3. Fix a letter symbols to the input and the outputs. (eg. A,B,C ,w, x, Y,F, etc)
4. Get the relationship between input and output from the truth table.
5. By using K-map obtain the simplified Boolean expression for the outputs.
6. Draw the logic diagram using gates.

Example : Design a combinational logic circuit with three inputs , the output is at logic 1
when more than one inputs are at logic 1.
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

Solution: Assume A, B, C are inputs and Y is output .

Truth table K map Simplification

Inputs Output
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1 Boolean Expression
1 0 0 0 Y=AC + BC + AB
1 0 1 1
1 1 0 1 Logic Diagram
1 1 1 1

6.2 Adder
The Basic operation in digital computer is binary addition. The circuit which
perform the addition of binary bits are called as Adder.

The logic circuit which perform the addition of two bit is called Half adder and three bit
is called Full adder.
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

Rules for two bit addition

0+0=0
0+1=1
1+0=1
1 + 1 = 102

6.2.1 Half Adder

The two inputs of the half adders are augend and addend, the outputs are sum and
carry.
Block diagram of Half adder
K-map simplification

Truth table of Half adder

Inputs Outputs
A B Carry Sum
0 0 0 0 Logic diagram
0 1 0 1
1 0 0 1
1 1 1 0

6.2.2 Full Adder

The three inputs of the full adders are augend , addend and the carry input from
the previous addition, the outputs are sum and carry
Block diagram of Full adder
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

Truth table K-map simplifications

Inputs Outputs
A B Cin Cout Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

The Full Adder can be implement using Two Half Adders and OR gates

The expression for sum is

The Expression for carry is

Logic Diagram
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

2.3 Subtractor
Subtractor is the logic circuit which is used to subtract two binary number (digit)
and provides Difference and Borrow as a output. In digital electronics we have two
types of subtractor, Half Subtractor and Full Subtractor.

Rules for two bit addition

0-0=0
0 - 1 = 1 with borrow 1
1-0=1
1-1=0

2.3.1 Half Subtractor

Half Subtractor is used for subtracting one single bit binary digit from another single bit
binary [Link] truth table of Half Subtractor is shown below.

Truth table of Half adder K-map for Difference and Borrow

Inputs Outputs
A B Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Logic Diagram
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

2.3.2 Full Subtractor

A logic Circuit Which is used for Subtracting Three Single bit Binary digit is
known as Full [Link] inputs are A,B, Bin and the outputs are D and Bout.
Truth table K-map for D and Bout
Inputs Outputs
A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0 Logic Diagram
1 1 0 0 0
1 1 1 1 1

We can further simplify the function of the Difference (D)

 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

Simplified Logic diagram

2.4 Parallel Adder – Subtractor

2.4.1 Four bit Parallel binary Adder

In practical situations it is required to add two data each containing more than
one bit. Two binary numbers each of n bits can be added by means of a full adder
circuit. Consider the example that two 4-bit binary numbers B 4B 3B 2B 1 and A 4A 3A 2A
1 are to be added with a carry input C 1. This can be done by cascading four full adder
circuits. The least significant bits A 1, B 1, and C 1 are added to the produce sum output
S1 and carry output C 2. Carry output C 2 is then added to the next significant bits A2 and
B2 producing sum output S 2 and carry output C 3. C 3 is then added to A3 and B3 and so
on. Thus finally producing the four-bit sum output S 4S 3S 2S 1 and final carry output
Cout.
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

[Link] diagram of 4 bit binary parallel Adder

2.4.2 Four Bit Parallel Binary Subtractor

We can design a four bit parallel subtractor by connecting three full subtractors and one
half subtractor. In the figure A = A3 A2 A1 A0 is minuend B = B3 B2 B1 B0 is subtrahend
giving the difference D = D3 D2 D1 D0.

[Link] diagram of 4 bit binary parallel Subtractor

The subtraction operation can be performed using 1’s and 2’s complement addition, so
we can design Full subtractor using Full Adder.

[Link] bit binary subtractor using Full Adder

2.4.3 Parallel binary Adder – Subtractor

 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

The addition and subtraction operations can be perform using a common adder
circuit, where a EX-OR gate is connected in the second input along with the mode
selection bit M. if M=0 the circuit act as a adder, M=1 then substractor. If M=0 then
output of the EX-OR gate is B act as adder, if M=1 then B’ act as a subtractor.

[Link] binary Adder – Subtractor

2.4.4 Carry look ahead Adder

In the parallel adder the carry input of each stage is depends on the carry output
of the previous stage. This processes leads to time delay in [Link] delay is called
propagation delay. The process can be speeding up by eliminating the inter stage carry
delay called look ahead carry addition. In uses two functions carry generate and carry
propagate.

[Link] Adder Circuit

The output sum and carry can be expressed as

 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

Gi is called carry generate and Pi is called carry propagate.

The Boolean function for the carry output of each stage can be

From the above functions it can be seen that C 4 does not have to wait for C3 and
C2. All the carries are propagating at the same time.

[Link] diagram of a look-ahead carry generator

 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

6.5 BCD Adder

In digital system, the decimal number is represented in the form of binary coded
decimal (BCD).The ten digit (0-9) decimal numbers are represented by the binary digits.
The circuit which add the two BCD number is called BCD adder. The BCD cannot be
greater than 9. The representation of the BCD number as follows, consider the 526 it
can be expressed as

There are three different cases in BCD Addition

i)Sum is less than or equal to 9 with carry 0
Consider the addition of two BCD numbers 6 and 3, The addition is performed as
normal binary addition

ii)Sum is greater than 9 with carry 0

consider the number 6 and 8 in BCD
The sum is invalid BCD number, Add the sum with correction number 6

After addition of 6 carry is produced into the second decimal position.

iii) Sum equals 9 or less with carry 1
Consider the addition of 8 and 9 in BCD.
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

The result 0001 0001 is valid BCD number but it is incorrect. Add 6 to get correct
number.

The procedure for BCD addition is

1. Add two BCD numbers using ordinary binary addition.
2. If four bit sum is less than or equal to zero, then correction is needed.
3. If the four bit sum is greater than 9 or if carry is generated then add 0110.

Implementation of BCD Adder

We require 4-bit binary adder for initial addition, Logic circuit to detect sum greater than 9, and
second 4 bit binary adder to add 0110.
The following truth table is used to design a circuit for the sum, which is greater than 9

Inputs Output K map for carry (Y) identification

S3 S2 S1 S0 Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0 Y = S3S2 + S3S1
1 0 0 0 0
1 0 0 1 0 If Y=1 add 0110 using binary adder
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

Block diagram of Binary Adder

[Link] diagram of BCD adder

The binary adder add two BCD numbers, ifcarry is ‘0’ nothing to be added. If carry is
‘1’ add 0110 with the sum, consider the overall carry from the first stage of the addition.
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

Example : Design an8-bit BCD adder using IC 74283.

Solution: Use two 4-bit BCD adder to design 8-bit binary adder.

Fig. 8- bit BCD Adder using IC 74283

6.6 Decoder
Decoder is a combinational circuit.

It has N inputs and 2N outputs.

2 to 4 Decoder
It has 2 inputs and 22 = 4 outputs.
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

Circuit Diagram

Truth Table

Logic Diagram
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

2 to 4 Decoder with Enable input

Truth Table

Logic Diagram
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

3 to 8 Decoder
It has 3 inputs and 23 = 8 outputs.
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

Logic Diagram

6.7 Encoders
Encoders is a combinational circuit which takes 2N inputs and gives out N outputs, the
enable pin should be kept 1 for enabling the circuit.

4 to 2 Encoder
It has 22 inputs and 2 outputs.
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

Truth Table

6.7.1 Priority Encoders

A Priority Encoder works opposite of the decoder circuit. If more than one input is
active, the higher order input has priority.

4 to 2 Priority Encoders

D0-D3 - inputs

A1,A0 – outputs

Active (A)– Valid indicator. It indicates the output is valid or not

Output is invalid when no inputs are active .i.e, A=0

Output is valid when at least one input is active .i,e, A=1

 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

Truth Table

K-map simplification
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

Logic Diagram

3 to 8 Priority Encoder

6.8 Mutliplexer (Mux)

Multiplexer is a combinational circuit that selects binary information from one of many
inputs and directs it into single output.

The selection of particular input is controlled by a set of selection line

Mutliplexer has 2n inputs, n select line (control input) and one output
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

It also called as Data selector

2 to 1 Multiplexer

has 21 inputs, 1 select line and one output

Circuit diagram

4 to 1 MUX

4 to 1 MUX has 22 = 4 inputs, 2 select line and one output

 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

8 to1 MUX
8 to1 MUX has 23 = 8 inputs, 3 select line and one output
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

6.8.1 MUX as universal combinational modules

Each minterm of the function can be mapped to a data input of the multiplexer.
For each row in the truth table, where the output is 1, set the corresponding data input
of the mux to [Link] the remaining inputs of the mux to 0.

Example 1: Implement the following Boolean function using 4:1 MUX

F(x,y,z) = Σm(1, 2, 6, 7)

Truth Table

Multiplexer Implementation
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

Example 2: Implement the following Boolean function using 8:1 MUX

F(A,B,C,D) = Σm(1, 3, 4, 11,12-15)

 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

6.9 Demultiplexer (DEMUX)

Demultiplexer has 2n outputs , n select lines, one input.

A demultiplexer is also called a data distributor.

1-to-2 demultiplexer
has 22 outputs , 2 select lines, one input.

The truth table

Logic diagram
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

ww
om

om
k

k
lic

lic
C

C
.c

.c
w

w
tr re tr re
.

.
ac ac
k e r- s o ft w a k e r- s o ft w a

1-to-4 Demultiplexer

It has one input,2 select lines,4 outputs

The truth table

 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
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ww
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Logic Diagram

1-to-8 Demultiplexer

Has one input

3-select lines

8-outputs

The truth table

 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
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C
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Logic Diagram
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
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C

C
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 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
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1-to-8 DEMUX using Two 1-to- 4 Demultiplexers

1-to-8 demultiplexer can be implemented by using two 1-to-4 demultiplexers with a

proper cascading.

In the above figure, the highest significant bit A of the selection inputs are connected to
the enable inputs such that it is complemented before connecting to one DEMUX and to
the other it is directly [Link] this configuration, when A is set to zero, one of the
output lines from Y0 to Y3 is selected based on the combination of select lines B and C.
Similarly, when A is set to one, based on the select lines one of the output lines from Y4
to Y7 will be selected.

6.9.1 Applications of Demultiplexer

 Synchronous data transmission systems

 Boolean function implementation (as we discussed full subtractor function above)
 Data acquisition systems
 Combinational circuit design
 Automatic test equipment systems
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
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 Security monitoring systems (for selecting a particular surveillance camera at a

time), etc.

6.10 CODE CONVERTORS

Numbers are usually coded in one form or another so as to represent or use it as required. For
instance, a number ‘nine’ is coded in decimal using symbol (9)d. Same is coded in natural-
binary as (1001)b. While digital computers all deal with binary numbers, there are situations
wherein natural-binary representation of numbers in in-convenient or in-efficient and some other
(binary) code must be used to process the numbers.

One of these other code is gray-code, in which any two numbers in sequence differ only by one
bit change. This code is used in K-map reduction technique. The advantage is that when
numbers are changing frequently, the logic gates are turning ON and OFF frequently and so are
the transistors switching which characterizes power consumption of the circuit; since only one
bit is changing from number to number, switching is reduced and hence is the power
consumption.

Let’s discuss the conversion of various codes from one form to other.

6.10.1 BINARY-TO-GRAY
The table that follows shows natural-binary numbers (upto 4-bit) and corresponding gray codes.
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
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Looking at gray-code (G3G2G1G0), we find that any two subsequent numbers differ in
only one bit-change.

The same table is used as truth-table for designing a logic circuitry that converts a given
4-bit natural binary number into gray number. For this circuit, B3 B2 B1 B0 are inputs
while G3 G2 G1 G0 are outputs.

K-map for the outputs:

And G3 = B3

So that’s a simple three EX-OR gate circuit that converts a 4-bit input binary number
into its equivalent 4-bit gray code. It can be extended to convert more than 4-bit binary
numbers.
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

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B

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to

to
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6.10.2 Gray-to-Binary
Truth-table:

Then the K-maps:

And B3 = G3
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

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N

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Y

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U

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B

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to
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The realization of Gray-to-Binary converter is

6.11 Comparators

 A comparator will evaluate two binary strings and output a 1 if the two strings are
exactly the same.
 The Exclusive-NOR (Equality gate) is used to perform the comparison.
 One Exclusive-NOR is used per pair of Binary bits and the outputs of all
Exclusive-NORS are ANDed together.

 The 7485 is a 4-bit magnitude comparator.

A magnitude comparator will determine if A = B, A > B or A < B.
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

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B

B
to

to
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 Expansion inputs are provided on the 7483 so that word sizes larger then 4-bits
may be compared.
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XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

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B

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to
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Magnitude Comparator
Definition
A magnitude comparator is a combinational circuit that compares two numbers A & B to
determine whether:
A > B, or
A = B, or
A<B
2-bit magnitude comparator
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
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4-bit magnitude comparator

Inputs: 8-bits (A ⇒ 4-bits , B ⇒ 4-bits)
A and B are two 4-bit numbers
_ Let A = A3A2A1A0 , and
_ Let B = B3B2B1B0
_ Inputs have 28 (256) possible combinations
_ Not easy to design using conventional techniques
The circuit possesses certain amount of regularity⇒ can be designed algorithmically.
Design of the EQ output (A = B) in 4-bit magnitude comparator
 hange E hange E
XC di XC di
F- t F- t
PD

PD
or

or
!

!
W

W
O

O
N

N
Y

Y
U

U
B

B
to

to
ww

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k

k
lic

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C

C
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w

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tr re tr re
.

.
ac ac
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