Study Material

DIGITAL SYSTEM DESIGN (PCC-ECR302)

MODULE IV
SEQUENTIAL CIRCUITS
Table of Contents

Content Page No

5.1 Introduction 5.3

5.1.1 Sequential circuit models 5.3
5.1.2 Differentiate between combinational and sequential circuits 5.4
5.2 Latches 5.5
5.2.1 Active high SR latch 5.5
5.2.2 NAND based S-R latch 5.7
5.3 Flip-flops 5.8
5.3.1 Comparison between latches and Flip-flops 5.8
5.4 S-R flip-flop 5.9
5.4.1 Block Diagram 5.9
5.4.2. Circuit Diagram and Working Principal 5.10
5.4.3 Present state – next state table and K-map simplification 5.11
5.4.4 Excitation table of S-R Flip-flop 5.11
5.4.5 State diagram of S-R flip-flop 5.12
5.5 D Flip-flop 5.12
5.5.1 Block Diagram 5.12
5.5.2 Truth Table 5.12
5.5.3 Circuit Diagram and working principal 5.13
5.5.4 Present state – next state table and K-map simplification 5.13
5.5.5 Excitation table of D flip-flop 5.13
5.5.6 State diagram 5.14
5.6 J-K Flip-flop 5.14
5.6.1 Block Diagram 5.14
5.6.2 Truth table, Circuit diagram and working principle of J-K flip-flop 5.15
5.6.3 Present state – next state table and K-map simplification 5.16
5.6.4 Excitation table 5.16
5.6.5 State diagram 5.16
5.6.6 Race around condition 5.17
5.7 Edge triggered flip flops 5.17
5.8 Master Slave JK flip flop 5.18
5.8.1 Block Diagram 5.18
5.8.2 Circuit Diagram and working principal 5.18
5.9 Realization of one flip-flop using other flip-flops 5.19
 5.9.1 Realization of D flip-flop using S-R flip-flop 5.19
5.9.2 Realization of S-R flip-flop using D flip-flop 5.21
5.9.3 Realization of J-K flip-flop using S-R flip-flop 5.22
5.9.4 Realization of S-R flip-flop using J-K flip-flop 5.24
5.9.5 Realization of D flip-flop using J-K flip-flop 5.26
5.9.6 Realization of J-K flip-flop using D flip-flop 5.28
5.10 T Flip-flop 5.29
5.10.1 Present state – next state table and K-map simplification 5.30
5.10.2. Excitation table 5.30
5.11. Counter 5.30
5.12 Asynchronous (ripple) counter 5.31
5.12.1 4-bit ripple / Asynchronous counter 5.32
5.12.2 3-bit ripple/asynchronous up counter 5.33
5.12.3 Asynchronous Down Counter 5.34
5.12.4 4-bit ripple down counter 5.35
5.12.5 3-bit ripple/asynchronous up-down counter 5.36
5.13 MOD ripple counter 5.38
5.13.1 MOD Number 5.38
5.13.2. Ripple counter with modulus <2^n – MOD-6 ripple counter 5.38
5.14. Synchronous Counter 5.39
5.14.1 Synchronous Up Counter 5.39
5.14.2 Synchronous Down Counter 5.41
5.14.3 Synchronous Up/Down Counter 5.42
5.15 MOD Synchronous Counter 5.43
5.15.1 MOD -3 Counter 5.43
5.15.2 MOD -6 Counter 5.45
5.15.3 MOD -10 Counter / Decade Counter 5.48
5.16. Registers 5.52
5.17 Types of shift registers 5.53
5.18 Different ways to transfer/move data 5.54
5.19 Serial–in serial–out shift register 5.55
5.19.1 Serial–in serial–out shift register using JK flip-flop 5.56
5.20. Serial–in parallel–out shift register 5.56
5.21 Parallel-in serial-out shift register 5.57
5.22 Parallel–in parallel–out shift register 5.58
5.23 Bidirectional shift register 5.58
5.24 Universal shift register 5.59
5.25 Ring counter 5.60
5.26 Johnson counter 5.61
5.27 Applications of shift registers 5.63
5.28 Exercise 5.64
5.1 Introduction
There are two main categories of digital circuits: combinational and sequential circuits. In the
combinational circuits, the output at any instant of time depends only on the present state of the input
variables. Their working is described by a truth table consisting of all possible input and output values.
All combinational circuits are just a combination of various types of logic gates, which are mainly used as
decision-making elements in a system.
In real time scenario, only combinational circuits are not sufficient for a logic system but require
knowledge of past values of some logic variables to finalize the output. Such circuits normally generate
some kind of sequence, hence popularly known as sequential circuits. In sequential logic circuit, bistable
devices (latches or flip-flops) are used to store two states i.e. 0 or 1. These bistable devices progress
through different states depending upon the input and output values of the circuit. The output values of
such circuit depend upon present as well as past inputs. Functioning of such complex circuit cannot be
explained by a simple truth table. Therefore, for all sequential circuits a new approach of state tables and
state diagram are normally preferred to describe the working. A sequential circuit is the circuit, in which
the present output is a function of present and previous sequence of inputs.
To understand a sequential logic circuit, it is necessary to know the internal state of the circuit. The
internal state of the circuit is determined by the nature of sequential circuit constructed using latches, flip-
flops, counters, shift registers or memories. In this module, sequential circuits are described using the
finite state model.
5.1.1 Sequential circuit models
The sequential circuit can be represented by a basic modeling structure to understand how flip-flops play
important role in sequential circuits. Models provide a means to represent an idea, concept or process
mathematically or graphically. This helps in enhancing the understanding of sequential circuits.
Sequential circuits are essentially consisting of combinational circuits with feedback. Figure represents a
generalized block diagram of sequential circuits. The combinational logic circuit (containing AND, OR
etc.) has two sets of inputs i.e. the external (present) inputs and the (past) inputs fed back from output
through memory. The memory stores an output from the combinational circuit that is fed back to the
combinational logic input to constitute the past inputs (present state) of the circuit. The output from the
combinational logic that forms the inputs to the sequential circuit elements constitutes the next state of the
circuit.
5.1.2 Differentiate between combinational and sequential circuits

Parameter Combinational circuits Sequential circuits

Principle At any time, outputs are dependent At any time, outputs are dependent not
on combination of present inputs only on present inputs but also on past
inputs/outputs

Memory Not present Required to store past inputs

Speed Faster Slower

Design Easier Comparatively difficult to design

All digital designers use the flip-flop for a sequential device that normally samples its inputs and changes
its output only when a clock signal is changing. On the other hand, most digital designers use latch for a
sequential device that watches its inputs continuously and can change its outputs at any time.
Latches and FFs are bistable multivibrator. Latches and flip-flops differ in the method used for changing
their state or method of gating or clocking. Latches are treated as asynchronous bistable multivibrator and
Flip flop is a synchronous bistable circuit. Latches are usually level triggered and flip flops are edge
triggered. Both these memory devices are capable storing 1-bit data.
In digital systems, a bistable device has two stable states 0 (RESET) and 1(SET). Flip-flops have a clock
input and synchronous outputs. Latches are asynchronous and their outputs can change at any time. It
may have an enable input. There are two types of Latches - SR and D latch. There are 4 types of Flip
flops: SR FF, D, FF, JK FF and T FF.
5.2 Latches

Latches are basic memory elements used in digital circuits to store and retain data. They are sequential logic
devices that can change state based on input signals and can hold that state even when the input signals change.
Unlike flip-flops, latches do not have a clock signal and can change state as soon as their input changes.

The simplest sequential circuit is the basic bistable element. It is constructed with two inverters connected
sequentially in a loop. It has no inputs and two outputs labelled as Q and Q’. As there are no inputs, it is not
possible to change the values of Q and Q’.

Let us assume Q=1 after power-on. As Q is connected to the input of second inverter, therefore Q’ is 0. A 0 at
Q’ is fed to input of first inverter and it will produce 1 at Q output, which we had assumed. Similarly, if we
assume Q=0 then we will get Q’ as 1 and we will get a stable state. Thus, there could be two stable state,
hence it is referred to as bistable element. This indicates that the bistable element has memory and it
remembers the state of the circuit.

The main disadvantage of bistable element is that it does not have any inputs, indicating that it is not possible
to change the information that is stored in it. In order to change the information, it is necessary to add inputs to
the gate which acts as an inverter. Thus we can use NOR and NAND gates for simple sequential circuit i.e.
latch.

There are four types of latches (i) Active high SR latch (ii) Active low SR latch (iii) Gated SR latch and (iv)
D-latch. Let us discuss the construction and working of these latches.

5.2.1 Active high SR latch

To store 0 and 1 we need a one bit memory cell. A basic storage element is called as latch and it is capable
of latching 0 or 1. Let us now study the SR latch. There are two types SR latch architectures based on
type of gates used in construction - NOR latch and NAND latch. Let us discuss the SR latch with Active
High Inputs.
The SR latch has two inputs: S (Set) and R (Reset). It has two stable states: Set state (Q = 1, Q' = 0) and
Reset state (Q = 0, Q' = 1). When S is asserted (set to 1) and R is deserted (reset to 0), the latch goes into
the Set state. When R is asserted (set to 1) and S is deserted (reset to 0), the latch goes into the Reset state.
The latch circuit is constructed using two cross-coupled NOR gates as shown in figure 4. In addition to
the complementary outputs Q and Q’, there are two inputs R (RESET) and S (SET). The SR latch can be
in any one of the two states: a SET state when output Q=1 or a RESET state when output Q=0.
To study the action of SR latch, it is necessary to recall the truth table of two input NOR gate.
In NOR gate, when both inputs are 00 then output is 1 and when either or both inputs are 1 then output of
NOR gate is 0. Truth table of NOR gate will be required in understanding the operation of SR latch.

Let us now understand the SET and RESET action of latch. When S=1, the Q output of latch should be set
to Q=1. And when R=1, then the Q output will be reset to 0.
Let us now start with the SET action of latch by making S=1 and R=0. This condition will store 1 in latch.
With S=1, second NOR gate will produce Q’=0. This can be checked from the truth table of NOR gate.
When one of the inputs is 1, the output of NOR gate will be 0. Similarly, with R=0, and Q’=0 the first
NOR gate produces Q=1. The outputs are complement of each other. Thus with S=1 and R=0, produces
SET condition.
Let us see whether the data is stored or not. If we remove the inputs i.e. if we make S=0 then outputs
should not change. When S=0 and R=0, then the second NOR gate will keep Q’=0 with inputs Q=1 and
S=0. Similarly the first NOR gate with the inputs R=0 and Q’=0, produces Q=1. This clearly indicates
that when S=0 and R=0, the outputs maintains the last value i.e. it has stored the last state. This SR=00
condition is also called as memory condition. In short, we can say binary 1 is latched i.e. stored into the
circuit.
Let us now understand the RESET action of latch by making S=0 and R=1. With R=1, the first NOR gate
will produce Q=0. This can be checked from the truth table of NOR gate. When one of the inputs is 1, the
output of NOR gate will be 0. Similarly, with S=0, and Q’=1 the second NOR gate produces Q=1. The
outputs are complement of each other. Thus with S=0 and R=1, produces RESET condition.
If we remove R input i.e. when R=0 and S=0, the output of the first NOR gate will keep Q=0 with inputs
Q’=1 and R=0. Similarly the second NOR gate with the inputs R=0 and Q’=1, produces Q=0. This clearly
indicates that when S=0 and R=0, the outputs maintains the last value i.e. it stores the last state. Thus with
SR=00 condition, the outputs of latch are unchanged and maintains the last state. In short we can say
binary 0 is latched i.e. stored into the circuit.
Let us consider the last condition, when both S=1 and R=1. Both NOR gates will produce outputs 0 i.e.
Q=0 and Q’=0. In this condition, both outputs are 0. Actually Q and Q’ should be complement of each
other. Thus, there is contradiction. Therefore, S=1 and R=1 input condition is not allowed.
The truth table of S-R latch is as follows:

Inputs Outputs
Action / Comments
S R Qn+1 𝐐̅̅𝐧̅̅+̅𝟏̅

0 0 Qn Qn̅̅ No change (last state)

0 1 0 1 Reset

1 0 1 0 Set

1 1 ? ? Forbidden / Invalid

5.2.2 NAND based S-R latch

5.3 Flip-flops
Latches and flip-flops are memory devices used in the construction of Sequential circuits. These memory
devices can remain in the same state even if the inputs are removed. These devices can hold a binary
value 0 or 1 until is forced to change state.
Latches and flip-flops are bistable devices. However, they differ in the way the change their state. Latches
are asynchronous bistable devices where latch accepts the input signal as soon as it changes and does not
require any external timing signal. A flip-flop is a memory device, which accepts the input only in
synchronism with the timing signal known as the clock.
The clock may be in the form of level, or an edge or a pulse. A level trigger means that the flip-flop
accepts the input depending upon voltage -high level or low level. An edge trigger changes the flip-flop
condition at rising edge (positive edge) or falling (negative) edge. The low to high transition on the clock
is a rising edge or positive going edge and high to low transition is known as falling edge or negative
going edge. In addition, there is pulse trigger signal on the clock to change the state.
There are four types of flip-flops used for storing 1-bit information namely SR, D, JK and T flip flop.
Flip-flops are digital logic circuits that can be in one of two states.
Flip-flops maintain their state indefinitely until an input pulse called a trigger is received. When a trigger
is received, the flip-flop outputs change state according to defined rules and remain in those states until
another trigger is received.
5.3.1 Comparison between latches and Flip-flops
Latches and flip flops are sequential circuits capable of storing an information and find applications in
many electronic gadgets. Figure-1 indicates the comparison table for latches and flip-flops. First column
in the table includes important keywords or parameters used for the comparison.
Latches are asynchronous bistable multivibrator devices whereas flip-flops are synchronous bistable
multivibrator devices. Latches and flip-flops are the basic elements and these are used to store
information. One flip-flop and latch can store one bit of data, hence referred to as 1-bit memory cell.
Latch can hold the data without gating or clocking signal. Certain latches can use enable signal for gating
the data into the latch. It changes state whenever the enable is asserted. Flip-flops can store the data in
synchronism with a clock signal. Flip flops can be clocked as level, edge or pulse triggering methods.
Parameters Latches Flip flops
Principle Asynchronous bistable Synchronous bistable
Storage 1-bit memory cell 1-bit memory cell
Gating or clocking Either absent or use of enable signal Level , edge or pulse trigger
mechanism
State change Checks the input continuously and Checks the input continuously
changes the output as soon as the and changes the output only at
input changes (after a small time determined by clock
propagation delay).
Sensitivity Similar to Level sensitive FF Edge or pulse sensitive FF

The main difference between the latches and flip-flops is how state changes. A latch checks input
continuously and changes the output whenever there is a change in input. But, flip flop is a combination
of latch and a clock which continuously checks input and changes the output only at time determined by
the clock. Latches can be treated just similar to a level triggered flip-flop, where the voltage level decides
the enabling of the flip-flop. Flip flops can be either edge or pulse sensitive.
5.4 S-R flip-flop
An S-R Flip-Flop (Set-Reset Flip-Flop) is a type of sequential logic device that has two inputs, S (Set)
and R (Reset), and two outputs, Q (output) and Q̅ (complement of the output). It is also known as an S-R
latch with clock enable. The S-R flip-flop can store one bit of binary data and can change its state based
on the inputs and clock signal.
5.4.1 Block Diagram:
The block diagram of S-R flip-flop is as follows:
5.4.2. Circuit Diagram and Working Principal
S-R flip-flop by using NOR gate is as follows

S-R flip-flop by using NAND gate is as follows

When Clock is 1 and both S and R inputs are 0 then inputs to latch are 11. Therefore, Q and Q’ will not
change. The output remains in the last state. The output of SR flip-flop will be RESET, if clock input is
High and SR inputs are 01. The SR flip-flop output goes High when clock input is 1 and SR inputs are 10.
This is a SET condition for the flip-flop. If both SR inputs are high (1) then the flip flop generates invalid
output i.e. both Q and Q’ are at 0 level. This generates invalid condition, which is not allowed. When
clock level is 0 then irrespective of S and R inputs latch inputs at high (1) state. Therefore, both the
outputs do not change. Thus, last state is maintained.
5.4.3 Present state – next state table and K-map simplification

5.4.4 Excitation table of S-R Flip-flop

5.4.5 State diagram of S-R flip-flop

5.5 D Flip-flop
A D flip-flop (Data flip-flop) is a type of edge-triggered sequential logic device that stores and transfers
data based on the clock signal. It has a single data input (D), a clock input (CLK), and two outputs: Q
(output) and Q̅ (complement of the output). The D flip-flop transfers the data input (D) to its output (Q)
on the rising edge or falling edge of the clock signal, depending on its specific implementation.
5.5.1 Block Diagram

5.5.2 Truth Table

5.5.3 Circuit Diagram and working principal

When the clock input is high, the Q output follows the input D. It is possible to store data 0 or 1 in the
flip-flop. When D=0 then flip flop output is RESET state and at D=1, the flip flops stores 1 i.e. SET state.
During low level of clock irrespective of the value of D input, the Q output of flip flop do not change
irrespective of D input. Thus, flip-flop keeps the last state. As the inputs appear at output after some delay,
hence D flip flop is also called as Delay flip flop.
5.5.4 Present state – next state table and K-map simplification
5.5.5 Excitation Table of D flip-flop

5.5.6 State diagram

5.6 J-K Flip-flop

5.6.1 Block Diagram
A J-K flip-flop is a type of edge-triggered sequential logic device that has two inputs, J (Jump) and K
(Kill), and two outputs, Q (output) and Q̅ (complement of the output). The J-K flip-flop is more versatile
than the S-R flip-flop because it can be used to implement all other types of flip-flops, including D flip-
flops and T flip-flops.
5.6.2 Truth table, Circuit diagram and working principle of J-K flip-flop
The Truth table J-K flip-flop is as follows:

The JK flip-flop is an SR flip-flop with feedback which enables only one of its two inputs to be active at
any given time. When clock is High (i.e. logic 1) and both JK inputs are 00 then, the latch output do not
change. Thus, JK flip flop holds the last state. The flip-flop enters into RESET mode (i.e. Q=0), when J=0
and K=1 with high state on clock. When J=1 and K=0, with clock input at High state, the output enter in
SET mode by setting Q as 1.
When clock as well as both J and K inputs are HIGH then output toggles from its previous state i.e. if
Q=0 then it becomes 1 and if Q=1 then it becomes0. Let us consider Q=0 and Q’=1 then output of J side
NAND gate provide 0 which changes the output to 1. Let us find out the change at k-side NAND gate. Q
is initially 0, the K side NAND will provide output as 1 and with new Q as 1 the final Q’ changes to 0
from 1. Now let us consider a case when clock is inactive. I.e. when clock is Low (0), the outputs do not
change irrespective of the JK inputs. This is once again the hold state of JK flip-flop.
5.6.3 Present state – next state table and K-map simplification

5.6.4 Excitation table

5.6.5 State diagram

5.6.6 Race around condition
The unpredictable or invalid condition of SR flip flop when both inputs are 1(S=R=1) is eliminated in a
JK flip flop by using the feedback connection from outputs to the inputs. Therefore, changes in the output
results change in input.
Consider for example that the inputs J=K=1 and CLK=1. Let us assume Q=0. A clock pulse width t p is
applied. After a time ∆t equal to propagation delay through two NAND gates in series the output will
change to Q=1. Now we have J=K=1 and Q=1 and after another time ∆t the output will change back to
Q=0.
Hence, we conclude that as long as CLK=1, the outputs will oscillate back and forth between 0 and 1. At
the end of clock, the output Q value is uncertain. This situation is referred to as the race around condition.

5.7 Edge triggered flip flops

The problem of race around condition in the level triggered flip flop can be solved by ‘edge triggering’
the flip flop.
Positive edge triggered flip-flops are those in which state transitions take place only at positive going (0
to 1) edge of the clock signal. Positive edge triggering is indicated by a triangle at the clock terminal of
the flip-flop as shown in figure.
Negative edge triggered flip flops are those in which state transitions take place only at negative going (1
to 0) edge of the clock signal. Negative edge triggering is indicated by a triangle along with small circle
or bubble at the clock terminal of the flip-flop.
5.8 Master Slave JK flip flop
A Master-Slave JK Flip-Flop is a type of digital flip-flop circuit that has two stages: a master stage and a
slave stage. It is commonly used in digital circuits for storing and transferring data. The circuit uses two
JK flip-flops, with the output of the master flip-flop connected to the input of the slave flip-flop, creating
a more stable and reliable flip-flop operation.
The master stage consists of a JK flip-flop. It operates in response to the clock signal (CLK) and the input
J and K signals. When the clock signal is high (positive edge or negative edge, depending on the specific
design), the master stage takes the current values of J and K inputs and sets the internal state accordingly.
The slave stage also consists of a JK flip-flop. However, the slave stage is controlled by the inverse of the
clock signal (CLK'). When the clock signal is low, the slave stage takes the output from the master stage
and transfers it to its internal state.
5.8.1 Block Diagram

5.8.2 Circuit Diagram and working principal:

During the rising (positive edge) or falling (negative edge) edge of the clock signal, the master stage's
output is determined based on the current values of J and K inputs. This state is latched and held during
the entire low phase of the CLK signal.
The output of the master stage is then fed into the slave stage, which updates its internal state when the
clock signal goes low. Since the slave stage operates on the falling edge of the clock signal, it changes its
state only after the master stage has latched the correct value during the rising/falling edge of CLK.
The feedbacks from slave Q and Q’ are connected to master JK inputs. The master section assumes the
state determined by the J and K inputs at the positive going edge of the clock pulse and the slave section
at the negative going edge of the clock pulse. The state of the slave then immediately appears at Q and Q’
outputs. Q output of slave is connected back to NAND gate which receives K input of master and Q’
output is connected back into NAND gate, which receives J, input of master.

When J=0 and K=0 at pulse triggering, there is no change at the output of the flip flop. In short, the flip-
flop holds the last state. When J=0 and K=1 at pulse trigger, the flip flop enters in Reset state i.e. Q=0.
Flip flop enters into SET state, when J=1 and K=0 at pulse clock transition. When J=1 and K=1 at
triggering transition, the flip flop toggles i.e. goes to the complement of the present state. Note that, in this
pulse triggering method, the flip-flop changes the state only once after a clock pulse. Thus, the problem of
racing is avoided.
5.9 Realization of one flip-flop using other flip-flops
5.9.1 Realization of D flip-flop using S-R flip-flop
A D flip-flop can be realized using two S-R (Set-Reset) flip-flops and some additional logic gates. The D
flip-flop has a single data input (D) and two outputs (Q and Q̅). The Q output follows the D input, while
the Q̅ output is the complement of the Q output.
Present state – next state table for D flip-flop
Excitation table for D flip flop realization using S-R flip-flop

Therefore, by K-map simplification the value of S and R are obtained.

The diagram for realization of D flip-flop using S-R flip-flop is as follows:

5.9.2 Realization of S-R flip-flop using D flip-flop
Present state – next state table for S-R flip-flop

Excitation table for S-R flip flop realisation using D flip-flop

5.9.3 Realization of J-K flip-flop using S-R flip-flop
Present state – next state table for J-K flip-flop
Excitation table for J-K flip flop realisation using S-R flip-flop
5.9.4 Realization of S-R flip-flop using J-K flip-flop
Present state – next state table for S-R flip-flop
Excitation table for S-R flip flop realisation using J-K flip-flop
5.9.5 Realization of D flip-flop using J-K flip-flop
Present state – next state table for D flip-flop

Excitation table for D flip flop realisation using J-K flip-flop

5.9.6 Realization of J-K flip-flop using D flip-flop
Present state – next state table for J-K flip-flop

Excitation table for J-K flip flop realisation using D flip-flop

5.10 T Flip-flop
A T flip-flop (Toggle flip-flop) is a type of digital flip-flop circuit that has a single input (T) and two
outputs (Q and Q̅). The T flip-flop is called "toggle" because its output toggles (changes state) each time
the T input transitions from 0 to 1 (rising edge) while the clock signal is active.
The block diagram of a T flip-flop is as follows:
5.10.1 Present state – next state table and K-map simplification

5.10.2. Excitation table

5.11. Counter
In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of
times a particular event or process has occurred, often in relationship to a clock. The most common type
is a sequential digital logic circuit with an input line called the clock and multiple output lines. The values
on the output lines represent a number in the binary or BCD number system. Each pulse applied to the
clock input increments or decrements the number in the counter.
A counter circuit is usually constructed of a number of flip-flops connected in cascade. Counters are a
very widely used component in digital circuits, and are manufactured as separate integrated circuits and
also incorporated as parts of larger integrated circuits.
An electronic counter is a sequential logic circuit which has a clock input signal and a group of output
signals that represent an integer "counts" value. Upon each qualified clock edge, the circuit will increment
(or decrement, depending on circuit design) the counts. When the counts have reached the end of the
counting sequence (maximum counts when incrementing; zero counts when decrementing), the next clock
will cause the counts to overflow or underflow and the counting sequence will start over. Internally,
counters use flip-flops to represent the current counts and to retain the counts between clocks. Depending
on the type of counter, the output may be a direct representation of the counts (a binary number) or it may
be encoded.
Some counters provide a Terminal Count output which indicates that the next clock will cause overflow
or underflow. This is commonly used to implement counter cascading (combining two or more counters
to create a single, larger counter), by connecting the Terminal Count output of one counter to the Enable
input of the next counter.
The modulus of a counter is the number of states in its count sequence. The maximum possible modulus
is determined by the number of flip-flops. For example, a four-bit counter can have a modulus of up to 16
(2^4).
Counters are generally classified as either synchronous or asynchronous. In synchronous counters, all
flip-flops share a common clock and change state at the same time. In asynchronous counters, each flip-
flop has a unique clock and the flip-flop states change at different times.
Synchronous counters are categorized in various ways. For example:
 Modulus counter – counts through a particular number of states.
 Decade counter – modulus 10 counter (counts through ten states).
 Up/down counter – counts both up and down, as directed by a control input.
 Ring counter – formed by a "circular" shift register.
 Johnson counter – a twisted ring counter.

5.12 Asynchronous (ripple) counter

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock.
All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are
also called ripple-counters because of the way the clock pulse ripples it way through the flip-flops.
An asynchronous (ripple) counter is a "chain" of toggle (T) flip-flops wherein the least-significant flip-
flop (bit 0) is clocked by an external signal (the counter input clock) and all other flip-flops are clocked
by the output of the nearest, less significant flip-flop (e.g., bit 0 clocks the bit 1 flip-flop, bit 1 clocks the
bit 2 flip-flop, etc.). The first flip-flop is clocked by rising edges; all other flip-flops in the chain are
clocked by falling clock edges. Each flip-flop introduces a delay from clock edge to output toggle, thus
causing the counter bits to change at different times and producing a ripple effect as the input clock
propagates through the chain. When implemented with discrete flip-flops, ripple counters are commonly
implemented with JK flip-flops, with each flip-flop configured to toggle when clocked (i.e., J and K are
both connected to logic high).
In the simplest case, a one-bit counter consists of a single flip-flop. This counter will increment (by
toggling its output) once per clock cycle and will count from zero to one before overflowing (starting over
at zero). Each output state corresponds to two clock cycles, and consequently the flip-flop output
frequency is exactly half the frequency of the input clock.
5.12.1 4-bit ripple / Asynchronous counter
Fig shows a 4 bit binary ripple counter. As shown, a binary ripple counter is constructed using clocked JK
flip flops. The system clock, a square wave, drivers flip flop A. The output of C drives flip-flop D. The
overall propagation delay time of counter is the sum of individual delays of flip-flops. All the J and K
inputs are connected to VCC (1), which mean that each flip flop toggles on the negative edge of its clock
input.
Consider initially all the flip-flops to be in the logical 0 State (i.e. Q A = QB = QC = QD = 0). A negative
transition (1 to 0) in clock input which drives flip-flop A causes QA to change from logical 0 to logical 1.
Flip-flop B does not change its state since it also requires negative transition at its clock input i.e. it
requires its clock input (QA) to change from logical 1 to logical 0. With the arrival of the second clock
pulse to flip-flop A, QA goes from 1 to 0. This change of state creates the negative going edge needed to
trigger flip-flop B, and thus QB goes from 0 to 1. Before the arrival of the sixteenth clock pulse, all the
flip-flops are in the logical 1 State. Clock pulse 16 causes QA, QB, QC and QD to go to logical 0 states in
turn.
5.12.2 3-bit ripple/asynchronous up counter
The block diagram and truth table of 3-bit ripple/asynchronous up counter are as follows

5.12.3 Asynchronous Down Counter:

Let QA, QB, and QC represent the flip-flop output states as the counter goes through its sequence. The
truth table shows that the output QA (LSB) changes its state (toggle) at each negative transition of clock
as it does in the up-counter. The QB output changes state every time QA goes from LOW to HIGH, i.e.
when 𝑄̅̅𝐴̅ goes from HIGH to LOW; QC changes state each time QB goes from LOW to HIGH, i.e. when
𝑄̅̅𝐵̅ goes from HIGH to LOW. Thus, in down counter, each flip-flop, except the LSB flip-flop, must toggle
when the inverted output of the preceding flip-flop goes from HIGH to LOW.
The input pulses are applied to the clock input of A flip flop; the 𝑄̅̅𝐴̅ output serves as the clock input for
the B flip-flop; the 𝑄̅̅𝐵̅ output serves as the clock input for the C flip-flop. From the figure of waveforms,
it shows that QA toggles at the negative transition of the clock, QB toggles whenever QA goes from LOW
to HIGH, and QC toggles whenever QB goes from LOW to HIGH. Whenever QA and QB go HIGH, 𝑄̅̅𝐴̅
and 𝑄̅̅𝐵̅ go LOW, and it is this negative transition at 𝑄̅̅𝐴̅ and 𝑄̅̅𝐵̅ that triggers outputs QB and QC
respectively.

Therefore, in the down counter, the counter content is decremented by one for every negative transition in
clock.
5.12.4 4-bit ripple down counter
The block diagram and truth table of 4-bit ripple/asynchronous down counter are as follows
5.12.5 3-bit ripple/asynchronous up-down counter
The UP-DOWN counter is a combination of the up-counter and the down-counter. As the UP-DOWN
counter has the capability of counting upwards as well as downwards, it is also called multimode counter.
In an up counter each flip-flop is triggered by the normal output of the preceding flip-flop; in a down
counter, each flip flop is triggered by the inverted output of the preceding flip-flop. In both the counters,
the first flip-flop is triggered by the input pulses.
The block diagram and truth table of 3-bit ripple/asynchronous up-down counter are as follows

Here, three logic gates per stage are required to switch the individual stages from count-up and count-
down mode. The logic gates are used to allow either the non-inverted output or the inverted output of one
flip-flop to the clock input of the following flip-flop, depending on the status of the control inputs. When
the count up line is held at 1 while the count-down line is at 0, the lower AND gates will be disabled and
there outputs are zero. So, it will have no effect on the outputs of OR gates. Also, the upper AND gates
will be enabled, i.e. it will allow QA to pass through the OR gate and into the clock input of the B flip-
flop. Similarly, the QB and QC outputs will be gated into the clock input of flip-flop C and D respectively.
Thus, as input pulses are applied, the counter will count up and follow a natural binary counting sequence
from 0000 to 1111.
With COUNT-UP = 0, COUNT-DOWN = 1, the upper AND gates are disabled and the lower AND gates
are enabled, allowing 𝑄̅̅𝐴̅, 𝑄̅̅𝐵̅ and 𝑄̅̅𝐶̅ to pass through to the clock inputs of the following flip-flops. Thus
for this condition, the counter will count down as input pulses are applied.
When the control inputs are both 0 or 1, the counter will not count up or count down because the clock
inputs of B, C and D will be held constant at either 0 or 1. The flip-flop A will keep toggling because it is
always being clocked. This conditions are not normally used.
5.13 MOD ripple counter
5.13.1 MOD Number:
The MOD-number of a counter is the total number of states it sequences through in each complete cycle.
MOD-Number = 2n
Where n = Number of flip-flops.
The maximum binary number counted by the counter is 2n − 1. Thus a 4- flip-flop counter can count as
high as 24 − 1 = 15
5.13.2. Ripple counter with modulus < 𝟐𝐧 – MOD-6 ripple counter
A MOD-6 ripple counter is a type of asynchronous (ripple) counter that counts in a sequence from 0 to 5
(MOD-6) and then resets back to 0. It uses three flip-flops to represent the counter's binary state, as the
MOD-6 counter requires three bits to represent six different states (0 to 5). A MOD -6 ripple counter is
shown in figure.
Without the NAND gate, the counter functions as a MOD-8 binary counter, which counts from 000 to
111. However, the presence of the NAND gate alters this sequence as follows:
a. The NAND gate output is connected to the CLEAR inputs of each flip-flop. As long as the NAND gate
output is HIGH, it will have no effect on the counter. When the NAND gate output goes LOW, it will
clear all flip-flops, and the counter immediately goes to the 000 state.
b. The output of the counter QB and QC are given as inputs to the NAND gate. The NAND gate outputs
goes LOW whenever QB = QC = 1. This condition will occur when the counter goes from 101 state to the
110 state. The LOW at the NAND gate output will clear the counter to the 000 state. Once flip-flops have
been cleared, the NAND gate output goes back to HIGH, since QB = QC = 1 condition no longer exists.
c. Therefore, the counting sequence is 000 → 001 → 010 → 011 → 100 → 101 → 000 → ……
So, it essentially skips 110 and 111 states going only through six different states; thus it is a MOD-6
counter.
5.14. Synchronous Counter:
A synchronous counter is a type of digital counter that uses flip-flops and synchronous clock signals to
count in a predetermined sequence. Unlike asynchronous (ripple) counters, all the flip-flops in a
synchronous counter are triggered simultaneously by the same clock signal, ensuring that all bits of the
counter change state at the same time. This eliminates the ripple effect and provides more precise and
reliable counting.
5.14.1 Synchronous Up Counter:
Asynchronous counter is the simplest type of binary counters as it requires less hardware. But its speed of
operation is low because the propagation delay time of all flip-flop is cumulative and the total settling
time is the product of the total number of flip-flops and the propagation delay of single flip-flop. Another
problem encountered with ripple counter is the glitches at the decoding gate outputs. These problems can
be eliminated by applying clock pulses to all the flip-flop simultaneously, which is done in synchronous
counter. The speed of operation in a synchronous counter is limited by the propagation delay of control
gating and flip-flop.
In a 4-bit synchronous up-counter, the clock inputs of all the flip-flops are connected together so that the
input clock signal is applied simultaneously to each flip-flop. Also, only the LSB flip flop A has its J and
K inputs connected permanently to VCC, while J and K inputs of the other flip-flops are driven some
combination of flip-flop outputs. The J and K inputs of the flip-flop B connected with Q A output of flip-
fop A; the J and K of flip-flop C are connected with AND operated output of QA and QB; similarly the J
and K of flip-flop D are connected with AND operated output of QA, QB and QC. As shown in figure and
according to the truth table, the flip-flop A changes its state with the occurrence of negative transition of
each clock-pulse. The flip-flop B changes its state when Q A = 1 and when there is negative transition at
clock input. Flip-flop C changes its state when QA = QB = 1 and when there is negative transition at clock
input. Similarly, flip-flop D changes its state when QA = QB = QC = 1 and when there is negative
transition at clock input.
Total delay = propagation delay of one flip-flop + propagation delay of AND gate
The above total delay will be same irrespective of the number of flip-flops present in the counter, and it
will normally be much lower than that of asynchronous counter with the same number of flip-flops.
Therefore, the speed of operation of synchronous counters is limited only by the propagation delays of a
single flip-flop and an AND gate. Thus, the maximum frequency of operation of synchronous counters is
given by

1
fmax 
t p  tg
tp = propagation delay of one flip-flop
tg = propagation delay of one AND gate
5.14.2 Synchronous Down Counter
A parallel down counter can be made to count down by using the inverted outputs of the flip-flops to feed
the various logic gates.
5.14.3 Synchronous Up/Down Counter:
To form a parallel UP/DOWN counter, the control inputs (COUNT UP and COUNT DOWN) are used to
allow either the normal output or the inverted output of flip-flop to the J and K inputs of the following
flip-flop. A MOD-8 UP/DOWN counter which will count from 000 to 111 when the COUNT UP = 1 and
COUNT DOWN = 0 or from 111 to 000 when the COUNT UP = 0 and COUNT DOWN = 1, is shown is
figure.

A logical 1 on the COUNT UP line while COUNT DOWN = 0 enables AND gates 1 and 3 and disables
gates 2 and 4. This allows the QA and QB outputs through the AND gates to the J and K inputs of the
following flip-flops, so that the counter counts up as pulses are applied. The reverse action takes place
when COUNT UP = 0 and COUNT DOWN = 1.
5.15 MOD Synchronous Counter
5.15.1 MOD -3 Counter
MOD -3 counter is one with three states. To design a counter with three states the number of flip-flops
required can be found using the following equation

2n  N  2n1

where, n is the number of flip-flops required and N is the number of states present in the counter. For
N=3, from the above equation, n=2, i.e. two flip-flops are required to design.
Present state – next state table for MOD -3 counter

Excitation table for MOD -3 counter

In the first row of the above table, for the flip-flop B of the counter to change from present state 0 to next
state 0, the JBKB inputs required are 0d; for flip-flop A to change from present state 0 to next state 1, the
JAKA inputs required are 1d. Similarly, other entries are also made using the application table.
5.15.2 MOD -6 Counter
MOD -6 counter is one with three states. To design a counter with three states the number of flip-flops
required can be found using the following equation

2n  N  2n1

where, n is the number of flip-flops required and N is the number of states present in the counter. For
N=6, from the above equation, n=3, i.e. three flip-flops are required to design.
Present state – next state table for MOD -6 counter

Excitation table for MOD -6 counter

In the first row of the above table, for the flip-flop C of the counter to change from present state 0 to next
state 0, the JCKC inputs required are 0d; for flip-flop B to change from present state 0 to next state 0, the
JBKB inputs required are 0d; for flip-flop A to change from present state 0 to next state 1, the J AKA inputs
required are 1d;. Similarly, other entries are also made using the application table.
5.15.3 MOD -10 Counter / Decade Counter
To design a BCD or Decade counter (MOD-10) that has ten states i.e. 0 to 9 the number of flip-flops
required is four.
Present state – next state table for MOD -10 counter
Excitation table for MOD -10 counter

In the first row of the above table, for the flip-flop D of the counter to change from present state 0 to next
state 0, the JDKD inputs required are 0d; for the flip-flop C of the counter to change from present state 0 to
next state 0, the JCKC inputs required are 0d; for flip-flop B to change from present state 0 to next state 1,
the JBKB inputs required are 0d; for flip-flop A to change from present state 0 to next state 1, the J AKA
inputs required are 1d;. Similarly, other entries are also made using the application table.
5.16. Registers
In almost all cities, we see various big rolling displays advertising different products or sales. This is one
of the most popular applications of shift register. Text/image can enter from left or right and moves out
sequentially. Similarly, data can be loaded inparallel from top and leaves towards bottom. For long
distance data communication, shift register can convert slow parallel data into high speed serial over
single wire and serial to parallel at a receiver end. This helps in reducing the cost of data transmission.
Shift registers like counters are basically some form of sequential circuit. Unlike combinational circuit,
sequential circuit outputs are not only dependent of present inputs but also on the past inputs as well.
Flip flops are used for storing binary information. Single flip flop can store 1-bit binary data either 0 or 1.
To increase the storage capacity, we need to use group of flip flops. Register is a group of flip flops
connected together to store multiple bits. The n-bit register consist of n number of flip flops and is
capable of storing n-bit information. For example 8-bit register can store 8-bit data for a computer and
requires 8 flip flops. Binary data can be entered serially or parallel into the register. Similarly, the data can
be shifted out in serial or parallel out on every clock pulse.
Shift registers are classified into 4 types depending upon how the data is shifted in and shifted out either
serially or parallel. In addition, there are bidirectional shift registers, ring and Johnson counter. There are
MSI shift registers available commercially in TTL as well as in CMOS families.
5.17 Types of shift registers
Shift registers are a type of sequential logic circuit. Shift register has two important keywords. The first
one is shift and the second is register. Register is basically a group of flip flops connected in such a way
that binary number can be entered into the register. Single flip flop can store only ‘1’bit data. For storing
‘n’-bits, n flip flops are required for storage. Shift register is capable of storage as well as shift or data
transfer.
For handling the binary data, there are two main operations Shift-In for data entry and Shift-Out for data
transfer or exit. Both the operations can be implemented either bit by bit i.e. serially or all-bits-
simultaneously i.e. in parallel.
Shift registers can have serial or parallel inputs and outputs. There are some shift registers that have both
serial and parallel inputs and outputs as shown in figure 1.
Classification of shift register depends on how the data is shifted IN and shifted-OUT i.e. whether the
data input and output are serial or parallel. There are four basic types of shift registers:
1. Serial In Serial Out (SISO) shift register
2. Serial In Parallel Out (SIPO) shift register
3. Parallel In Serial Out (PISO) shift register
4. Parallel In Parallel Out (PIPO) shift register
When the data is to be moved serially both at the input or output, the type of shift register used is serial in
serial out (SISO).
If the data is fed serially at the input and is retrieved in parallel manner at the output, the shift register is
known as serial in parallel out (PISO). This action results in serial to parallel conversion.
When data is entered in parallel and taken out in a serial fashion, the shift register is called parallel in
serial out (PISO) register. This shift register is also called parallel to serial converter.
Finally, if both the input and output are in parallel manner, the shift register is termed as parallel in
parallel out PIPO) register.
In all four types, the storage as well as transfer of data takes place only upon the applications of clock
pulses. When the clock is absent, the original data is retained till power is on and shift register acts like a
temporary memory.
5.18 Different ways to transfer/move data

The possible ways of data movements in a shift register are shown in figure 2. Registers are implemented
using flip flops that provide storage capacity. In this case, a 4-bit shift register is used for shift and
storage. The arrow indicates the direction and type of data transfer. Data is entered serially and shifted
right or left. It is also possible to introduce rotate right or left operation using closed loop path. Serial
operation requires at least four clock pulses for 4-bit register to shift the data to left or right. For faster
operation, data can be entered in using parallel shift in operation or parallel shift out in single clock cycle.
5.19 Serial–in serial–out shift register

The serial in serial out (SISO) shift register is a simply collection of clocked flip flops linearly connected.
This register accepts data serially (one bit at a time) and shifts or moves the data serially through various
stages of the registers and exits form last flip flop serially.
Let us consider a 4 bit shift register constructed using four D-flip flop in cascade as shown in figure 4.
External serial data is fed to the first D flip flop and data exits serially from the fourth i.e. last flip flop.
Each flip flop has its outputs connected to the inputs of the next in line. The same clock input goes to all
flip –flops and they are all negative edge triggered.
Let us study the operation of SISO register. The shift register is initially in clear state i.e.(Q A QB QC QD=
0000). Consider data to be entered as 0101. Data must be entered beginning with right most bit first
(LSB). The serial data input ‘1’ is applied to the first FF. When the first clock pulse is applied, the first FF
output becomes QA=1. The register contains now 1000. Now the second bit is applied to the data input.
D=0 for first flip flop and D=1 for the second flip flop. When second clock pulse is applied, at negative
transition, The second FF output QB changes to 1 and QA becomes 0. The register contains now 0100. The
third bit 1 at serial input is allowed to store in the first FF with the third clock pulse. The 0 stored in first
FF is shifted to second flip flop and 1 stored in second flip flop is shifted to third flip flop. The register
output is 1010. With the fourth clock pulse, the last bit 0 is present at serial input and is shifted into first
flip flop and QA becomes 0. Bit stored in first FF is shifted to second FF i.e. 1. The 0 stored in second FF
is shifted to third FF. The LSB =1 stored in third FF is shifted to last FF. The register now contains 0101.
After shift in operation, first (right most) bit of serial data is available at the serial data output. The second
data bit is shifted out at the next clock transition. Similarly third bit is also shifted out and last bit is
available with next clock transition The register is of right shift type and the stored data is shifted out of
the right and lost after eight clock cycles.
Let us summarize the operation. In SISO register, first bit is entered into the register on the first clock
pulse and then shifted from left to right as remaining bits are entered and shifted. In such register, for
serial data one bit at a time is transferred into or out of the register. Therefore, 4 clock pulses are required
to transfer the data into the register and additional 3 clock pulses are required to shift data out of the
register serially.
5.19.1 Serial–in serial–out shift register using JK flip-flop

Operation

5.20. Serial–in parallel–out shift register

For a 4-bit SIPO shift register, there is one data input, 4-outputs and one clock input as shown in figure.
In such register the data is enter serially just similar to SISO shift register. First bit is entered into the
register on the first clock pulse and then shifted from left to right as remaining bits are entered and
shifted. In such register, for serial data one bit at a time is transferred into the register. Therefore, 4 clock
pulses are required to transfer the data into the register.
There is difference in a way the data bits are shifted out of the register. Once the data are stored in the
register, each bit appears on respective output lines of flip flops. As all bits are available simultaneously,
the shift register provides parallel out lines.
5.21 Parallel-in serial-out shift register

This type of shift register accepts data in parallel form and outputs it in serial form. With a single clock
pulse, data bits are entered simultaneously into the respective flip flop stages of the shift register and
output is available bit by bit from last storage. For PISO register, it is necessary to shift the data after
loading it in parallel. But unfortunately, the two acts - parallel loading and shifting serially cannot occur
simultaneously.
This register consists of 4 D flip flops. All flip flops are triggered simultaneously by a common clock.
There are four parallel data inputs ABCD applied to the register. Parallel data bits and outputs of previous
stage are given as inputs to two AND gates. Other input comes from direct control and inverted control as
shown here. Outputs of the two AND gates act as inputs for the OR gate whose output is fed as input to
the next stage of shift register as shown in figure 7.
Let us consider parallel data ABCD=0101. When the control line LOW, second AND gate is enabled and
first AND is disabled. So parallel data bit appears as data input.
Application of one clock pulse now allows this parallel data to be stored into the 4-bit register. Advantage
of this configuration is that any number of bits are transferred into the register in a single clock pulse.
With one clock pulse the parallel data available at D input appears at the output of register.
On the other hand, when control line is HIGH, first AND gate is enabled i.e. the Q output of previous FF
appears as data input to the next stage. Here, four clock pulses are required to shift the data out of the
register serially. The output of last FF Q3 acts as a serial data output of the shift register.
5.22 Parallel–in parallel–out shift register
In the 4 bit parallel in parallel out shift register, four independent D flip are used as shown in figure. The
D inputs are acting as the parallel inputs and Q outputs of the FFs act as the parallel outputs of the shift
register. Let us consider the parallel data ABCD = 0101.

The clock inputs of all FFs are triggered by a single clock signal. Once the register is clocked, all the data
at the D inputs appear at corresponding Q outputs of the FFs simultaneously. This shift register requires
only one clock pulse for operation; hence it is the fastest shift register.
5.23 Bidirectional shift register
It is the shift register in which the data can be shifted either left or right. The four bit bidirectional shift
register using D flip flops is shown in figure 9. There are two AND gates and a OR gate used at the input
of each D flip flop. This combinational circuit allows the serial data to be shifted left or right based on the
Left/Right shift control pin.
Let us consider a binary data 1101 applied to the serial data in for left shift. The M input is set to 0. With
this control input, the inverter produces 1 at the output which enables the second AND gates of the
combinational circuit. This allows data present at second AND gate to pass through OR gate to D inputs
of the FFs. The D input of FFD receives the serial data; D input of FFC receives QD output; D input of FFB
receives QC output and D input of FFA receives QB output.
Application of a clock pulse shifts the data to the left by 1 bit position. After four clock pulses, the output
of left shift register contains the data 1101. It further requires 3 clock pulses to shift the data out serially
from Q0 of the left shift register.
Let us consider a binary data 0101 applied to the serial data in for right shift. The M input is set to 1. With
this control input, the first AND gates of the combinational circuit is enabled. This allows data present at
first AND gate to pass through OR gate to D inputs of the FFs. The D input of FFA receives the serial data
input; D input of FFB receives QA output; D input of FFC receives QB output and D input of FFD receives
QC output.
Application of a clock pulse shifts the data to the right by 1 bit position. After four clock pulses, the
output of right shift register contains the data 0101. It further requires 3 clock pulses to shift the data out
serially from QD of the right shift register.
5.24 Universal shift register
A universal shift register can transfer data in three different modes. It can load and transmit data in
parallel. It can load and transmit data in serial fashion, through left shifts or right shift. This allows user to
activate either SISO, SIPO, PISO and PIPO shift register. 4bit Universal shift register consist of 4 positive
or negative edge triggered D flip flops.
Serial in or serial out can be implemented by shifting the data in any one of the two directions. Left shift
requires QA ← QB ← QC ← QD ← serial Data in whereas the right shift requires Serial data in → QA
→ QB → QC → QD.
For SISO, the shift in operation needs shift/load input connected to HIGH state and will take 4 clock
pulses to shift the data serially in. The shift out operation also need shift/load input kept connected to
HIGH state and will require 3 clock pulses shift data serially out. This is because the output already has
LSB before shift out operation begins. For SIPO, the Shift/load operation is connected at HIGH state and
will require no clock pulse to take the data is already available at the outputs.
For PISO operation, shift/load input be connected to LOW state to enable parallel load operation. For
shift out operation, the shift/load input must be connected to HIGH state for shift serial OUT and will
require 3 pulses again. For PIPO operation, shift/load input be connected to LOW state to enable parallel
load operation and requires only 1 clock pulse to load the data in parallel and no clock pulse to take the
data at output since it is always available at the output.
For shift left operation, parallel data input (Dn) receives Qn+1 output, hence shift/load be connected to
low state for both modes.
5.25 Ring counter
Ring counter is a type of shift register with the output of the last flip flop is fed back to the input of the
first flip flop. The data stored within the shift register will circulate as long as clock pulses are applied.
The 4-bit ring counter consists of four D flip flops with clock input connected to the common clock.
External RESET input is connected to Preset input of the first FF and Clear input of all remaining flip
flops as shown in figure.
Let us understand the working of ring counter with the help of function table. Initially, an active LOW
level is applied to Reset input, which sets QA as 1 and other flip flop outputs will be 0. The contents of
the register are QAQBQCQD =1000 as shown in figure.

Application of first clock pulse shifts the logic 1 to QB as D input of second FF is connected to QA. The
register now contains 0100. Application of second clock pulse shifts the logic 1 to Q C as D input of third
FF is connected to QB. The register now contains 0010. Further application of third clock pulse shifts the
logic 1 to QD as D input of fourth FF connected to QC. The register now contains 0001. Forth clock pulse
shifts the logic 1 to QA as D input of fourth FF connected to QD. The register now contains 1000 again
and ring counter operation continues further.
5.26 Johnson counter
A Johnson counter is a modified ring counter in which the complemented output of the last flip flop is
connected to the input of the first flip flop. Johnson counter is also called as twisted ring counter.
Let us consider a 4-bit Johnson counter constructed using 4-D flip flops as shown in figure. The circular
connection is made from complement output of the rightmost flip flop to the input of the leftmost D flip
flop. The register shifts its contents one bit position to the right with every clock pulse and the
complement value of last flip flop is transferred to the first flip flop at the same time.
Let us understand the working of Johnson counter. Initially, an active LOW level is applied to the clear
input, which resets all the flip flops. Thus the register contains QAQBQCQD =0000. With the first clock
pulse, the first flip flop inserts 1 into the register as 𝑄̅̅𝐷̅ =1. The content of the counter are 1000. With the
second clock pulse, new ‘1’ is added into the register as 𝑄̅𝐷̅ ̅ =1. The content of the counter is now 1100.
Next clock pulse generates the counter contents as 1110. Fourth clock pulse shifts the whole contents to
right and adds 1 to the left position. Thus we get 1111.
As QD=1, the complement of QD is 0. Now the value ‘0’ is inserted into the register. Thus, with the next
clock pulse, the counter contains 0111. Next counter becomes 0011 with next clock pulse. Further it
becomes 0001 with the clock pulse. Finally the counter becomes 0000 with the clock pulse.
Starting from the clear state, the Johnson counter goes through a sequence of 8 states. In general, a n-bit
twisted ring Johnson counter will go through a sequence of 2×n states. The disadvantage of Johnson
counter is that it does not count in binary sequence.
5.27 Applications of shift registers
Shift register are used in variety of applications as listed below.
1. Delay line- The SISO register can be used to introduce time delay. The delay is proportional to
number of flip flops.
2. Serial to parallel converter- Serial in parallel out (SIPO) shift register can be used to convert data
in serial form to parallel form e.g. keyboard interfacing.
3. Parallel to serial converter- A parallel in serial out ( PISO ) shift register can be used to convert
data in parallel form to serial form. This is required in a situation where parallel data transmission
is not feasible at long distance e.g. modem/router interfacing.
4. Sequence generator- sequence to operate various electronic gadgets can be obtained using shift
register
5. Ring counter - a particular set of control signals can be generated using ring counter.
1. Shift register is also used in
6. Pulse train generator
7. Registers in processors
8. Keyboard encoding
9. Rolling display
10. Universal asynchronous receiver transmitter (UART)
5.28 Exercise

A. Choose the correct alternative from the following

1. The clock signal in a sequential circuit is used for:
a) Storing data in memory elements
b) Generating arithmetic operations
c) Providing power to the circuit
d) Reading data from memory elements
2. A counter is a sequential circuit that can:
a) Perform arithmetic operations
b) Store data indefinitely
c) Generate clock signals
d) Count pulses or events
3. The modulus of a counter determines:
a) The clock frequency
b) The maximum count value before resetting
c) The number of input signals
d) The number of flip-flops used
4. A synchronous counter:
a) Uses ripple carry logic
b) Has a delay in updating outputs
c) Counts independently of clock pulses
d) Updates outputs simultaneously
5. Which of the following is true for a ring counter?
a) All flip-flops toggle simultaneously
b) Only one flip-flop toggles at a time
c) The counter counts up and down
d) It uses asynchronous logic
6. A decade counter counts from:
a) 0 to 9
b) 0 to 10
c) 1 to 10
d) 1 to 9
7. In a Johnson counter, the outputs are fed back to:
a) The inputs
b) The clock signal
c) The reset input
d) The AND gates
8. A counter that counts both upward and downward is called a:
a) BCD counter
b) Up/down counter
c) Ring counter
d) Synchronous counter
9. Which flip-flop type is commonly used to design synchronous counters?
a) SR flip-flop
b) D flip-flop
c) JK flip-flop
d) T flip-flop
10. Which type of flip-flop is also known as a "Data or Delay" flip-flop?
a) D flip-flop
b) SR flip-flop
c) JK flip-flop
d) T flip-flop
B. Short Answer Type Questions
11. Discuss the differences between an up-counter and a down-counter.
12. Compare and contrast the functionality of a positive-edge-triggered D flip-flop and a negative-edge-
triggered D flip-flop
13. Design T flip-flop using J-K flip- flop.
14. Design T flip-flop using D flip- flop.
15. Design T flip-flop using S-R flip- flop.
16. Design J-K flip-flop using T flip- flop.
17. Design S-R flip-flop using T flip- flop.
18. Design D flip-flop using T flip- flop.
19. Design MOD 5 asynchronous counter using J-K flip flop
20. Design MOD 9 asynchronous counter using J-K flip flop
C. Long Answer Type Questions
21. Design MOD 14 asynchronous counter using J-K flip flop
22. Design MOD 14 synchronous counter using J-K flip flop
23. Design MOD 10 asynchronous counter using J-K flip flop
24. Design MOD 3 asynchronous counter using J-K flip flop
25. Design MOD 9 synchronous counter using J-K flip flop