Study Material

DIGITAL SYSTEM DESIGN (PCC-ECR302)

MODULE III
LOGIC GATES AND LOGIC FAMILIES

Table of Contents

Content Page No

3.1 Introduction 3.3

3.2 OR Gate 3.3
3.3 AND gate 3.4
3.4 NOT gate 3.5
3.5 NAND gate 3.6
3.6 NOR gate 3.7
3.7 NAND gate as universal gate 3.8
3.8 NOR gate as universal gate 3.9
3.9 XOR (Exclusive OR) gate 3.10
3.9.1 Implementation of Ex-OR gate by using basic gates only 3.11
3.9.2 Implementation of Ex-OR gate by using NAND gates only 3.11
3.9.3 Implementation of Ex-OR gate using NOR gates only 3.12
3.10 XNOR gate 3.13
3.10.1 Implementation of Ex-NOR gate by using basic gates only 3.14
3.10.2 Implementation of Ex-NOR gate by using NAND gates only 3.14
3.11 Logic Families 3.15
3.12 Classification of IC chips 3.15
3.13 Types of logic families 3.16
3.14 Characteristics of logic families 3.18
3.15 Basic features of logic families 3.19
3.16 Comparison of logic families 3.20
3.17 Exercise 3.21
3.1 Introduction
Logic gates are the basic components in digital electronics. These gates are used to create digital circuits
right from simple to complex logic circuit and even complex integrated circuits. Complex microprocessor
or microcontroller ICs are constructed using many logic gates. Logic gates are the fundamental building
blocks of all digital systems. It has one or more inputs and one output with some logical relationship
between them. Logic gate accepts binary signals i.e. True or False, ON or OFF, 1 or 0 and have an ability
to make decisions. The state of the output is decided by the input states. All logic gates implements some
Boolean function which correlates output with input through some logical operation. Logic gates are mainly
designed with the electronic switches using diodes and transistors.
There are three basic gates – AND, OR and NOT. NAND and NOR gates are derived gates are also known
as universal logic gates. An XOR gate is inequality detector gate and can be used in comparator, adders,
parity generators etc. The symbols of logic gates are of two types – Distinctive shapes & rectangular shapes.

3.2 OR Gate:
An OR gate is a logic circuit with two or more inputs and one output. The OR gate performs logical addition
i.e. OR function. Fig. 3 shows the logic symbol and truth table of two input OR gate along with simple
implementation using switches.
The output of an OR gate is HIGH only when all of its inputs are in the HIGH state. In all other cases, the
output is LOW. For OR gate, Y = A + B
3.3 AND gate:
AND gate is a logic circuit having two or more inputs and one output. The AND gate performs logical
multiplication i.e. AND function. Fig.2 indicates the logic symbol and truth table of two input AND gate
along with simple implementation using switches.
The output of an AND gate is HIGH only when all of its inputs are in the HIGH state. In all other cases, the
output is LOW. For AND gate, Y = A.B
The logical operation of AND gate can be expressed with the help of a table which includes all input
combinations and corresponding outputs. Such table of input / output relations is known as truth table. In
this case, there are 2 inputs to AND gates to provide 22 = 4 input combinations in the truth table. The truth
table may be extended to any number of inputs. For 3 inputs, there are 8 combinations and 16 for 4 inputs.
3.4 NOT gate:
NOT gate has one-input and one-output. It is a logic circuit whose output is always the complement of the
input. Fig. 1 indicates the logic symbol and truth table of NOT gate along with simple implementation using
switches. The NOT gate is popularly known as inverter. It performs logical inversion or complementation.
That is, if A is the input to a NOT circuit, then its output Y is given by Y = ıı or A’. That is, a LOW input
produces a HIGH output and vice versa.
3.5 NAND gate
NAND gate is combination of AND and NOT gates. The NAND gate provides AND functions with inverted
output. Fig.4 indicates the logic symbol and truth table of two input NAND gate along with simple
implementation using switches.
The output of a NAND gate is logic ‘0’ when all its inputs are a logic ‘1’. For all other input combinations,
the output is logic ‘1’.

Symbol and truth table are as follows:

3.6 NOR gate
NOR gate is combination of OR and NOT gates. The NOR gate provides OR function with inverted output.
Fig. 5 shows the logic symbol and truth table of two input NOR gate along with simple implementation
using switches.
The output of a NOR gate is a logic ‘1’ when all its inputs are logic ‘0’. For all other input combinations,
the output is logic ‘0’.

Symbol and truth table of NOR gate are as follows:

3.7 NAND gate as universal gate:
A universal gate is a gate that can be used to implement any other gate in digital logic circuits. The NAND
(NOT-AND) gate is considered a universal gate because it has the capability to implement all the basic
logic functions, including AND, OR, NOT, and even combinations of these functions. Here's why the
NAND gate is considered universal:
Action of NAND gate as NOT gate: When both inputs of a NAND gate are the same (either 0 or 1), the
output is the complement of that input. This behavior is the same as a NOT gate.

Action of NAND gate as AND gate: By connecting multiple NAND gates in series, the output of one
NAND gate can be fed as input to another NAND gate. This arrangement effectively implements the AND
function.

Action of NAND gate as OR gate: By connecting multiple NAND gates in parallel and then applying a
NOT operation to the output of the parallel arrangement, you can achieve the OR function. This is known
as De Morgan's theorem, which states that the complement of a NAND operation is equivalent to an OR
operation.
3.8 NOR gate as universal gate:
A universal gate is a gate that can be used to implement any other gate in digital logic circuits. The NOR
(NOT-OR) gate is considered a universal gate because, like the NAND gate, it has the capability to
implement all the basic logic functions, including AND, OR, NOT, and even combinations of these
functions.
Action of NOR gate as NOT gate: When both inputs of a NOR gate are the same (either 0 or 1), the output
is the complement of that input. This behavior is the same as a NOT gate.

Action of NOR gate as OR gate: By connecting multiple NOR gates in parallel, the output of one NOR
gate can be fed as input to another NOR gate. This arrangement effectively implements the AND function.
Action of NOR gate as AND gate: By connecting multiple NOR gates in series and then applying a NOT
operation to the output of the series arrangement, you can achieve the OR function. This is also based on
De Morgan's theorem, similar to the NOR gate's implementation of the AND function.

3.9 XOR (Exclusive OR) gate

Exclusive OR gate is basically designed to exclude the condition of standard OR gate so as to generate real
binary addition. An XOR gate is a two inputs and one output logic circuit. Fig.6 indicates the logic symbol
and truth table of two input XOR gate along with simple implementation using switches.
The output of an XOR gate is at logic ‘1’ when the inputs are dissimilar and at logic ‘0’ when the inputs are
similar.
3.9.1 Implementation of Ex-OR gate by using basic gates only

3.9.2 Implementation of Ex-OR gate by using NAND gates only

The output of XOR gate can be also written as

Y  AB  AB
 AA  AB  AB BB
 A(A  B)  B(A  B)

 
 (A  B) A  B

 (A  B)AB
[By Demorgan’s theorem]

   
 A AB  B AB

   
 A AB  B AB

  .BAB
 A AB



3.9.3 Implementation of Ex-OR gate using NOR gates only

Y  AB  AB
 AA  AB  AB BB
 A(A  B)  B(A  B)

 
 (A  B) A  B

 (A  B)AB
[By Demorgan’s theorem]


 (A  B) A  B 

Name of the Faculty: ARIGHNA BASAK

Designation and Department: Assistant Professor; Department OF ECE
Brainware University, Kolkata 3. 12
  

 A  A  B  B(A  B)

 A  A  B  B(A  B)  A  (A  B)  B  (A  B)

 A  (A  B)  B (A  B)  A  (A  B)  B  (A  B)

3.10 XNOR gate

XNOR is obtained by the combination of NOT and XOR gates. XNOR gate is a two inputs and one output
XOR gate with active low output. Fig.7 indicates the logic symbol and truth table of two input XNOR gate
along with simple implementation using switches.
The output of an XNOR gate is at logic ‘1’ when the inputs are similar and at logic ‘0’ when the inputs are
dissimilar
3.10.1 Implementation of Ex-NOR gate by using basic gates only

3.10.2 Implementation of Ex-NOR gate by using NAND gates only

3.11 Logic Families
Logic families refer to groups of digital electronic circuits or gates that share similar characteristics in terms
of their operation, voltage levels, power consumption, speed, noise immunity, and other performance
metrics. Different logic families have evolved over time to meet various design requirements and
technological advancements. Here are some common logic families:
TTL (Transistor-Transistor Logic): TTL logic uses bipolar transistors and resistors to implement logic gates.
It operates on low voltage levels, typically 5V, and is known for its high speed and low power consumption.
However, it's more susceptible to noise.
CMOS (Complementary Metal-Oxide-Semiconductor): CMOS logic uses both NMOS and PMOS
transistors to create logic gates. It operates on a wider range of supply voltages (typically 3V to 15V) and
is known for its low power consumption, making it popular for portable devices. CMOS offers better noise
immunity compared to TTL.
ECL (Emitter-Coupled Logic): ECL logic uses a differential amplifier configuration for high-speed
operation and is commonly used in high-frequency applications. It operates with multiple power supply
levels and is known for its very fast switching speeds.
RTL (Resistor-Transistor Logic): RTL logic uses transistors and resistors to create logic gates. It was one
of the earliest logic families but has been largely replaced by TTL, CMOS, and other families due to
limitations in speed and noise immunity.
DTL (Diode-Transistor Logic): DTL logic uses diodes and transistors to construct gates. It was used before
the development of TTL and CMOS logic families but has become obsolete due to its limitations in terms
of speed and power consumption.
Each logic family has its own advantages and disadvantages, and the choice of which family to use depends
on the specific requirements of the application, such as speed, power consumption, noise immunity, and
cost. As technology advances, new logic families continue to emerge, catering to various needs in digital
circuit design.
3.12 Classification of IC chips
Depending on the package density, the number of devices in an IC chip can be classified as follows
1. Small scale integration (SSI) < 10 logic gates

2. Medium scale integration (MSI) ~ 10 - 100 logic gates

3. Large scale integration (LSI) > 100 logic gates

4. Very large scale integration (VLSI) ~ thousands of logic gates

(104 − 109 components in a single chip)

5. Ultra large scale integration (ULSI) ~ more than 109 components in

a single chip
3.13 Types of logic families
As explained in previous section, logic families are the logic circuits having identical electrical parameters.
It is a group of compatible ICs with the same logic levels and supply voltages for performing various logic
functions. They are fabricated using a specific circuit configuration which is referred to as a Logic family.
The circuit design of the basic gate of each logic family is the same.
The logic family is designed by considering the basic electronic components such as resistors, diodes,
transistors, and MOSFET; or combinations of any of these components. Accordingly, logic families are
classified as per the construction of the basic logic circuits. Many different logic families of digital ICs have
been introduced commercially are listed in table.

Logic families are classified according to the principle type of electronic components used in their circuitry
as shown in Figure. They are
a. Bipolar ICs which uses diodes and transistors (BJT)
b. Unipolar ICs which uses MOSFETs

Out of the logic families mentioned above, DL, RTL and DTL are not very useful due to some inherent
disadvantages while TTL, ECL and CMOS are widely used in many digital circuit design applications.
Each logic family is further classified based on the significant variation in the key parameters.
This helps in improving the performance of that logic family. For example, TTL logic family has
subfamilies such as low power TTL, Schottky TTL etc.
TTL has an extensive list of digital functions and is currently the most popular logic family. ECL is used in
systems requiring high-speed operations. MOS is used in circuits requiring a high component density,
whereas CMOS is used in systems requiring low power consumption.
These three families, TTL, ECL and CMOS have LSI devices and also a large number of MSI and SSI
devices. SSI devices are those that come with a small number of gates or flip flops in one IC package. The
limit on the number of circuits in SSI devices is number of pins in a package. A 14 pin package can
accommodate only four two input gates because, each gate requires three external pins-two each for inputs
and one each for output, for a total of 12 pins.
The remaining two pins are needed for supplying power to the circuits. TTL ICs are usually distinguished
by numerical designations such as the 5400 and 7400 series.
The former has wide operating temperature range and is suitable for military use and the latter has a
narrower temperature range and is suitable for industrial use only. TTL SSI ICs such as 7404, 7400 etc are
available in the market.
3.14 Characteristics of logic families
Propagation delay tp:
The propagation delay is the time delay between the occurrence of change in the logical level at the input
and before it is reflected at the output. It is the time delay between the specified voltage points on the input
and output waveforms. Propagation delays are separately defined for LOW-to-HIGH and HIGH-to-LOW
transitions at the output. In addition, we also define enable and disable time delays that occur during
transition between the high-impedance state and defined logic LOW or HIGH states.

Propagation delay tpLH: This is the time delay between the specified voltage points on the input and output
waveforms with the output changing from LOW to HIGH.
Propagation delay tpHL: This is the time delay between the specified voltage points on the input and output
waveforms with the output changing from HIGH to LOW. It is the average transition delay time for a signal
to propagate from input to output when the binary signals change in value. The signal through gate takes a
certain amount of time to propagate from the inputs to the output. The interval of time is defined as the
propagation delay of the gate. Propagation delay is expressed in nanoseconds (ns) (1ns = 10 -9 s). The signals
travelling from input to output of the system pass through a number of gates. The propagation delay of the
system is the sum of the propagation delays of all these gates. When the speed of operation is important,
each gate must have a small propagation delay and the digital circuit must have minimum number of gates
between input and output.
Power dissipation: The power dissipation parameter for a logic family is specified in terms of power
consumption per gate and is the product of supply voltage VCC and supply current ICC. The supply current
is taken as the average of the HIGH- level supply current ICCH and the LOW- level supply current ICCL.
Fan in: Fan in of a gate is the number of inputs connected to the gate without any degradation in the voltage
level.

Fan out: Fan out is the maximum number of logic gates that a gate can drive without any degradation in
the voltage level.

Noise Margin

Noise margin is the maximum noise voltage added to the input signal of digital circuit that does not cause
an undesirable change in the circuit output.

DC noise: It is caused by a drift in the voltage levels of a signal

AC noise: It is caused by random pulse that may be created by other switching signals.

Rise time, tr: This is the time that elapses between 10% and 90 % of the final signal level when the signal
makes a transition from logic LOW to logic HIGH.

3.15 Basic features of logic families

RTL

 The propagation delay of RTL is 500 ns. Therefore speed of operation is low
 A fan-out is 4 or 5 with switching delay of 50 ns
 It has a fan in of 4
 Poor noise immunity
 High power dissipation

DTL

 The propagation delay of DTL is 25 ns

 A fan-out as high as 8 is possible with DTL family
 It has a fan in of 8
 The noise margin is high

TTL

 The propagation delay of TTL is 10 ns

 A fan-out as high as 10 is possible with TTL family
 Power dissipation is about 10 mW
 The noise margin is 0.4 V
ECL

 The propagation delay of ECL is 1 ns

 A fan-out as very high as 25 is possible with ECL family
 Power dissipation is about 40 mW
 The noise margin is low and about 250 mV

MOS logic

 Operating speed is slower

 A fan-out is as high as 50
 Low power dissipation
 Good noise margin

CMOS family

 The propagation delay is 25 – 100 ns.

 A fan-out is very high as 50
 Low power consumption
 Greater packing density

3.16 Comparison of logic families

3.17 Exercise

A. Choose the correct alternative from the following

1. Which logic gate's output is 1 only when all its inputs are 1?
a) AND
b) OR
c) NOT
d) XOR
2. The output of an OR gate is 0 when:
a) All inputs are 1
b) All inputs are 0
c) At least one input is 0
d) At least one input is 1
3. A NOT gate can also be called:
a) Inverter
b) Complementer
c) Reverser
d) Negator
4. The output of a NAND gate is inverted when:
a) All inputs are 1
b) All inputs are 0
c) At least one input is 0
d) At least one input is 1
5. Which logic gate's output is 0 only when all its inputs are 0?
a) AND
b) OR
c) NOT
d) XOR
6. What is the output of an XOR gate when both inputs are the same?
a) 0
b) 1
c) Depends on other inputs
d) Not defined
7. Which logic family offers high noise immunity and is commonly used in portable devices?
a) TTL
b) CMOS
c) ECL
d) BiCMOS
8. Emitter-Coupled Logic (ECL) is known for:
a) Low power consumption
b) High noise immunity
c) Low manufacturing cost
d) Compatibility with CMOS
9. Which logic family is known for its high-speed operation and is used in high-frequency applications?
a) TTL
b) CMOS
c) ECL
d) BiCMOS
10. Which logic family is known for its low power consumption and compatibility with portable devices?
a) TTL
b) CMOS
c) ECL
d) BiCMOS
B. Short Answer Type Questions
11. Explain the fundamental operation of AND gate. Provide truth tables and circuit symbols for this gate.
12. Explain the fundamental operation of OR gate. Provide truth tables and circuit symbols for this gate.
13. Explain the fundamental operation of NOT gate. Provide truth tables and circuit symbols for this gate.
14. Explain the fundamental operation of NAND gate. Provide truth tables and circuit symbols for this gate.
15. Explain the fundamental operation of NOR gate. Provide truth tables and circuit symbols for this gate.
16. Explain the fundamental operation of EX-OR gate. Provide truth tables and circuit symbols for this
gate.
17. Explain the fundamental operation of EX-NOR gate. Provide truth tables and circuit symbols for this
gate.
18. Discuss the operation of the NAND gate and explain why it's considered a universal gate.
19. Explain why EX-OR gate is considered as exclusive gate.
20. Explain why EX-NOR gate is considered as exclusive gate.
C. Long Answer Type Questions
21. Compare and contrast the TTL (Transistor-Transistor Logic) and CMOS (Complementary Metal-Oxide-
Semiconductor) logic families in terms of voltage levels, power consumption, noise immunity, and speed.
22. Describe the basic operation of the ECL (Emitter-Coupled Logic) family. What advantages does it offer
in terms of speed and performance?
23. Discuss the power consumption characteristics of CMOS logic compared to other logic families. How
is CMOS well-suited for battery-powered devices?
24. Describe the significance of power supply voltage in logic families. How does it influence the overall
performance and operation of logic gates?
25. Discuss the role of noise in digital circuits. How can logic families with better noise immunity enhance
circuit reliability?