Study Material

DIGITAL SYSTEM DESIGN (PCC-ECR302)

MODULE IV
COMBINATIONAL CIRCUITS
Table of Contents

Content Page No

4.1 Half Adder 4.3

4.1.1 Block diagram, Truth table and Circuit Diagram of Half Adder 4.3
4.1.2 Implementation of half adder using NAND gates only 4.3
4.1.3 Implementation of half adder using NOR gates only 4.4
4.2 Full Adder 4.4
4.2.1 Block diagram, Truth table and Circuit Diagram of Full Adder 4.4
4.2.2 Implementation of full adder using two half adder 4.6
4.2.3 Implementation of full adder using NAND gates only 4.7
4.3 Half Subtractor 4.8
4.3.1 Block diagram, Truth table and Circuit Diagram of Half Subtractor 4.8
4.3.2 Implementation of half subtractor using NAND gates only 4.9
4.4 Full Subtractor 4.9
4.4.1 Block diagram, Truth table and Circuit Diagram of Full Subtractor 4.9
4.4.2 Implementation of full subtractor using two half subtractor 4.11
4.5 Multiplexer 4.12
4.5.1 2:1 Multiplexer 4.13
4.5.2 4:1 Multiplexer 4.14
4.6. Examples of Multiplexer 4.15
4.7 Applications of multiplexers 4.19
4.8 Demultiplexer 4.19
4.8.1 1:2 Demultiplexer 4.20
4.8.2 1:4 Demultiplexer 4.21
4.8.3 Applications of Demultiplexers 4.22
4.9 Encoder 4.24
4.9.1 Octal to binary encoder 4.24
4.9.2 Decimal to BCD encoder 4.26
4.10 Decoder 4.28
4.10.1 2 to 4 line decoder 4.28
4.10.2 3 to 8 (Binary to Octal) decoder 4.30
4.10.3 Examples of Decoder 4.32
4.11 Parity Generator 4.34
4.12 Magnitude Comparator 4.35
4.12.1 1-bit magnitude comparator 4.36
 4.12.2 2-bit magnitude comparator 4.37
4.13 Code conversion 4.40
4.13.1 BCD – Excess 3 code conversion 4.40
4.13.2 Binary to Gray Code Converters 4.43
4.14 Additional Example 4.45
4.15 Exercise 4.47
4.1 Half Adder
4.1.1 Block diagram, Truth table and Circuit Diagram of Half Adder
A half adder is a combinational logic circuit used to perform the addition of two single-bit binary
numbers. It has two inputs (A and B) representing the two bits to be added and two outputs (Sum and
Carry) representing the result of the addition.
The truth table and block diagram for a half adder is as follows:

From the truth table, the logic expressions for the outputs are as follows:

4.1.2 Implementation of half adder using NAND gates only

4.1.3 Implementation of half adder using NOR gates only

4.2 Full Adder

4.2.1 Block diagram, Truth table and Circuit Diagram of Full Adder
A full adder is a combinational logic circuit used to perform the addition of three single-bit binary
numbers. It takes in three inputs (A, B, and Carry-In) representing the two bits to be added (A and B) and
the carry generated from the previous stage (Carry-In). The full adder produces two outputs: the Sum and
the Carry-Out.
The block diagram and truth table for a full adder are as follows:
From the truth table through K-Map the logic expressions for the outputs are as follows:
The full adder circuit can be implemented using basic logic gates such as XOR, AND, and OR gates.
Here's the logic diagram of a full adder:

4.2.2 Implementation of full adder using two half adder

A full adder can be implemented using two half adders and an OR gate. This approach breaks down the
addition of three bits (A, B, and Carry-In) into two stages.

Here's the logic diagram for implementing a full adder using two half adders:

Where HA1 and HA2 represent two half adders, Ai and Bi represent inputs of half adder, Ci-1 represents
carry-in, SH represents sum of HA1, CH represents temporary carry provided by HA1, Si represents final
sum and Ci represents carry-out.

The logic expressions for the Sum and Carry-Out can be derived as follows:
4.2.3 Implementation of full adder using NAND gates only

The circuit diagram of full adder using NAND gates is as follows:

4.3 Half Subtractor
4.3.1 Block diagram, Truth table and Circuit Diagram of Half Subtractor
A half subtractor is a combinational logic circuit used to perform subtraction of two single-bit binary
numbers. It has two inputs (A and B) representing the minuend (the number from which subtraction is
performed) and the subtrahend (the number to be subtracted). It produces two outputs (Difference and
Borrow) representing the result of the subtraction.

The block diagram and truth table for a half subtractor are as follows:

From the truth table the logic expressions for the outputs are as follows:

D  AB  AB  A  B
Bout  AB
The half subtractor circuit can be implemented using basic logic gates such as XOR and AND gates.
Here's the logic diagram of a half subtractor:
4.3.2 Implementation of half subtractor using NAND gates only

4.4 Full Subtractor

4.4.1 Block diagram, Truth table and Circuit Diagram of Full Subtractor
A full subtractor is a combinational logic circuit used to perform subtraction of three single-bit binary
numbers. It takes in three inputs (A, B, and Borrow-In) representing the minuend (the number from which
subtraction is performed), the subtrahend (the number to be subtracted), and the borrow-in from the
previous stage. The full subtractor produces two outputs: the Difference and the Borrow-Out.
The block diagram and truth table for a half subtractor are as follows:
From the truth table through K-Map the logic expressions for the outputs are as follows:

The full subtractor circuit can be implemented using basic logic gates such as XOR, AND, and OR gates.
Here's the logic diagram of a full subtractor:
4.4.2 Implementation of full subtractor using two half subtractor

A full subtractor can be implemented using two half subtractor and an OR gate. This approach breaks
down the subtraction of three bits (X, Y, and Borrow-In) into two stages.

Here's the logic diagram for implementing a full subtractor using two half adders:

Where HS1 and HS2 represent two half subtractor, X and Y represent inputs of half subtractor, B in
represents borrow-in, DH represents difference result of HS1, BoutH represents temporary borrow provided
by HS1, D represents final difference result and B out represents borrow-out.

The logic expressions for the difference and borrow-out can be derived as follows:
4.5 Multiplexer
A multiplexer (MUX) is a digital logic component that is used to select one of many input signals and
route it to a single output line. It is a data selector that operates based on the control inputs to choose the
desired input to pass through to the output.

A multiplexer has the following key components:

 Data inputs (I0, I1, ..., In-1): These are the n data inputs that carry the signals to be selected.
 Control inputs (S0, S1, ..., Sm-1): These are the m control inputs that determine which input signal
gets selected. The number of control inputs (m) determines the number of data inputs that can be
selected (2^m).
 Output (Y): The selected data input is routed to the output line (Y).
Multiplexer are also called as DATA Selector or router because it accepts several data inputs and allows
only one of them to get through to the output at a time. The basic multiplexer has n input lines and single
output line. It also has m – select or control lines. The relation between number of select lines and number
of data inputs are
2m = n
As multiplexer selects one out of many, it is often called as 2m to 1 line converter.
4.5.1 2:1 Multiplexer
A 2:1 multiplexer (2-to-1 multiplexer) is a simple digital logic circuit that selects one of two input signals
and forwards it to the output based on the control input. It has two data inputs (I0 and I1), one control
input (S0), and one output (Y). The block diagram, truth table and logical expression are as follows:

In this multiplexer, I0 and I1 are the data inputs, S0 is the select line and Y is the output of the multiplexer.
In a function table, select line S0 is shown as the input and Y is the output. When S0 = 0 then the
multiplexer selects the data I0 which appears at output Y and when S0=1, the multiplexer selects the data
I1 which receives at output Y.
The 2:1 multiplexer can be implemented using logic gates such as AND, OR, and NOT gates. Here's the
logic diagram of a 2:1 multiplexer:
4.5.2 4:1 Multiplexer
A 4:1 multiplexer (4-to-1 multiplexer) is a digital logic circuit that selects one of four input signals and
forwards it to the output based on two control inputs. It has four data inputs (I0, I1, I2, and I3), two control
inputs (S1 and S0), and one output (Y). The block diagram, truth table and logical expression are as
follows:

The logic symbol indicates that there are 4 data inputs namely I0, I1, I2, I3 and single output (Y). For 4
data, inputs there are two select lines namely S0 and S1. While preparing the function table we write S 1 as
MSB and S0 as LSB. The 2 select inputs provide 4 input combinations for selecting the proper data input
at the output Y.
The output Y receives I0 only when S1=0 and S0=0. Similarly, output Y receives I1 only when S1S0=01.
Output Y receives I2 only when S1S0=10. Output Y receives I3 only when S1S0=11. The 4:1 multiplexer
can be implemented using logic gates such as AND, OR, and NOT gates. Here's the logic diagram of a
4:1 multiplexer:
4.6. Examples of Multiplexer
Example 4.1 Design 4:1 multiplexer using 2:1 MUX
A 2:1 multiplexer selects one of two inputs based on the control input. By cascading two 2:1 multiplexer
together, a 4:1 multiplexer is created. Here's the logic diagram for a 4:1 multiplexer using two 2:1
multiplexer:

Example 4.2 Design 8:1 multiplexer using 4:1 multiplexer and OR gate
A 4:1 multiplexer selects one of four inputs based on the control input. By cascading two 4:1 multiplexer
together, a 8:1 multiplexer is created. Here's the logic diagram for a 8:1 multiplexer using two 4:1
multiplexer:
Alternatively, by cascading two 4:1 multiplexer and one 2:1 multiplexer together, a 8:1 multiplexer is
created. Here's the logic diagram for a 8:1 multiplexer using two 4:1 multiplexer and one 2:1 multiplexer
is as follows

Example 4.3 Design 16:1 multiplexer using 4:1 MUX

16:1 multiplexer is designed by using 4:1 MUX is as follows:
Example 4.4 Full adder using 8:1 multiplexer
Designing a full adder using an 8:1 multiplexer (MUX) is an interesting approach that allows to use the
MUX to select the appropriate output based on the binary inputs and carry-in. A full adder takes three
inputs: A (bit A), B (bit B), and Carry-In (Cin), and produces two outputs: Sum (S) and Carry-Out (C out).
Truth table for a Full Adder:

Set inputs A and B as the data inputs (I0 and I1) to the MUX.
Set the Carry-In (Cin) as the 3rd bit (S2) of the select inputs of the MUX.
Connect the 4th and 5th select inputs (S1 and S0) of the MUX to ground (0) to select I0 as the default
output.
Example 4.5 Full subtractor using 4:1 multiplexer
4.7 Applications of multiplexers
Multiplexer or data selectors are combinational circuits which transfer data from many sources to output
under the control of data select lines. Multiplexer has many applications right from data routing, time
division multiplexing, function generator to parallel to serial converter etc. A single multiplexer can
replace several logic gates ICs, saving PCB area, interconnections, design efforts and cost. A list of
popular applications is given below.
1. Data routing
2. Data bussing
3. Switch setting comparator
4. Multiplexer as a function generator
5. Parallel to serial converter
6. Cable TV signal distribution
7. Telephone network
4.8 Demultiplexer
A demultiplexer (also known as a DEMUX) is a digital logic circuit that performs the reverse operation of
a multiplexer. It takes a single input and distributes it to one of multiple output lines based on the control
inputs. In other words, a demultiplexer selects one of several outputs and forwards the input signal to that
selected output line.
A demultiplexer has the following key components:
 Data input (D): This is the single input line that carries the input signal to be distributed to one of
the output lines.
 Control inputs (S0, S1, ..., Sm-1): These are the m control inputs that determine which output line
the input signal should be forwarded to. The number of control inputs (m) determines the number
of output lines that the demultiplexer can have (2^m).
 Output lines (Y0, Y1, ..., Yn-1): These are the n output lines where the input signal will be
distributed to. The number of output lines (n) depends on the number of control inputs and is
equal to 2^m.

4.8.1 1:2 Demultiplexer

A 1:2 demultiplexer (also known as a 1-to-2 demultiplexer) is a simple digital logic circuit that takes a
single input and forwards it to one of the two output lines based on the control input. It is the smallest
type of demultiplexer and has one data input (D), one control input (S), and two output lines (Y 0 and Y1).
In 1 to 2 demultiplexer, with S0=0 the Y0 output of demultiplexer receive the input data. Similarly, when
S0 becomes ‘1’, the Y1 output of demultiplexer receives the input data. Thus, the Select or control line
selects the desired output to which the input data is transferred or distributed. Hence, demultiplexer is also
known as data distributor. To distribute the input data D to Y0, the select input S0 should be 0 and Y1 will
receive data input D when S0=1. The Boolean expressions for the outputs are

Y0  S0D
Y1  S0D
The 1:2 demultiplexer can be implemented using logic gates such as AND and NOT gates. Here's the
logic diagram of a 1:2 demultiplexer:

4.8.2 1:4 Demultiplexer

A 1:4 demultiplexer (also known as a 1-to-4 demultiplexer) is a digital logic circuit that takes a single
input and forwards it to one of the four output lines based on the control inputs. It has one data input (D),
two control inputs (S0 and S1), and four output lines (Y0, Y1, Y2, and Y3).
In 1 to 4 demultiplexer, the input data can be distributed to 1 of the 4 outputs. Selection of the output is
decided by the binary word applied to the select lines. With S1S0=00, the Y0 output of demultiplexer
receive the input data. For S1S0=01, the output Y1 receives the input data. With S1S0=10, the input data is
distributed to Y2 and when S1S0=11, the output Y3 receives the input data. The Boolean expressions for
the outputs are:

Y0  S1S0D
Y1  S1S0D
Y2  S1S0D
Y3  S1S0D
The truth table for a 1:4 demultiplexer is as follows:

The 1:4 demultiplexer can be implemented using logic gates such as AND and NOT gates. Here's the
logic diagram of a 1:4 demultiplexer:
4.8.3 Applications of Demultiplexers
Digital demultiplexers are combinational devices controlled by a selector address that routes input data to
one of many outputs of the demultiplexers. These can be used in following applications.
1. Data demultiplexing
2. Clock demultiplexing
3. Memory addressing
4. Four phase clock generator
5. Function generation using DMUX
6. Switch encoding
7. Serial to parallel converter
4.9 Encoder
character into binary code. An encoder has a number of input lines but only one of them is activated at a
time representing a digit or character and produces a binary code depending on which input is activated.
Figure is the logic symbol or block diagram of encoder with ‘m’ inputs and ‘n’ outputs. In short, it is
multiple inputs and multiple outputs device with proper conversion system. Note that encoder performs
the reverse operation of the decoder. The block diagram of encoder is as follows

An encoder has ‘m’ number of input lines and ‘n’ number of output lines. The numbers of outputs (n) are
always less than number of inputs (m).
Thus, the encoder accepts an m-bit input digital word and converts it into an n-bit another digital word.
Encoders can also be devised to encode various symbols and characters for the keypads and keyboards.
Some of the most commonly used encoders are – (1) Linear encoders are octal to binary, Decimal to BCD
and Hexadecimal to binary where normal encoding is implemented and (2) Priority encoders.
Liner encoders: Linear / normal encoders accepts m inputs, only one is activated at a given time and
produces n bit output code. As the numbers of output lines are ‘n’, it is possible to encode maximum up to
2n inputs. In many digital systems, octal, decimal or hexadecimal numbers are used as inputs. Let us now
discuss the working principal and designing of these encoders.
4.9.1 Octal to binary encoder
An octal to binary encoder is also known as 8-line to 3-line encoder. It accepts 8- inputs and produces a 3-
bit output corresponding to the activated octal input. Figure-3 shows the logic symbol of Octal to binary
encoder.

The truth table of octal to binary encoder is shown in Table-1 There are eight inputs corresponding 8 octal
inputs (I0, I1, I2, I3, I4, I5, I6, I7) and 3 Outputs (Y0, Y1, Y2). Let us look at the table carefully.

In the truth table, the input variable I0 represents the least significant digit (LSD) and and I7 represents
most significant digit (MSD). Similarly, in the outputs Y0 represents least significant bit (LSB) and Y2 is
the most significant bit (MSB). The truth table includes only all valid combinations of the inputs. The
valid combinations are those which have exactly one input equal to logic 1 while all other inputs are logic
0’s.
As the number of inputs is 8, K-maps cannot be used to derive the Boolean expressions. The Boolean
expression can be directly derived from the truth table by visual inspection. Let us obtain the Boolean
expression for each output.
Output Y0 is 1 if any of the inputs I1 or I3 or I5 or I7 is 1. Then, the Boolean expression
Y0 = I1 +I3 +I5 +I7
Similarly,
Y1 = I2 +I3 +I6 +I7
and
Y2 = I4 +I5 +I6 +I7
From these Boolean expressions, the Octal to Binary Encoder can be implemented by using simply three
4 input Or gates. Figure-4 indicates the logic diagram for Octal to Binary Encoder.
4.9.2 Decimal to BCD encoder
A decimal to BCD (binary coded decimal) encoder is also known as 10-line to 4-line encoder. It accepts
10- inputs and produces a4-bit output corresponding to the activated decimal input. Figure shows the
logic symbol of decimal to BCD encoder.

The truth table of Decimal to BCD encoder is shown in Table-2 There are ten inputs corresponding 10
decimal inputs (I0, I1, I2, I3, I4, I5, I6, I7, I8, I9) and 4 Outputs (Y0, Y1, Y2, Y3). Let us look at the table
carefully. Note the encoder assumption that only one of the inputs is activated (logic 1) and other inputs
are not activated (i.e. at logic 0).

In the truth table, the input variable I0 represents the least significant digit (LSD) and and I9 represents
most significant digit (MSD). Similarly, in the outputs Y0 represents least significant bit (LSB) and Y3 is
the most significant bit (MSB). The truth table includes only all valid combinations of the inputs. The
valid combinations are those which have exactly one input equal to logic 1 while all other inputs are logic
0’s.
As the number of inputs is 10, K-maps cannot be used to derive the Boolean expressions. The Boolean
expression can be directly derived from the truth table by visual inspection. Let us obtain the Boolean
expression for each output.

Output Y0 is 1 if any of the inputs I1 or I3 or I5 or I7 or I9 is 1. Then, the Boolean expression

Y0 = I1 +I3 +I5 +I7 +I9

Similarly,

Y1 = I2 +I3 +I6 +I7

Y2 = I4 +I5 +I6 +I7

Y3 = I8 +I9
From these Boolean expressions, the Decimal to BCD Encoder can be implemented by using simply three
4 OR gates. Figure-6 indicates the logic diagram for Decimal to BCD Encoder.
4.10 Decoder
Decoder is a combinational logic circuit that converts a binary code into the desired output signals. It is
called decoder because it performs the reverse process of encoder. The process of converting binary input
code into desirable output is known as decoding. In short, it is multiple inputs and multiple outputs device
with proper conversion system. Note that decoder performs the reverse operation of the encoder.
The block diagram of decoder is as follows

Decoder converts an n bit code to single active output. The information present in one code is obtained
back into the desired code. In general Decoder is circuit which convert specific code into more general
form of code.
• A decoder is a logic circuit that accepts a set of inputs that represents a binary number and activates only
the output that corresponds to the input binary number.
• In other words, a decoder circuit looks at its inputs, determines which binary number is present and
activates the one output that corresponds to that number; all other outputs remain inactive
4.10.1 2 to 4 line decoder
A 2-to-4 line decoder is a digital circuit that takes a 2-bit binary input and activates one of four output
lines based on the binary value of the input. It is a specific type of binary decoder, where n (number of
inputs) is 2 and 2^n (number of outputs) is 4. In this decoder, note that S 1 represents MSB and S0 is the
LSB of the input code.
The truth table of 2:4 decoder is as follows:

From this truth table, the logical expression is as follows:

D0  S1S0
D1  S1S0
D2  S1S0
D3  S1S0
4.10.2 3 to 8 (Binary to Octal) decoder
A 3-to-8 line decoder, also known as a binary-to-octal decoder, is a digital circuit that takes a 3-bit binary
input and activates one of eight output lines based on the binary value of the input. It is a binary decoder
with 3 input lines (A, B, and C) and 2^3 = 8 output lines (Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7)
representing the octal code of the active input line.

The truth table for a 3-to-8 line decoder is as follows:

The logic diagram for a 3-to-8 line decoder can be implemented using logic gates such as AND, OR, and
NOT gates. Here's the logic diagram of a 3-to-8 line decoder
4.10.3 Examples of Decoder
Example 4.6 Design a 4 : 16 decoder using 3 : 8 decoder

Example 4.7 Design a 5:32 decoder using 3:8 decoder and 2:4 decoder
Example 4. 8. Design a 4:16 decoder using 2:4 decoder

Example 4.9. Implement full adder using 3 to 8 decoder

Example 4.10. Implement full subtractor using 3 to 8 decoder

4.11 Parity Generator

It is combinational circuit that accepts an n-1 bit data and generates the additional bit that is to be
transmitted with the bit stream. This additional or extra bit is called as a Parity Bit.
In even parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in the data stream and the
parity bit is ‘1’ if there are odd number of 1s in the data stream.
In odd parity bit scheme, the parity bit is ‘1’ if there are even number of 1s in the data stream and the
parity bit is ‘0’ if there are odd number of 1s in the data stream. Let us discuss both even and odd parity
generators.
The truth table is as follows:
Input Output Y
A B C D Even parity bit Odd parity bit
0 0 0 0 0 1
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 0 1
1 0 1 0 0 1
1 0 1 1 1 0
1 1 0 0 0 1
1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 0 1

The circuit for an even parity generator is as follows:

The circuit for an odd parity generator is as follows:

4.12 Magnitude Comparator

A magnitude comparator is a digital circuit used to compare the relative magnitudes of two binary
numbers. It determines whether one number is greater than, equal to, or less than the other number.
Magnitude comparators are commonly used in various digital systems, including arithmetic units and
control logic.
4.12.1 1-bit magnitude comparator
The simplest case of a magnitude comparator is a 1-bit comparator, which compares two single-bit binary
numbers A and B. Let's represent A as A[0] and B as B[0]. The comparator has two outputs: A>B and
A=B. If A[0] is greater than B[0], then the output A>B is set to 1. If A[0] is equal to B[0], then the output
A=B is set to 1. Otherwise, both outputs are set to 0.
The block diagram and truth table for a 1-bit magnitude comparator is as follows:

The circuit for a 1-bit magnitude comparator is shown below:

4.12.2 2-bit magnitude comparator
A 2-bit comparator compares two binary numbers, each of two bits and produces their relation such as
one number is equal or greater than or less than the other. The figure below shows the block diagram of a
two-bit comparator which has four inputs and three outputs.
The block diagram and truth table for a 2-bit magnitude comparator is as follows:

In this context, the first number A is designated as P = P 1P0 and the second number is designated as Q =
Q1Q0. This comparator produces three outputs as (P>Q), (if P = Q) and (P<Q). Let us prepare the K-map
for each output so as to implement the 2-bit magnitude comparator.
The K-map simplification and circuit for a 2-bit magnitude comparator are as follows:
 P  Q 


P1 P0 Q1Q0  P1P0 Q1Q0  P1P0Q1Q0  P1 P0Q1Q0

  
 P1Q1 P0Q0  P0 Q0  P1Q1 P0Q0  P0 Q0 
 P Q  P Q P Q  P Q 
0 0 0 0 1 1 1 1

 P  Q P  Q 
0 0 1 1







4.13 Code conversion
4.13.1 BCD – Excess 3 code conversion
The BCD (Binary Coded Decimal) to Excess-3 code conversion circuit and the Excess-3 to BCD
conversion circuit can be implemented using combinational logic gates such as AND, OR, and XOR
gates.
The truth table for the BCD to Excess-3 conversion is as follows:

K-map simplification for the BCD to Excess-3 conversion is as follows:

The circuit diagram for BCD to Excess-3 code is as follows:
4.13.2 Binary to Gray Code Converters
The truth table for converting a 4-bit Binary number to Gray Code is as follows:

Karnaugh Map for Each Output Bit:

Circuit diagram of binary to gray code converter is as follows:

4.14 Additional Example

Example 4.11 Implement the following function using 8:1 multiplexer:

F ( A, B, C, D)   m 0,1,3,5,8,9,11,14,15

Solution
Example 4.12 Implement the following function using 8:1 multiplexer:

Y( A, B, C, D)  m 1,3, 4,11,12,13,14,15

Solution
4.15 Exercise
A. Choose the correct alternative from the following
1. A 2-to-1 multiplexer has:
a) 2 input lines and 1 output line
b) 1 input line and 2 output lines
c) 2 input lines and 2 output lines
d) 1 input line and 1 output line
2. The Boolean expression for a 2-to-1 multiplexer with inputs A, B, and select line S is:
a) A + B
b) A * B
c) A XOR B
d) A AND S + B AND S'
3. In a 2-to-1 multiplexer, when the select line S is 0, the output is:
a) Input A
b) Input B
c) A + B
d) A * B
4. A decoder is used to:
a) Encode data
b) Generate clock signals
c) Convert binary code to another code
d) Decode binary information to activate a specific output line
5. The output lines of a 3-to-8 decoder are activated based on the:
a) Binary input code
b) Decimal input code
c) Gray code
d) Binary complement of input code
6. A demultiplexer is used to:
a) Combine signals
b) Distribute a single input to multiple outputs
c) Amplify signals
d) Generate clock signals
7. A multiplexer with n select lines can select between:
a) 2^n inputs
b) n inputs
c) 2 inputs
d) 2n inputs
8. The operation of a demultiplexer is controlled by its:
a) Inputs
b) Outputs
c) Select lines
d) Clock signal
9. The sum output of a full adder is the XOR of:
a) A and B
b) A and carry
c) B and carry
d) A, B, and carry
10. The output of a combinational circuit changes in response to:
a) Clock signal
b) Only the inputs
c) Memory elements
d) Both inputs and memory elements
B. Short Answer Type Questions
11. Discuss the significance of priority encoders in designing digital systems
12. Construct the following function using 4:1 multiplexer
Y( A, B, C, D)  m 1,3, 4,11,12,13,14,15

13. Construct the following function using 8:1 multiplexer

Y( A, B, C, D)  m1,3, 4, 6, 7,8,11,12,13,

14. Construct the following function using 4:1 multiplexer

Y( A, B, C, D)  m1,3, 4, 6, 7,8,11,12,13,

15. Design 16:1 Multiplexer using 8:1 MUX and 2:1 MUX.
16. Design 16:1 Multiplexer using 8:1 MUX and a OR gate.
17. Design full adder circuit using 1:8 de-multiplexers.
18. Design full subtractor circuit using 1:8 de-multiplexers.
19. Design full adder circuit using 4:1 MUX.
20. Construct and explain the full subtractor circuit using two half adder circuit through a block diagram.
C. Long Answer Type Questions
21. Design 32:1 MUX using 4:1 MUX.
22. Design 16:1 MUX using 2:1 MUX.
23. Design 6:64 Decoder using 3:8 decoders.
24. Implement a 4-bit binary-to-octal decoder circuit.
25. Design 64:1 MUX using 8:1 MUX.