Verilog Testbenches for Subtractors

The document contains testbench modules for half subtractor, full subtractor, and a custom module p13 in Verilog. Each testbench applies various input combinations to the respective modules and simulates their behavior over time. The simulation ends with a stop command after all test cases are executed.

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Verilog Testbenches for Subtractors

Uploaded by

ghanavigk

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Download as DOCX, PDF, TXT or read online on Scribd

module halfsubtractor_tb;

reg a, b;
wire difference, borrow;
// Instantiate the Unit Under Test (UUT)
halfsubtractor uut (
.a(a),
.b(b),
.difference(difference),
.borrow(borrow)
);
initial begin
// Apply all input combinations
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
#10 $stop; // End simulation
end
endmodule
module fullsubtractor_tb;
reg a, b, bin;
wire D, bout;
fullsubtractor uut (
.a(a),
.b(b),
.bin(bin),
.D(D),
.bout(bout)
); initial begin
a = 0; b = 0; bin = 0; #10;
a = 0; b = 0; bin = 1; #10;
a = 0; b = 1; bin = 0; #10;
a = 0; b = 1; bin = 1; #10;
a = 1; b = 0; bin = 0; #10;
a = 1; b = 0; bin = 1; #10;
a = 1; b = 1; bin = 0; #10;
a = 1; b = 1; bin = 1; #10;
#10 $stop; // End simulation
end
endmodule
module p13_tb;
reg [3:0] a, b;
reg [2:0] sel;
wire [7:0] z;
// Instantiate the Unit Under Test (UUT)
p13 uut (
.z(z),
.a(a),
.b(b),
.sel(sel)
);
initial begin
// Initialize inputs
a = 4'b0011; // 3
b = 4'b0101; // 5
// Test each operation
sel = 3'b000; #10; // a + b
sel = 3'b001; #10; // a - b
sel = 3'b010; #10; // a << 1
sel = 3'b011; #10; // a * b
sel = 3'b100; #10; // a && b
sel = 3'b101; #10; // a || b
sel = 3'b110; #10; // !a
sel = 3'b111; #10; // ~a
#10 $stop; // End simulation
end
endmodule

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Verilog Testbenches for Subtractors

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Verilog Testbenches for Subtractors

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module halfsubtractor_tb;

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