Model Question Paper Solutions
Course: Basics of Digital Logic and Computer Organization (25CS111)
Model Question Paper - 01
PART A (15 marks)
1 mark each
1. a) 1011 (Binary consists of 0s and 1s only).
2. b) 1 (A NOT gate is a single-input device).
3. a) American Standard Code for Information Interchange
4. a) NAND (NAND and NOR are universal gates).
5. a) Difference and borrow
6. a) Delay flip-flop (or Data flip-flop).
7. c) CPU
8. c) PC (Program Counter).
9. a) Universal Serial Bus
10. b) Bus
11. c) NAND inverts AND, NOR inverts OR
12. c) Bit by bit (Serial shifting).
13. c) It can be represented using ON and OFF states
14. b) Synchronous Counter
15. c) NOT
Fill in the blanks:
1. real numbers (Floating point represents real numbers/fractions).
2. outputs
3. one
4. current (Current instruction being executed).
5. output
PART B (10 marks)
Answer any FIVE. (2 marks each)
1. Hexadecimal 2A to Binary:
2 = 0010
A = 1010
Answer: 0010 1010
2. Base Values:
Binary: 2
Octal: 8
Decimal: 10
Hexadecimal: 16
3. Boolean Laws:
Commutative Law: A + B = B + A
De Morgan’s Law: A ⋅ B = A + B
4. Sequential Circuits: Flip-flops, Counters, Shift Registers.
5. Control Unit Function: It directs the operation of the processor by generating
control signals to fetch, decode, and execute instructions.
6. Address Bus: A unidirectional bus that carries the memory address of data to
be read from or written to.
7. Memory Types: RAM (Random Access Memory), ROM (Read Only Memory).
8. I/O Ports: USB, HDMI, Ethernet.
PART C (15 marks)
Answer any FIVE. (3 marks each)
1. Need for Data Representation: Digital computers work with electrical signals
(ON/OFF). Data representation (like Binary, ASCII) is needed to translate
human-readable information (numbers, text, images) into a binary format the
machine can process and store.
2. Binary vs BCD:
Binary: A continuous representation of value. Example: 1510 = 11112 .
BCD: Replaces each decimal digit with a 4-bit binary code. Example:
1510 = 0001 0101BCD .
3. NAND as AND: Connect two NAND gates. The first NAND produces A ⋅ B .
Feed this into a second NAND (configured as a NOT gate by joining inputs). The
result is A ⋅ B = A ⋅ B .
4. SOP vs POS:
SOP (Sum of Products): ORing of AND terms. Example: Y = AB + AC .
POS (Product of Sums): ANDing of OR terms. Example:
Y = (A + B) ⋅ (A + C).
5. Multiplexer (MUX): A combinational circuit that selects one of many input
signals and forwards the selected input to a single output line. Applications:
Data routing, waveform generation, parallel-to-serial conversion.
6. Von Neumann Architecture: A design model for a stored-program digital
computer. Key Components: CPU (ALU + Control Unit), Memory Unit (storing
both data and instructions), and Input/Output mechanisms, connected by a
system bus.
7. Bus Roles:
Data Bus: Bidirectional; carries actual data.
Address Bus: Unidirectional; carries memory locations.
Control Bus: Carries control signals (Read/Write, Interrupts).
8. Memory Differentiation:
Primary: Volatile, fast, CPU accessible (e.g., RAM).
Secondary: Non-volatile, slower, high capacity (e.g., HDD/SSD).
Tertiary: Archival storage (e.g., Magnetic Tape).
PART D - Section I (25 marks)
Answer any FIVE. (5 marks each)
1. BCD (Binary-Coded Decimal):
Purpose: Used where precise decimal accuracy is required (e.g., financial
systems) to avoid rounding errors common in floating-point binary.
Decimal 59 in BCD: 5 = 0101, 9 = 1001. Result: 0101 1001 .
Decimal 59 in Pure Binary: 32 + 16 + 8 + 2 + 1 = 59. Result: 111011 .
Comparison: BCD uses more bits (8 bits) than pure binary (6 bits) for the
same number.
2. Basic Logic Gates:
AND: Output High only if all inputs are High. Y = A ⋅ B .
OR: Output High if at least one input is High. Y = A + B .
NOT: Inverts the input. Y = A.
Uses: AND for security enable; OR for dual-switch lighting; NOT for signal
inversion.
3. POS Derivation from Truth Table:
Look for outputs where Y = 0.
Row 3 (0,1,0): Term is (A + B + C).
Row 4 (0,1,1): Term is (A + B + C ).
Row 6 (1,0,1): Term is (A + B + C ).
Row 7 (1,1,0): Term is (A + B + C).
Final Expression:
Y = (A + B + C)(A + B + C )(A + B + C )(A + B + C).
4. MUX and DEMUX Applications:
MUX: Communication systems (combining calls on one line), Logic function
implementation without simplification.
DEMUX: Decoding addresses, routing data to different printers/devices
from one source, serial-to-parallel conversion.
5. Instruction Execution Cycle:
Fetch: CPU retrieves instruction from memory using the Program Counter
(PC).
Decode: Control Unit interprets the opcode to understand what action to
perform.
Execute: ALU performs the calculation or data is moved.
(Store): Results are written back to memory/registers.
PART D - Section II (30 marks)
Answer any THREE. (10 marks each)
1. Truth Table Construction (from Circuit Diagram on Page 4):
Analysis:
Gate 1 (Top): NAND gate with inputs A and B. Output X = A ⋅ B .
Gate 2 (Bottom): NOT gate with input C. Output Z = C .
Gate 3 (Right): 3-Input AND gate. Inputs are X , B (directly), and Z .
Equation: Y = (A ⋅ B ) ⋅ B ⋅ C .
Logic Simplification:
(A + B ) ⋅ B ⋅ C
(AB + B B) ⋅ C
(AB + 0) ⋅ C = A ⋅ B ⋅ C .
Truth Table: Output is 1 ONLY when A=0, B=1, C=0. All other states are 0.
2. XOR Cipher:
Decoding:
Encoded (X): 0 1 1 0 0 (Derived from
M ⊕ K = 11001 ⊕ 10101 = 01100).
Key (K): 1 0 1 0 1
Decode Operation: X ⊕ K
0⊕1=1
1⊕0=1
1⊕1=0
0⊕0=0
0⊕1=1
Decoded Message M: 11001 (Matches original).
3. Washing Machine Control:
a) Sequential Circuit. Because the output depends on the current state
(e.g., Rinse) and proceeds to the next state in a specific order. It requires
"memory" of where it is in the cycle.
b) Components:
Counter: To track the time for each stage.
State Register (Flip-flops): To store the current mode (Fill, Wash, etc.).
Model Question Paper - 02
PART A (15 marks)
1. c) Because digital circuits understand only binary
2. c) All flip-flops are triggered by the same clock pulse
3. c) To reduce complexity and cost
4. c) XOR (Exclusive OR is high when inputs differ/only one is high).
5. a) 0011 (Invert bits: 1->0, 0->1).
6. c) T (Toggle flip-flop).
7. c) NAND (It is a universal gate, derived from AND+NOT).
8. c) 8 (0 to 7).
9. b) AND + NOT
10. c) Store data temporarily during processing
11. c) Addition of two bits
12. b) Data selector
13. c) Store the address of the next instruction
14. b) RAM
15. c) Hard Drive
Fill in the blanks:
1. eight
2. XOR
3. asynchronous
4. same memory
5. non-volatile
PART B (10 marks)
1. Octal of 111010:
Group by 3: 111 010
1112 = 7
0102 = 2
Answer: 728
2. Unicode vs ASCII: Unicode represents text for most of the world's writing
systems (16-bit/32-bit), whereas ASCII is limited to English/Latin characters (7-
bit/8-bit).
3. AND Gate: A digital gate that outputs High only if all inputs are High. Symbol:
D-shape.
4. Combinational Circuits: Adder, Multiplexer, Encoder, Decoder.
5. ALU: Arithmetic Logic Unit. Performs mathematical (add, sub) and logical
(AND, OR) operations.
6. Registers: Accumulator (ACC), Program Counter (PC), Instruction Register (IR).
7. System Buses: Data Bus, Address Bus, Control Bus.
8. GPU Function: Graphics Processing Unit. Specialized for parallel processing,
primarily for rendering images and video.
PART C (15 marks)
1. 1's vs 2's Complement:
1's Comp: Invert all bits (Example: 101 → 010). Has two zeros (+0, -0).
2's Comp: Invert all bits + 1 (Example: 101 → 010 + 1 = 011). Has unique
zero.
2. Floating Point Structure:
Sign bit: 0 for positive, 1 for negative.
Exponent: Represents the scale/magnitude.
Mantissa: Represents the precision/significant digits.
3. AND/OR/NOT: (Standard truth table definitions).
4. NAND to AND: NAND gate followed by a NOT gate (made from a NAND).
5. Decoder Applications: Memory address decoding, 7-segment display driver,
Instruction decoding in CPU.
6. Fetch-Decode-Execute: (See MQP-01 Part D Q5).
7. CPU vs GPU: CPU has few powerful cores for serial processing (logic/OS).
GPU has thousands of smaller cores for parallel processing (graphics/matrix
math).
8. Memory Size Order: Register < Cache < RAM < Hard Disk.
PART D - Section I (25 marks)
1. Binary Addition:
10110(22) + 00111(7)
0+1=1, 1+1=0(c1), 1+1+1=1(c1), 0+0+1=1, 1+0=1.
Result: 11101 (29).
2. SOP Derivation:
Target rows where Y = 1.
Row 2 (0,0,1): AB C
Row 3 (0,1,0): AB C
Row 4 (0,1,1): ABC
Row 5 (1,0,0): ABC
...etc. Sum these terms.
3. Circuit Truth Table (from Page 8 diagram):
Assumption based on typical shapes in diagram: Top is NAND, Bottom is
XOR (curved back), Final is AND.
Y = (A NAND B) ⋅ (A XOR B)
Y = (AB ) ⋅ (AB + AB)
Since AB implies AB is false (0), the NAND output is always 1 when XOR
is 1.
Result: The circuit acts exactly like an XOR gate.
Table: 00->0, 01->1, 10->1, 11->0.
4. Encoder vs Decoder: Encoder converts active input line to binary code
(compression). Decoder converts binary code to active output line
(expansion).
5. ISA: Instruction Set Architecture. Interface between software and hardware.
Types: Data transfer, Arithmetic, Logical, Control flow.
PART D - Section II (30 marks)
1. Gate Selection:
a) OR (1 if at least one is 1).
b) XNOR (1 if inputs are same: 00 or 11).
c) NOR (1 only if all inputs are 0).
d) NOR (Assuming "Switch Off" = 0, output 1 when both 0).
e) XOR (1 iff inputs are different).
2. Smart Home Logic:
Inputs: S1, S0. Outputs: Bedroom(B), Living(L).
Mode 0 (00): Off.
Mode 1 (01): Bedroom ON (B = 1, L = 0).
Mode 2 (10): Living ON (B = 0, L = 1).
Mode 3 (11): Both ON (B = 1, L = 1).
Logic:
Bedroom is ON when S0 is 1 OR (S1 is 1 AND S0 is 1)... actually simpler:
Bedroom is ON when Bit 0 is 1? No.
Let's map: 00->00, 01->10, 10->01, 11->11.
This is a 2-to-4 Decoder connected to the lights (Logic High drives
the light).
Model Question Paper - 03
PART A (15 marks)
1. a) 1101 (8 + 4 + 1 = 13)
2. a) Unicode
3. b) 0 (NAND is inverse of AND. 1 AND 1 = 1, so NAND = 0).
4. a) 3-in, 2-out (Inputs: A, B, Cin. Outputs: Sum, Cout).
5. a) RAM
6. b) ASCII (Historically, though Unicode is modern standard, ASCII is the classic
answer for "code"). Note: Q2 acknowledges Unicode is larger.
7. a) All inputs are 1
8. c) Multiplexer (No clock/memory).
9. d) The same memory and bus
10. c) Signal that stops the CPU temporarily
11. b) Control Unit (It manages I/O, though CPU generally communicates via Bus
Interface). Actually, closest answer for "unit" managing flow is Control Unit.
12. b) Perform logical operations
13. b) Use of memory (Sequential has memory).
14. d) OR
15. c) Multiplexer
Fill in the blanks:
1. ASCII
2. adder
3. flip-flops
4. ALU
5. bus protocols (or interfaces).
PART B (10 marks)
1. Complements of 00010101:
1's: 11101010
2's: Add 1 to 1's → 11101011
2. Decimal 255 to Hex:
255/16 = 15 remainder 15.
15 = F .
Answer: FF
3. Universal Gate: A gate capable of implementing any Boolean function without
other gate types. Examples: NAND, NOR.
4. Flip-Flops: SR, JK, D, T.
5. Instruction Cycle: The complete process of fetching, decoding, executing,
and storing an instruction.
6. Von Neumann Components: CPU, Memory, I/O.
7. Output Devices: Monitor, Printer, Speaker.
8. Interrupt: A signal sent to the processor requesting immediate attention,
suspending the current task.
PART C (15 marks)
1. BCD 0100 0011 to Decimal:
Split into 4-bit groups: 0100 and 0011 .
01002 = 4
00112 = 3
Answer: 4310
2. Negative Numbers: Represented using Signed Magnitude (MSB is sign), 1's
Complement, or 2's Complement (standard).
3. Significance of Boolean Expressions: Allows mathematical modeling of
circuits to simplify them (reduce gate count) before physical construction.
4. Truth Table Y = A ⋅ B + A ⋅ C :
This is a 2:1 MUX logic.
If A=0, Y=C. If A=1, Y=B.
Rows: 000(0), 001(1), 010(0), 011(1), 100(0), 101(0), 110(1), 111(1).
PART D - Section I (25 marks)
1. Negative Representations (-25):
Binary of 25: 00011001
Signed Magnitude: Set MSB to 1 → 10011001
1's Complement: Invert bits → 11100110
2's Complement: Add 1 → 11100111
2. SOP Derivation (Table in Q2):
Identify output 1 rows.
Write minterms (e.g., AB C ).
Sum them up.
3. NAND vs NOR:
NAND: 0 only if both inputs 1.
NOR: 1 only if both inputs 0.
Include truth tables.
4. Counters: Digital circuits that traverse a sequence of states upon clock
pulses. Applications: Digital clocks, Frequency dividers, Event counting.
5. CU and ALU:
CU decodes instruction and sets control lines.
ALU performs the math requested by CU.
They work together: CU says "Add", ALU adds.
PART D - Section II (30 marks)
1. Truth Table Procedure: Identify gate types → write intermediate boolean
expressions → substitute input values (0/1) for every combination.
2. Scoreboard System:
a) Sequential Circuit. Scores must be stored and incremented.
Combinational circuits cannot store history.
b) Components:
Registers: To hold the score.
Adders: To increment score.
Decoder/Driver: To show score on display.
3. Full Adder from Half Adders:
Standard block diagram: Two Half Adders and an OR gate.
Sum = A ⊕ B ⊕ Cin
Carry = AB + Cin (A ⊕ B)
4. Addressing Modes:
a) MOV R1, #5 : Immediate Addressing (Data is in instruction).
b) MOV R2, [1000] : Direct Addressing (Address given directly).
c) ADD R3, [R1] : Register Indirect (Address held in register).
d) MOV R4, [R2 + 4] : Indexed/Displacement Addressing.
e) MOV R5, R3 : Register Addressing.
5. Storage Calculation:
a)
i) Movies: 500 × 5 GB = 2500 GB.
ii) Songs: 1000 × 8 MB = 8000 MB = 8 GB (approx).
iii) Photos: 2000 × 3 MB = 6000 MB = 6 GB.