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PAM4 DSP Advances for 400GbE+

The document discusses advancements in PAM4 DSP architecture for applications beyond 400GbE, highlighting key components such as low power MLSD and soft FEC for improved performance. It reviews current technologies used in 100G and 400G systems, emphasizing the benefits of high-speed ADCs and DSP equalization capabilities. The findings suggest that these advancements will facilitate the development of future high-speed networking solutions.

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12 views10 pages

PAM4 DSP Advances for 400GbE+

The document discusses advancements in PAM4 DSP architecture for applications beyond 400GbE, highlighting key components such as low power MLSD and soft FEC for improved performance. It reviews current technologies used in 100G and 400G systems, emphasizing the benefits of high-speed ADCs and DSP equalization capabilities. The findings suggest that these advancements will facilitate the development of future high-speed networking solutions.

Uploaded by

xl
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

PAM4 DSP Architecture Advances for Beyond 400GbE

Ilya Lyubomirsky, Jamal Riani, and Arash Farhoodfar, Inphi Corp.


IEEE 802.3 NEA Beyond 400GbE CFI Consensus Development, Sept. 14, 2020
Summary

▪ 100G per Lambda/per Lane PAM4 Rx DSP Architectures


▪ Identify Potential DSP Building Blocks for Beyond 400GbE
▪ Low Power MLSD
▪ Soft FEC for Low Latency Higher Coding Gain
▪ Conclusions

2
100G PAM4 Rx DSP Architecture

Err Gen

Analog Digital
1. High Speed ADC enables LMS LMS
DSP Architectures Baud Rate
1/T

AFE ADC 10-30 tap FFE DFE

Slicer Mux FEC


2. FFE, DFE, and
MLSD for stronger EQ
MLSD

LF 3. Leverage DSP soft


PLL DCO TED
information for higher
coding gain FEC

3
Maximum Likelihood Sequence Detection (MLSD)

X
◼ Fully equalizing postcursor tap (f) through the FFE is expensive in
terms of noise enhancement →high SNR penalty vs channel IL f
X
X: sampling points

◼ Commonly a DFE is used to handle postcursor ISI:


― Only channel energy at main tap is used for symbol detection X X X X
Time in
― Postcursor energy is thrown away → suboptimal Baud

Postcursor energy is
◼ Optimal detection has to use all signal energy. Both symbol k and
symbol k+1 contains directly information on PAM symbol k, through f f thrown away!
main tap or postcursor tap
― Such optimal detection is achieved by applying sequence
detection seeking to find the Maximum Likelihood sequence
FFE Slicer
_ dec.

UI
X
Reference: farhoodfar_3bj_01_0912 delay
f

4
Measurement Results for 53Gbaud LR PAM4 SerDes

Variable IL measurement setup for 7nm SerDes test chip Measured BER vs. Channel IL

5
200G Dispersion Penalty Simulation Results: Looking Ahead to Beyond 400GbE

Tx chirp

FR4 2km

6
Concatenated Codes: ADC Enables Soft Decision Inner Code in the Module DSP

KP4 KP4

Source: Frank Kschischang, “Introduction to Forward Error Correction,”


OFC Short Course, 2018

7
Low Complexity/Low Latency Soft Decision FEC (SFEC) Measurement Results

SFEC latency < 1 ns


SFEC power 55-65 mW
SFEC Coding Gain @ KP4 FEC
threshold = 1.61dB
per 100G lane

8
Second Generation SFEC Simulation Results

Source: “Next Generation PON and Data Center Interconnect: Exploring Synergies on FEC,” IEEE Summer Topical, July, 2019

9
Conclusions

▪ We reviewed PAM4 DSP technology deployed today in 100G per lane


electrical SerDes as well as 400G FR4/DR4/LR4 optical modules

▪ Rx DSP equalization capabilities far exceed the assumptions that went into
PAM4 TDECQ reference equalizer; DSP based equalizers can include 10-30
tap FFE, 1-tap DFE, and MLSD

▪ Advancements in high speed ADC technology also open the way toward low
latency higher gain soft decision FEC; such soft decision FECs are already in
use for enhancing the reach and/or lowering optical module costs

▪ Beyond 400GbE project will be able to leverage these DSP advancements

10

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