Combinational Circuit Design

Digital Electronics
3-27

Sol. Implementation tables

Carry Implementation

Do D D2 D
1 Do
1D
1 D2
Logic 1 1 Da 1 Y
Carry
A A 1 |2 Do Quadruple Sum
2Y
Sum 2 D1 2:1
MUX
D D 2 D2
D2 Da 2 Da
EN
2 EN
B
A A AA
B in

Fig. 3.10.17
Ex. 3.10.15 Realize F(w, x, y, z) = (1, 4, 6, 7, 8, 9, 10, 11, 15) using 4 to 1 MUX. AU : May-04, Marks 8

Sol.

D D3
Wx

Wx 5

Wx

Wx 13 14

D wx+wX D=WX+WX =
w x

D2 = Wx+w
D3= W x+wX+Wx
xD D 4:1 F
D, MUX
= w© x = X+W X

W+X
D
Fig. 3.10.18
Ex. 3.10.16 Implement the function with a multiplexer.
HA, B, C, D) =
2 0,1,3,4,8,9,15) AU: Dec.-08, 14, Marks 6

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3 -28

Digital Electronics Sol.

Sol. Do
D
Implementation table Logic1
D7 D2
D D2 D4 Dg
D3 8:1
7 MUX
5 D4
A
OO 2
13 4 D
B8 10 12
A
D6
1 0 A A

Implementation
ABC
Logic 1
Fig. 3.10.21

Ex. 3.10.19 Implement

the following function usin
MUX F
8:1 suitable multiplexer
F(A, B,C,D) = 2 (1, 3, 4, 11, 12, 13, 14, 15)

AU: May-11, 16, Marks 8

Sol.
Fig. 3.10.19
Ex. 3.10.17
Implement the fellowing function using
suitable multiplexer. +5V(Logic 1)
FCx, y, z) =m
(0, 2, 5, 7) AU: May-09, Marks 2
Sol.

Logic 1 D
D
2
D 8:1 161 F
MUX MU
Ds 10
D6 11
12
D- 13
14
15

(Logic 0)F SS2 S So

Fig. 3.10.20
emw..

x. 3.10.18 A B C
:1
Implement
multiplexer.
the given Boolean function
using
"A, B, C) = 21, 3, 5, 6)
Fig. 3.10.22
wwww

AU Dec.-09, Marks 6 Ex. 3.10.20 Realize the

multiplexer F(A, B, C) Boolean function using
= 0,1,3,7) approP
"opriate

TECHNICAL AU Dec.-11, Marks

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 Combinational Circuit Design

Digital Electronics 3 29
Roview Questions

Sol. 1. Defne multiplexer AU: Dec.-06, Marks 2

selector.
data 1
(Logic 1)+5 V 2. What is
the working of 2
and explain basic gates.
3. Draw realize it using
and
multipexer AU: Dec.-03, Marks 2
with help of logic
the
multiplexer
8:1 4; 1
MUX
-F 4. Explain AU: Dec.-03, Marks 8
truth table.
circuit and
4 : 1 multiplexer.
5. Write the
truth table of a AU: May-08, Marks 2
with the help of logic
1 multiplexer
6. Explain 8
table.
circuit and truth
Fig. 3.10.23 and working of quadruple 2
7. Explain the concept AU: May-07, Marks 6
Examples for Practice to 1 line multiplexer.
Ex. 3.10.21 Implement the following function using 8:1 8. State the applications of multiplexers.
multiplexer
fa, b, c, d) = 2m (0, 1, 5, 6, 8, 10, 12, 3.11 Demultiplexer AU: May-04, Dec.-09,16
15) circuit that receives information
A demultiplexer is a
Implement Boolean function f = AB + transmits this information on one
Ex. 3.10.22 on a single line and
The selection of specific
CD+ABC using 8: 1 multiplexer. of 2" possible output lines.
the values of n selection
output line is controlled by
3.10.7J Applications of Multiplexer lines.
1. They used as a data selector to select one out
are
of many data inputs.
Data inpu Pin
can be used to implement combinational
2 They
logic circuit.
1:2
3. They are used in time multiplexing systems. DEMUX

4. They are used in frequency multiplexing systems.

5. They are used in A/D and D/A converter. Enable Y2n
6. They are used in data acquisition systems.
S-1 s So
3.10.8 Multiplexer ICs (a) Block diagram

ICnumber Function Yo
74150 16:1 multiplexer
Y2
8:1 multiplexer Data inpu
74151

74153 Dual 4: 1 multiplexer

Y2-1
74157 Quad 2-input multiplexer
Refer Appendix A for details Sp-1 S2 S, So
Select inputs
Table 3.10.3 Multiplexer ICs (b) Equivalent circuit

Fig. 3.11.1
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 Combinational Circuit n
30
Digital
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line, 2" output ii
he the block diagram of a demultiplexer. It has
one input data
put lines;
Fig. 3.11.1 shows
n select lines and one enable input.

Differentiate between Multiplexer and Demultiplexer

Parameter Multiplexer Demultiplexer

Definition digital Demultiplexer is a circuit

Multiplexer S a
that receives information on
switch which allows digital
information from several a single line and transmits
sources to be routed onto a this information on one of
single output line. 2 possible output lines
Number of data inputs
Number of data outputs 2

Relationship of input and Many to one One to many

output
APplications Used as a data selector U s e d a s a data d i s t r i b u t o r

In time division Intime

multiplexing at the
division
transmitting end
multiplexing he
receiving end
3.11.1 Types of Demultiplexers
[Link] 1:4 Demutiplexer
Fig. 3.11.2 shows 1:4
input information is demultiplexer.
The single
the
directed to input variable Dn has a path to all four
input should be high to enable
only one of the
output lines depending on the select outputs, but
demultiplexer. inputs. Enable
So
Enable (E)S, SoDnY%|YY2 Ys|
0
Din
DES5, Yo XXX|ooo
o oo o
0o o
0 011 10o oD,
Din isis routed
YoE3, So
to Yo
routed to
Dn
ES,S Din 1
0
0
0
1 Din is routed to
Y
ES5 Dn y 1
110 o0YES So Dn
10
1 1 Din is routed to Y2
ESS Din Y3 1 2E S, So Dn
1 1 1
Enable o o oDa
Din is
(a) Logic diagram
1
routed to Y
is routed to Y3
Y3 ES, S, Din
(b) Function table for 1:4
demultiplexer
Fig. 3.11.2
 eight p
out
a 1 : 8Demultiplexer

to all
path inputs.
has a
1:8 demultiplexer. The single input data D
select

3.11.3
3.11.3 shows
s ho the
ie. on
Fig.
information is rected to only one of depending
the output lines
The
t h ei n p u ti n f o

S2 So

ES,3,S Dn Yo
Din

ES SS DnY2
Data Din
input
ES,S,Sp DinY
1:8 Y3 ES,S Din.Y4
DEMUX Y4

E
Es3S0 DnYs
Enable
ESSS DnYs
So S,S
ESSS Din,Y7
Select inputs
Enable o
(a) Block schematic (b) Loglc diagram

Enable Select inputs| Outputs

E SYY%%YYsYY
0 0 0
0 x x x |o o 0 0 0
0 0 0 0 o 0 ES, S,S, Dn
0 0 o Dn 0
0 1 0 Din
o 0 0 ES S, 5% Dn
1 01 0 0 o P 0 0 0 o o E
Sy S,$% Pin
o o 0 D 0 0 0 o ES, s, S, D
1 |0 11 www

o 0 o 0 D 0 0 0 ES S, 5 D.
1 1 o

01 o
0 0 0
o ES S 5, Din
1 1
11 1 o 0 0
0 0 0
ES,SS%Din
1 1 1 1 00 o 0010 Dn Es, s, S D
(c) Function table

Fig. 3.11.3 1:8demultiplexer

circuit. AU May-07, Marks 8
AL1 demultiplexer
Draw the diagram 1 to 16
e dagram and explain

ww.-n.

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 3-32

Digital Electronics
Sol. Din
So
3

Yo

D Y2

Y
Y4

- Ys

D
Ya

D-
Y10

D Y11

D-Y
D Y13

TTTTTTI
- Y15

Fig. 3.11.4 1 to 16
3.11.2 Expanding Demultiplexers Demultiplexer
To provide larger
output needs we can cascade two or more
more number of output lines. Such a demultiplexer to get demultiplexe with

connection is known as
demultiplexer tree.
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 Combinational Circuit Design

Digital Electronics 3-33

Ex. 3.11.2 Design 1: 8

demultiplexer using two 1: 4 Din DEMUX
1:4 1
demultiplexers. Din
3
Solution: A

Step 1: Connect D signal to D input of both select

the demultiplexers. inputs
Step 2 Connect select lines B and C to select S
lines S, and of the both
So demultiplexers, Din 1:4 Ys
respectively. DEMUX 2 -Ys
Step 3 Connect most significant select line (A) Y7
such that when A = 0 DEMUX 1 is
enabled and when A = 1 DEMUX 2 is of demultiplexers
3.11.5 Cascading
enabled. Fig.

Ex. 3.11.3 mplement 1 : 16 demultiplexer using 1:4 demultiplexers.

Sol.

Oo
-O
Pin 1:4
Demux 2 Y2 O2

Yo
1:4 Os
Din Demux 3 Y2

Yo Po
1:4
Din Demux 1 Y2

-O
in 1:4
Demux 4 Y2-O10
-O1

O12
Pin 1:4
-

O13
Demux 5 Y O14
O15

S So

Fig. 3.11.6 1: 16 Demux using 1 :4 Demux

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 ircuit nDesian
Combinational Circuit
3-34
Digital Electronics select one
Step 3 Logically
to minterms.
OR the outputs correspos
orrespondin
outputs. To
demultiplexer has 16 16) select demultiplexer gives minter
h e 1: 16 2"
input 1,
-

needs 4 (::
the circuit With D required mi
of the 16 output,

lines. Each 1 : 4
demultiplexer requires 2 select
lines.
the output
can
so by
implement
logically ORing
Boolean functions mintermy
for
lines (S, we
implementat
Step 1:Connect two least significant select
demultiplexer.
subtractor. Fig. 3.11.7
shows the
tation
4: 1
lines of four s u b t r a c t o r using
demultiplexer.
So)toselect full

more 4:1
demultiplexer such
Step 2: Connect one to the data
are routed
that its four outputs
Connect o
four demultiplexers.
inputs of the
to the select lines
higher select lines (S S2) -D
of this demultiplexer. 2
1:8
Examples for Practice Din- 1 DEMUX

Draw 1 64 demultiplexer tree using 1 : 16

Ex. 3.11.4 :

demultiplexer.
Ex. 3.11.5 Draw 1 : 64 demultiplexer tree using 1: 8
So S S2
demultiplexe.

A B C
3.11.3 Implementation of Combinational Logic
using Demultiplexer
Ex. 3.11.6 Fig. 3.11.7 Full subtractor using 1 8 demultiplexer
Implement full subtractor using demultiplexer.
Ex. 3.11.7 Implement the
AU Dec.-09, Marks 10 following functions using
Sol. demultiplexer:
(A, B,C) -2 m(0, 3, 7)
Step 1 Write the truth table of full
subtractor. S2 (A,B,C) 2 m(1, 2, 5)
Step 2 Represent output of full-subtractors in Sol.
minterm form.
B (A, B, C) =m (0, 3, 7)
in
0 (A, B, C) m(1, 2, 5)
1
Implementation using 1:8 demultiplexer.

DIn 1 1:8
DEMUX
1
Table 3.11.1 Truth
For full
subtractor
table of full
subtractor D
difference D function
written as D =f(A, B,
C) m
can be
unction can be (1, 2, 4, 7) and
Bout
written as, AB C
Bout F (A, B, C)
- 2 m(1,2,3, 7) Fig. 3.11.8
T
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 Combinational Circuit Design
Digital Electronics
3 35
Examples for Practice
Inputs
Ex. 3.11.8
Implement full adder using
demultiplexer. 8
Ex. 3.11.9
Implement the following functions
using
demultiplexer
(A, B, C) = m (1, 5, 7) n-bit
z (A, B, C) = 2m (3, 6, 7) comparator

3.11.4 Applications of Demultiplexer

1. It can be used as a decoder. A>B A-B ACB

2. It can be used as a data distributer. Outputs

3 It is used in time division
multiplexing at the
of n-bit comparator
receiving end as a data separator. Fig. 3.12.1 Block diagram

4 It can be used to
implement Boolean expressions.
Ex. 3.12.1 Design 2-bit comparator using gates.
3.11.5 Demultiplexer ICs Sol.

The truth table for 2-bit is given in Table 3.12.1.

IC Number Function

74154 1:16 Demultiplexer Inputs Outputs

74155 Dual 1: 4
Demultiplexer BoAB A =B A <B
A Ap B
Refer Appendix A for details 1 0
0 0 0
****

Table 3.11.2 Demultiplexer ICs

0 0
Review Questions
1. Define demultiplexer. AU:May-04, Marks 2

2. Differentiate between multiplexer and 0 1 0 0

demultiplexer.
3. State the applications of demiltiplexer.
4. Design and explain 1 of 8 demultiplexer
1
AU:Dec.-16, Marks 8
1 0 1

3.12 Magnitude Comparator 0 0 0

AU: May-08, 11, 12, 16, Dec.-13, 14, 16,17 1 0

A Comparator is a special combinational circuit
esigned primarily to compare the relative magnitude
1 0
of two binary numbers. Fig. 3.12.1 shows the block

agram of n-bit comparator. It receives two n-bit

an 0
umbers A and B as inputs and the outputs are A> 1 1 0 0 0
the relative
B,
A B and A < B. Depending upon 1 1 1 1
nagnitudes of the two number, one of the outputs
will be high.
Table 3.12.1

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 K-map simplification

A B A<B
A>B
AA B,B 01 11 10 AA
B,Bo 01 11 10 AA 0 01 1110
oo 00 o o 0o

01 01 01

11

10
10 oO
A>B
AB,Bo +AB,+ AAp5o

Fig. 3.12.2
(A B)
AA B, +AA B,B, AA B,B AAo B,Bo + +

A,B, (Aga,+ AB) A,B, (AB, +AgB)

-

(A B) (A, ©
B,)
(A B) AA, B, +A B,B+AB
Logic diagram

B Bo

A>B

D
A=B
D

A<B

T
Fig. 3.12.3
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 "8 VUstC
astc 8ates,
gates.
12.2
PO
: Consider t w one bit number A and B. The
truth table is as shown.
Inputs Outputs
A
B YA-B YA>B AB
0 0 1 0 0
0 0 0 1
10 0 0
1 1 1 0 0

B
A BO B A -YA>B
o -YA= B
0

YA=BAB+AB
= AB
YAB AB YAB AB
B
D- YAB
AOB
(a) k-map simplification (b) Logic diagram

Fig. 3.12.4
3.12.3 Design a 5-bit magnitude comparator using comparator IC 7485 AU : May-08, Marks 8

Truth Table

deononooenee

Bo I(A>B) IA B) I(A B
0 0 0
0

0 0

0
 3-38
Desi
Input B
Digital Electronics Input A
Implementation

A1
B4 B3 B2 B
As Ag Az
IA B)
4-bit comparator

Bo I(A = B)
(7485)

B) A AB A<B
A
A Bo
Output

Fig. 3.12.55
AU : May-12
3.12.1 4-bit Magnitude Comparator

Ag

A2 D
DDAL
A
(A<B)

B- X
D
Ap
D
Bo (A B)
D
(A B)
Fig. 3.12.6 4-bit
comparator
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 Combinational Circuit Design

Digital Electronics
3- 39 so that the
comparator,
word
Consider two binary numbers, A and B with four 4. Design a
4-bit

digits each. the table.

output follows
Output
Word
A = Ag Az Aq Ap
1 00
A B
and
B B Ba B, Bo 0 10
A> B
When the numbers are binary, the digits are either 0
1
or 1, and the equality of each A <B
pair of bits can be
expressed logically with an exclusive-NOR function
AU:May-12, Marks 16
as
with three
comparator
4-bit magnitude
X A , B, + A, B, 5. Design a
B.
and A <

outputs: A >B, A =B
i = 0, 1, 2, 3 AU: Dec.-14, Marks 12
for
with 3
4-bit magnitude comparator
where X = 1 only if the pair of bits in position i are 6. Design a

: A > B, A B, A < B.
=

equal. This can be expressed as outputs

AU : May-16, Marks 8

(A B) =
x3 X2 X1 Xo 7. Describe the operation of 3-bit magnitude
To determine whether A is greater or less than B, we comparator. AU: Dec.-16, Marks 13
check the relative magnitudes of pairs of significant
digits, starting from the most significant position. If 3.13 Decoder AU:Dec.-06, 13,17, May-07
the two digits of a pair are equal, we compare the
A decoder is a multiple-input, multiple-output logic
next lower significant pair of digits. The
comparison circuit which converts coded inputs into coded
continues until a pair of unequal digits is reached. If
and codes
corresponding digit of A is 0 and that of B is 1, we outputs, where the input output are

can say that A < B. If the corresponding digit of A is

different.
1 and that of B is 0, we can say that A > B. The Fig. 3.13.1 shows the general structure of the
decoder circuit. As shown in the Fig. 3.13.1, the
The above sequential comparison can be expressed encoded information is presented as n inputs
logically by the two Boolean functions.
producing 2" possible outputs. The 2" output values
are from 0 through 2" - 1.
(A B) A sB3 +X3 AzB2 +Xg*2A1B1 +XgX2X1A gBo
(A B) AB3 +X3 A2B2 +Xg X2 AB, +x3 X2 XAgBo
Note: x = AB + A B = AB+AB n-data
inputs
Possible
n:2
Review Questions Decoder n
2 outputs
1. Write the function of magnitude comparator Enable
AU: Dec.-17, Marks inputs
2. Draw the block schematic of magnitude
comparator and explain its operations. Fig. 3.13.1 General structure of decoder
AU: Dec,-13, Marks 16 Usually, a decoder is provided with enable inputs to
activate decoded
. Explain a 2-bit magnitude comparator with gate based output When on data inputs.
any one enable input is unasserted, all outputs of
level circuit and truth table.
decoder are disabled.

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 Digital Electronics - 40
Combinational Circuit De..
esig
3.13.1 Binary Decoder 1 0 1o 0 0
A
decoder which has an n-bit
a one
binary input code andd 0 0 0 0
activated output out of 2" code is called
output
binary decoder. A binary decoder is used when it is
necessary to activate exactly one of 2" Table 3.13.1 Truth table for a 2 to 4
on an
n-bit
outputs based decoder
input value. Ex. 3.13.1 Draw the circuit for 3 to 8
decoder
Fig. 3.13.2 shows 2 to 4 explain. an
decoder. Here, 2 inputs are
decoded into four
outputs, eachoutput representing Sol. Fig. 3.13.3 shows 3 to 8 line decoder. Hero
one of the
minterms of the 2
inverters provide the input variables. The two inputs are decoded into eight outputs, each
outmue
each one of four AND
complement of the
inputs, and represent one of the minterms of the 3
in.
minterms.
gates generates one of the variables. The three inverters nput
provide the
complement of the inputs, and each one of
the eight-
AND gates generates one of the
A B minterms. Enable
input is
provided to activate decoded
on data inputs A, B, and C. The table
output based
truth table for 3 to 8 shows the
decoder.
B

D- A
C

D--Y,=AB
D- Y2=AB

Enable (EN)
- Y =AB -Y =
-Y, =ABc
Fig. 3.13.2 2 to 4
line decoder
The Table 3.13.1 -Y=
decoder. As shownshows the truth table
in the truth for a 2 to 4
is 1
(EN =1), one, and table, if enable -Y =
Ya is active for a only one, of the outputs input
active, i.e. Yo=1 whengiven input. The output Y is
to
-Y4 =ABT
Y, is active when inputs A =B =0, the Y
input is 0, i.e. EN
inputs A =
0 and B 1. If output -Y5 =ABC
=
0, then all the enable
outputs are 0.
Inputs Y =ABT
Outputs
EN BY,Y,|Y% Y7 ABC
o xxoo Enable (EN)
0

Fig. 3.13.3 3 : 8 line decoder

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 DIS
1 1
Inputs Outputs 001 0 o 0 1 111
1
EN A B cY,YYs Y,YY,Y 0 1 o o 1 1 11 1 1 |
1 1 1|1 1|1
xxxo o o oo o 001o 101 11 1
0 0 0 1 1 11|11
o 0 0 | 0 0 0 oo U
1 1 11
1 0 0 00 0 0 0 1 oo 1
0
0 01 10 1 1 1111|1
o 1 0 0 0 0 0 1 1 1 1|1 1
1 1 11 11 1
1 0 1 1
0 o o 0 0
0 1 11 1
Function table
11 0 o o o 0 Table 3.13.3
0 0
Decoder
101o 0 0 0 3.13.3 The 74X139 Dual 2 to 4
and identical
1 The 74X139 consists of two independent
2-to-4 decoders. The enable inputs and outputs of IC
1111 0 0 74X139 are active low. Fig. 3.13.4 shows the logic

Table 3.13.2 Truth table for

symbol and Table 3.13.3 shows the function table for
a 3 to 8 decoder IC 74X139. The Table 4.16.4 shows the truth table for
one half of a 74X139 dual 2-to-4 decoder. The truth
3.13.2 The 74X138 3-to-8 Decoder table for other half is same as first half.
The 74X138 is a
commercially available 3-to-8
decoder. It accepts three binary inputs (A, B, C) and Inputs Outputs
when enabled, provides eight individual active low
outputs (Yo Y,). The device has three enable inputs: 1
two active low (G2A, G2B) and one active
high (G). 1 1
Fig. 3.13.4 and Table 3.13.3 show logic symbol and
0
function table respectively.
0

74X138 0

Yo15) Table 3.13.4 Truth table for half of

one a 74X139
Y14)
2) 74X139
3 Y213)
(1) 1G
(3)C (12) (2)
1Y4

Y11)
1A
1Y (5)
1B 1Y26)
s (10) 1Y 7
(9)
(5) G2B (15)
Y (7) 2G
(14)2A 2Y12)

Fig. 3.13.4 Logic symbol (13)28 2Y (11)

2Y,(10)
2
2Y 9 ) 2

Inputs Outputs
Fig. 3.13.5 Logic symbol for IC 74X139
S2G2 clBa Ys o 3.13.4 Expanding Cascading Decoders
xx. 1 1 1 111
xx x11 Binary decoder circuits can be connected together to
X1xxxx1111111 form a larger decoder circuit. Fig. 3.13.6 shows the 4 x

Xx o xxx| 1 1 1 1 1 1 11 16 decoder using two 3 x 8 decoders.

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 a DiectroniCS Q t De

Here, one input line (D) is used to

enable/disable the decoders. When
D 0, the top decoder is enabled Yo
and the other is disabled. Thus the -0
bottom decoder outputs are all 1s,
D -O2 Y2
A
and the top eight outputs generate 3: -Og 3:8
minterms 0 000 to 0 1 1 1. When
Decoder -O4 Decoder
D=1 the enable conditions are
On
reversed and thus bottom decoder
EN
outputs generate minterms 1000 to
1111, while the outputs of the top
p-O15
Fig. 3.13.6
decoder are all 1s.

Ex. 3.13.2 Design 5-to-32 decoder using one 2-to-4 and four 3-to-8 decoder ICs.
AU: Dec.-17, Marks 6
Sol.

74L3138(1
Yo

G
G2A
G3B

74LS138(2)
1/2 74LS139
EN 1Y
Y1 Y10
D -
A Y11
Y12
Y13
G2A

74LS138(3)
- 16

-Y17
18
19
Y20
Y21
GaA Y2
G28 Y23
74LS138(4)
-Y Y24
-Y25
26
27
EN 28
29
G2A 30
Fig. 3.13.7 5-to-32 G28 Y31
decoder using
74LS138 and 74LS139
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 Combinauo

74LS139. The
half
3 43 and
7 4 L S 1 3 8 s

D and E.
D i g i t a lE l e c t r o n i c s
four
o r d e r inputs,
decoder 1sing higher lower
the of 5-to-32
construction
the t w o The three
3.13.7 shows
The Fig. 3.13. decode decoders.
d e c o d e r to
is used as a 2-to-4 3 to 8 the s a m e
s e c t i o n of 74LS139 IC of the four ns that mean

half enable o n e This

this dec a r e u s e d to The remaining enable
outputs of
decoders.

The four four 3 to 8

A, B and C are connected in parallelto
enabled.

o n e is for 5-
5-to-32
order inputs signals
four 3-to-8 decoders is selected but only enable

output pin
each
of of the parallel
to
c o n s t r u c t

connected in
off
signals o four 3-to-8 decoder ICs are

decoder.
Decoder or multiple
zation of Boolean Function using single
to implement
3.13.5 Realizat
be used active low or
can either
The combination
of decoder and external logic gates
two output
states;
runcuOn.
of the
output
functions. We know that decoder can have one

in the
implementation of binary
these output states
Let us see the significance of variables; 1e. t
acthve hign.
for input
minterms (product terms) or selectea
sum
output is active high, it
generates
When decoder have to take
function we
implement SOP
makes selected output logic 1. In such c a s e to
terms generated by decoder.
product

Examples for Understanding

Ex. 3.13.3 Implement Boolean function F =

m (1, 2,
B
3, 7) using 3:8 decoder. C

Sol 3:8
oder
3 D -F
Step 1 Connect function variables as e
inputs to the decoder.

EN
Logically OR the outputs
Step 2 minterms
correspond to present Fig. 3.13.8
to obtain the output.

output
Ex. 3.13.4 Implement the. following multiple
to 16 line decoder.
combinational logic using a 4 line

Y=ABCD+ABCD+A BCD+ ABCD -Y

+ABCD+ ABCD
D+ AB D
Y2 =ABC D+ BC D+A B
Y=A BC D+ ABC D+ ABCD. Og
O6
O7
Sol.
Write the function in their
c 4:16
Decoder Os
Og
D
Step 1:
minterm forms O10
O11
10, 11)
Y3
O12
Y 2m (0, 3, 2, 6, O13
(1, 4 5, 13) O14
Y2 m O15
Y3-m (7, 14, 15)
outputs of
OR the Fig. 3.13.9
Step 2: Logically the
to
decoder corresponding
functions.
minterms in the

PUBLICATIONS An up thrust for knowiedge

TECHNICAL
 16-line dero
Examples with Solutlons circuit using a 4-line to
decoder.
combinational logic
Ex. 3.13.5 Implement the following multiple output
3, 9, 11) AU : Dec,-08, M
2m (1, 2, 4, 7, 8, 11, 12, 13), 2 2m(2,
8)
J3 m(10, 12, 13, 14), f - 2m (2, 4,
Sol.:

Inputs

4:16
Decoder D
Y10
Y11
Y12
Y13
EN Y14

Fig. 3.13.10
Ex. 3.13.6
Design and implement a full adder circuit **********

using a 3:8 decoder. AU May-11, Mark

Sol.: Truth table for full
adder is as
shown in the Table 3.13.5.
Outputs
Carry Sum
0 0
0
Yo
A A
B 3:8
B Decoder
Cin C
1
0

10
Table 3.13.5 Truth table
for full-adder
Ex. 3.13.7 Design excess-3
an to BCD code Fig. 3.13.11
converter using decoder
and gates.

T
TECHNICAL
PUBLICATIONS An up thrust
for knowiedna
 CSS-S to
BCD
a l . : 1 h e

coc
e
converter is as shown
B2 in the Table 3.15.0.
10 Realization
0 11 0 0
10 0 0
1
Yo
0 1 0

0 0
Bo
Ya
0
Eg A Ys B1
0 Excess-3
COde
E2- Y6
E C
Y7 - B2
0 1 0 4:16
Eo D
Decoder
00 1 40
0 0
Yn
YA2
Y44
Table 3.13.6
Fig. 3.13.12
Examples for Practice
Ex. 3.13.8 Implement the following Boolean functions using decoder and OR
FiA,B,C,D) 2 (24,7,9)
=
gates:
F2 (A,B,CD) 2 (10,13,14,15)
=

Ex. 3.13.9 Implement the logic circuit for full subtractor using decoder.
3.13.6 Applications of Decoder
The uses of decoders are
Code converterIS

Implementation of combinational circuits

Address decodirng
BCD to 7-segment decoder
3.13.7 Decoder 1 C