INSTITUTE OF AERONAUTICAL ENGINEERING

(Autonomous)
Dundigal, Hyderabad -500 043

ELECTRONICS AND COMMUNICATION ENGINEERING

Course Title ELECTRONIC DEVICES AND CIRCUITS

Course Code AECB06

Program B. Tech

Semester THREE

Course Type Core

Regulation IARE - R18

Theory Practical

Course Structure Lectures Tutorials Credits Laboratory Credits

3 1 4 3 1.5

Course Coordinator Mr. D Khalandar Basha, Assistant Professor

COURSE OBJECTIVES:

The students will try to learn:

I The operational principles, characteristics of semiconductor devices and circuitsfor
rectification, amplification, conditioning and voltage regularization of signals.
II The analytical skills needed to model analog and digital integrated circuits (IC) at discrete
and micro circuit level
The foundations of basic electronic circuits necessary for building complex electronic
III
hardware.
IV Familiarize the students with circuit simulation techniques

COURSE OUTCOMES:
After successful completion of the course, students will be able to:
Knowledge Level
Course Outcomes (Bloom’s
Taxonomy)
CO 1 Summarize the semiconductor device properties using energy band Understand
diagrams.
1
CO 2 Illustrate the volt-ampere characteristics of pn junction diode for Understand
finding cut-in voltage, static and dynamic resistances.
CO 3 Apply the pn junction characteristics for the diode applications such as Apply
switch, clippers, clampers and rectifiers.
CO 4 Demonstrate the constructional features and principle of operation of Understand
bipolar and uni-polar devices for distinguishing between cut off, active
and saturation regions of operation.
CO 5 Establish the relations of current gain, voltage gain of bipolar junction Understand
transistor and field effect transistor respectively using their
characteristics
CO 6 Analyse the input and output characteristics of transistor Analyze
configurations for determining the input - output resistances, current
gain and voltage gain.
CO 7 Estimate the characteristic parameters of BJT, FET amplifier Evaluate
circuitsusing low frequency model.
CO 8 Examine DC and AC load line analysis of BJT and FET amplifiers for Analyze
optimal operating level regardless of input, load placed on the device.
CO 9 Design the various biasing techniques for BJT, JFET and MOSFETs Apply
amplifier circuits considering stability condition for establishing a
proper operating point.
CO 10 Compute the characteristic parameters of FET and MOSFETs in Apply
common source, common drain and common gate amplifiers using the
drain and the transfer characteristics.
CO 11 Demonstrate the working principle of special purpose semiconductor Understand
diodes and transistors for triggering and voltage regulation applications.
CO 12 Design basic electronic circuits using active transistors Create

CO 13 Apply electronic circuits in global engineering applications Apply

2
SYLLABUS:

MODULE -I DIODE AND APPLICATIONS Classes: 08

Diode - Static and Dynamic resistances, Equivalent circuit, Load line analysis, Diffusion and
Transition Capacitances, Diode Applications: Switch-Switching times. Rectifier - Half Wave
Rectifier, Full Wave Rectifier, Bridge Rectifier, Rectifiers With Capacitive Filter, Clippers-
Clipping at two independent levels, Clampers-Clamping Operation, types, Clamping Circuit
Theorem, Comparators.
MODULE - II BIPOLAR JUNCTION TRANSISTOR (BJT) Classes: 10
Principle of Operation and characteristics - Common Emitter, Common Base, Common Collector
Configurations, Operating point, DC & AC load lines, Transistor Hybrid parameter model,
Determination of h-parameters from transistor characteristics, Conversion of h-parameters.

MODULE - III TRANSISTOR BIASING AND STABILIZATION Classes: 10

Bias Stability, Fixed Bias, Collector to Base bias, Self Bias, Bias Compensation using Diodes and
Transistors.
Analysis and Design of Small Signal Low Frequency BJT Amplifiers: Analysis of CE, CC, CB
Amplifiers and CE Amplifier with emitter resistance, low frequency response of BJT Amplifiers,
effect of coupling and bypass capacitors on CE Amplifier.
MODULE - IV JUNCTION FIELD EFFECT TRANSISTOR Classes: 08
Construction, Principle of Operation, Pinch-Off Voltage, Volt- Ampere Characteristic, comparison
of BJT and FET, Biasing of FET, FET as Voltage Variable Resistor, MOSFET Construction and its
Characteristics in Enhancement and Depletion modes.
MODULE - V FET AMPLIFIERS Classes: 09
Small Signal Model, Analysis of CS, CD, CG JFET Amplifiers. Basic Concepts of MOSFET
Amplifiers.
Special Purpose Devices: Zener Diode - Characteristics, Voltage Regulator; Principle of
Operation - SCR, Tunnel diode, UJT, Varactor Diode.
Text Books:
1. Electronic Devices and Circuits - Jacob Millman, McGraw HillEducation.
2. Electronic Devices and Circuits theory– Robert L. Boylestead, Louis Nashelsky, 11th Edition,
Pearson, 2009.
Reference Books:
3. The Art of Electrionics , Horowitz, 3rdEdition Cambridge University Press,2018
4. Electronic Devices and Circuits, David A. Bell – 5th Edition,Oxford.
5. Pulse, Digital and Switching Waveforms –J. Millman, H. Taub and Mothiki S. Prakash Rao, 2
Ed., McGraw Hill,2008.
6. Electronic Devices and Circuits, S. Salivahanan, [Link] Kumar, AVallvaraj, 2nd
Edition,TMH.

3
 MODULE –I
DIODE AND APPLICATIONS

Diode - Static and Dynamic resistances, Equivalent circuit, Load line analysis, Diffusion and
Transition Capacitances, Diode Applications: Switch-Switching times. Rectifier - Half Wave
Rectifier, Full Wave Rectifier, Bridge Rectifier, Rectifiers With Capacitive Filter, Clippers-Clipping
at two independent levels, Clampers-Clamping Operation, types, Clamping Circuit Theorem,
Comparators.

COURSE OUTCOMES (COs):

After successful completion of the course, students will be able to:

CO No Course Outcomes Knowledge Level
(Bloom’s Taxonomy)
CO 1 Summarize the semiconductor device properties using energy band Understand
diagrams.
CO 2 Illustrate the volt-ampere characteristics of pn junction diode for Understand
finding cut-in voltage, static and dynamic resistances.
CO 3 Apply the pn junction characteristics for the diode applications such Apply
as switch, clippers, clampers and rectifiers.
CO 13 Apply electronic circuits in global engineering applications Apply

IDEAL VERSUS PRACTICAL RESISTANCE LEVELS

DC or Static Resistance
It is defined as the ratio of the voltage to the current, V/I, in the forward bias characteristics of the PN
junction diode. In the forward bias characteristics of the diode as shown in Fig. 1, the d.c. or static
resistance (RF) at the operating point can be determined by using the corresponding levels of voltage V
and current I, i.e. Rf = . Here, the D.C. resistance is independent of the shape of the characteristics in the

region surrounding the point of interest. The D.C. resistance levels at the knee and below will be greater
than the resistance levels obtained for the characteristics above the knee. Hence, the D.C. resistance will
be low when the diode current is high. As the static resistance varies widely with V and I.

4
 Figure 1. Determining the dc resistance of a diode at a particular operating point.

AC or Dynamic Resistance
It is defined as the reciprocal of the slope of the volt-ampere characteristics.

rf =

A straight line drawn tangent to the curve through the Quiescent Point (Q-point) as shown in Fig. 2 will
define a specific change in voltage and current which may be used to determine the a.c. or dynamic
resistance for this region of the diode characteristics. As shown in Fig. 3, for a small change in voltage,
there will be a corresponding change in current, which is equidistant to either side of the Q-point. Hence,

the a.c. or dynamic resistance is determined as rf = . The derivative of a function at a point is equal to

the slope of the tangent line drawn at the point. The Schockley‟s equation for the forward and reverse bias
regions is defined by
I = Io (e V/ꞑVT – 1)

Fig.2 Dynamic Resistance Fig.3 calculation of Dynamic Resistance from graph

Taking the derivative of the above equation w.r.t. the applied voltage, V, we get
5
 =

Generally I >> Io in the vertical-slope section of the characteristics. Therefore,

DIODE EQUIVALENT CIRCUITS

An equivalent circuit is a combination of elements properly chosen to best represent the actual
terminal characteristics of a device, system, or such in a particular operating region. In other words, once
the equivalent circuit is defined, the device symbol can be removed from a schematic and the equivalent
circuit inserted in its place without severely affecting the actual behavior of the system. The result is often
a network that can be solved using traditional circuit analysis techniques.

Piecewise-Linear Equivalent Circuit

As the volt–ampere relationship of the diode is non-linear, the analysis of circuits containing diodes is
difficult. With the help of piecewise linear approximation model of the diode, the results can easily be
obtained. The particular regions of operation of the volt–ampere characteristics of the diode are broken
into linear segments and the concept of a diode cut-in voltage is also used in this piecewise linear model.
If the reverse resistance Rr is included in the diode characteristics, then the piecewise linear and
continuous volt–ampere characteristic is obtained. Piecewise linear model is used when a more accurate
model than ideal-diode model is needed but not resorted to nonlinear equation or graphical technique. The
piecewise linear model for diode is obtained by using following steps:
1. Approximate the actual V–I characteristics by straight-line segments.
2. Model each section (forward and reverse characteristics) with a resistance in series with a constant
voltage source.
The simple piecewise linear equivalent for the diode is shown in Fig. 4

6
 Fig.4 characteristics of Piecewise linear model

Since the diode is a binary device, it can exist in only one of two possible states, i.e., the diode is either in
ON or OFF state at a given time. If the voltage applied across the diode exceeds the cut-in voltage, Vg,
the diode is forward biased and is said to be in ON state with diode forward resistance Rf. For a reverse
bias, the diode is open circuited and is said to be in OFF state with infinitely large reverse resistance Rr.
The piecewise linear model is used for analysis of the diode circuits. Consider a circuit containing several
diodes, resistors and power supplies. This type of circuit is analyzed by assuming the state of the diode.
For ON state, the diode is replaced with Rf value and for the OFF state, the diode is replaced with Rr
value. After replacing the diode with this piecewise model, the entire circuit is linear and now by using
Kirchhoff‟s voltage and current laws, the entire current and voltage in the circuit and be calculated. The
assumption that a diode is ON can be verified by observing the sign of the current through it. If the
current is in forward direction, then the assumption of the diode is justified.

DIFFUSION CAPACITANCE

The capacitance that exists in a forward biased junction is called a diffusion or storage capacitance (CD),
whose value is usually much larger than CT, which exists in a reverse-biased junction. This is also defined
as the rate of change of injected charge with applied voltage, i.e., CD = dQ/dV, where dQ represents the
change in the number of minority carriers stored outside the depletion region when a change in voltage
across the diode, dV, is applied.
Diffusion capacitance CD increases exponentially with forward bias or, alternatively, that it is proportional
to diode forward current, I. The values of CD range from 10 to 1000 pF, the larger values being associated
with the diode carrying a larger anode current, I. The effect of CD is negligible for a reverse-biased PN
junction. As the value of CD is inversely proportional to frequency, it is high at low frequencies and it

7
decreases with the increase in frequency.

TRANSITION CAPACITANCE

The amount of capacitance changed with increase in voltage is called transition capacitance. The
transition capacitance is also known as depletion region capacitance, junction capacitance or barrier
capacitance.

The change of capacitance at the depletion region can be defined as the change in electric charge per
change in voltage.

CT = dQ / dV
Where,

CT= Transition capacitance

dQ = Change in electric charge

dV = Change in voltage

The transition capacitance can be mathematically written as,

CT = ε A / W
Where,
ε = Permittivity of the semiconductor
A = Area of plates or p-type and n-type regions
W = Width of the depletion region

RECTIFIER:
All electronic devices require carrier movement caused by discrete positive and negative potentials. Also,
D.C. is used as the supply voltage for most amplifiers and electronic gadgets. These D.C. sources may be
battery for portable equipment but are very expensive for heavy use, and involve other problems like
leakage and periodic charging. An alternative is to convert the cheaply available A.C. from power lines to
D.C. and such converters are called rectifiers. The principle of operation essentially is to convert A.C. into
unidirectional voltages and currents using polarity sensitive switches, that is, diodes, and others.

Characteristics of a Rectifier Circuit:

Any electrical device which offers a low resistance to the current in one direction but a high resistance to
the current in the opposite direction is called rectifier. Such a device is capable of converting a sinusoidal
input waveform, whose average value is zero, into a unidirectional waveform, with a non-zero average
component.

8
A rectifier is a device, which converts a.c. voltage (bi-directional) to pulsating d.c. Load currents: They
are two types of output current. They are average or d.c. current and RMS currents.

Average or DC current: The average current of a periodic function is defined as the area of one cycle of
the curve divided by the base.
It is expressed mathematically as
Average value/dc value/mean value =

Effective (or) R.M.S current:

The effective (or) R.M.S. current squared ofa periodic function of time is given by the area of one cycle
of the curve, which represents the square of the function divided by the base.

Peak factor:
It is the ratio of peak value to rms value
Peak factor =

Form factor:

It is the ratio of Rms value to average value

Form factor=

Ripple Factor (  ):
It is defined as ration of R.M.S. value of a.c. component to the d.c. component in the output is known as
“Ripple Factor”.

Efficiency ( ):
It is the ratio of d.c output power to the a.c. input power. It signifies, how efficiently the rectifier circuit
converts a.c. power into d.c. power.

9
Peak Inverse Voltage (PIV):
It is defined as the maximum reverse voltage that a diode can withstand without destroying the junction.

Transformer Utilization Factor (UTF):

The D.C. power to be delivered to the load in a rectifier circuit decides the rating of the transformer used
in the circuit. So, transformer utilization factor is defined as

% Regulation:
The variation of the D.C. output voltage as a function of D.C. load current is called regulation. The
percentage regulation is defined as

For an ideal power supply, % Regulation is zero.

CLASSIFICATION OF RECTIFIERS:
Using one or more diodes in the circuit, following rectifier circuits can be designed.
1) Half - Wave Rectifier
2) Full – Wave Rectifier
3) Bridge Rectifier

HALF-WAVE RECTIFIER:
The half-wave rectifier circuit has a step down transformer, a semiconductor diode, a variable load
resistor RL as connected in the Fig.5.

Fig.5 Basic structure of HWR and its waveforms

10
The a.c. voltage is applied to the rectifier circuit using step-down transformer-rectifying element i.e., p-n
junction diode and the source of a.c. voltage, all connected is series.
The input to the rectifier circuit, V=Vm sin (wt)
Where Vm is the peak value of secondary a.c. voltage.
Operation:
For the positive half-cycle of input a.c. voltage, the diode D is forward biased and hence it conducts. Now
a current flows in the circuit and there is a voltage drop across RL. The waveform of the diode current
(or) load current is shown in fig [Link] the negative half-cycle of input, the diode D is reverse biased and
hence it does notconduct. Now no current flows in the circuit i.e., i=0 and VO=0. Thus for the negative
half- cycle no power is delivered to the load.
Analysis:
In the analysis of a HWR, the following parameters are to be analyzed.
1. DC output current
2. DC Output voltage
3. R.M.S. Current
4. R.M.S. voltage
5. Rectifier Efficiency (η )
6. Ripple factor (γ )
7. Peak Factor
8. % Regulation
9. Transformer Utilization Factor (TUF)
10. form factor
11. o/p frequency

Let a sinusoidal voltage Vi be applied to the input of the rectifier. Then V=Vm sin (wt) Where Vm is the
maximum value of the secondary voltage. Let the diode be idealized to piece-wise linear approximation
with resistance Rf in the forward direction i.e., in the ON state and Rr (=∞) in the reverse direction i.e., in
the OFF state. Now the current „i‟ in the diode (or) in the load resistance RL is given by V=Vm sin (wt)

Average voltage

11
 =

Average current
IDC=

RMS voltage:

RMS current: Irms

Peak factor

Peak factor = =2

Form factor

Form factor= =1.57

Ripple Factor:

= 1.21

Efficiency ( ):It is the ratio of d.c output power to the a.c. input power. It signifies, how efficiently the

12
rectifier circuit converts a.c. power into d.c. power.

= 40.8

Transformer Utilization Factor (TUF):

The d.c. power to be delivered to the load in a rectifier circuit decides the rating of the transformer used in
the circuit. Therefore, transformer utilization factor is defined as

TUF =0.286.
The value of TUF is low which shows that in half-wave circuit, the transformer is not fully utilized.
If the transformer rating is 1 KVA (1000VA) then the half-wave rectifier can deliver1000 X 0.287 = 287
watts to resistance load.

Peak Inverse Voltage (PIV):

It is defined as the maximum reverse voltage that a diode can withstand without destroying the junction.
The peak inverse voltage across a diode is the peak of the negative half- cycle. For half-wave rectifier,
PIV is Vm.

Disadvantages of half-wave rectifier:

1. The ripple factor is high.
2. The efficiency is low.
3. The Transformer Utilization factor is low.
Because of all these disadvantages, the half-wave rectifier circuit is normally not used as a Power rectifier
circuit.

FULL WAVE RECTIFIER:

The full wave rectifier circuit consists of a mains transformer, two semiconductor diodes D1 and D2, load
resistance Rl as connected in the Fig. 6. The secondary winding of the transformer has a center-tap and
the two voltages VS1 and VS2 are 180° out of phase and equal in magnitude. During the interval 0 to p of
13
the secondary input voltages VS1 and VS2; semiconductor diode D1 is forward biased, If flows through
Rl and hence develops output voltage Vout = If x Rl. At the same time semiconductor diode D2 is reverse
biased.

The polarities of the voltages across the secondary winding are such that semiconductor diode D2 is
forward biased and D1 is reverse biased. If2 flows through Rl and develops voltage Vout across the load
resistance, Rl. Vout = If 2 x Rl. Since the semiconductor diode D1 is reverse biased, the reverse current Ir 1
flows through Rl.

During positive half of the input signal, anode of diode D1 becomes positive and at the same time the
anode of diode D2 becomes negative. Hence D1 conducts and D2 does not conduct. The load current
flows through D1 and the voltage drop across RL will be equal to the input voltage.

Fig. 6 Full Wave Rectifier circuit and its input, output wave forms.

During the negative half cycle of the input, the anode of D1 becomes negative and the anode of D2
becomes positive. Hence, D1 does not conduct and D2 conducts. The load current flows through D2 and
the voltage drop across RL will be equal to the input voltage. It is noted that the load current flows in the
both the half cycles of ac voltage and in the same direction through the load resistance.

Averagevoltage:
The average voltage across the load resistance is

14
If the diode forward resistance and the transformer secondary winding resistance are included in the
analysis, then

RMS vale of the voltage at the load resistance is

-1

= 0.482

RMS Voltage:

RMS Current:

Peak Factor: Peak factor = =2

15
Form Factor= =1.11

Ripple Factor:

= 1.21

Efficiency ( ):It is the ratio of d.c output power to the a.c. input power. It signifies, how efficiently the
rectifier circuit converts a.c. power into d.c. power.

Substitute and we will get

= 81.2

Peak Inverse Voltage (PIV):

It is defined as the maximum reverse voltage that a diode can withstand without destroying the junction.
The peak inverse voltage across a diode is the peak of the negative half- cycle. For half- wave rectifier,
PIV is 2Vm

Advantages
1) Ripple factor = 0.482 (against 1.21 for HWR)
2) Rectification efficiency is 0.812 (against 0.405 for HWR)
3) Better TUF (secondary) is 0.574 (0.287 for HWR)
4) No core saturation problem
16
Disadvantages:
1) Requires center tapped transformer.

BRIDGE RECTIFIER:
Another type of circuit that produces the same output waveform as the full wave rectifier circuit above, is
that of the Full Wave Bridge Rectifier. This type of single phase rectifier uses four individual rectifying
diodes connected in a closed loop "bridge" configuration to produce the desired output. The main
advantage of this bridge circuit is that it does not require a special center tapped transformer, thereby
reducing its size and cost. The single secondary winding is connected to one side of the diode bridge
network and the load to the other side as shown below.

Fig. 7 Bridge rectifier and its input, output waveforms

The four diodes labeled D1 to D4 are arranged in "series pairs" with only two diodes conducting current
during each half cycle. During the positive half cycle of the supply, diodes D1 and D2 conduct in series
while diodes D3 and D4 are reverse biased and the current flows through the load as shown fig. 7. As the
current flowing through the load is unidirectional, so the voltage developed across the load is also
unidirectional the same as for the previous two diode full-wave rectifier, therefore the average DC voltage
across the load is 0.637Vmax. However in reality, during each half cycle the current flows through two
diodes instead of just one so the amplitude of the output voltage is two voltage drops ( 2 x 0.7 = 1.4V )
less than the input VMAX amplitude. The ripple frequency is now twice the supply frequency (e.g. 100Hz
for a 50Hz supply).

FILTERS

The output of a rectifier contains dc component as well as ac component. Filters are used to minimize the
undesirable ac i.e., ripple leaving only the dc component to appear at the output.
17
Some important filters are:
Inductor filter
1. Capacitor filter

2. LC or L section filter

3. CLC or Π-type filter

CAPACITOR FILTER

This is the simplest form of the filter circuit and in this arrangement a high value capacitor C is placed
directly across the output terminals, as shown in figure. During the conduction period it gets charged and
stores up energy to it during non-conduction period. Through this process, the time duration during which
Ft is to be noted here that the capacitor C gets charged to the peak because there is no resistance (except
the negligible forward resistance of diode) in the charging path. But the discharging time is quite large
(roughly 100 times more than the charging time depending upon the value of RL) because it discharges
through load resistance RL.

The function of the capacitor filter may be viewed in terms of impedances. The large value capacitor C
offers a low impedance shunt path to the ac components or ripples but offers high impedance to the dc
component. Thus ripples get bypassed through capacitor C and only dc component flows through the load
resistance RL

Capacitor filter is very popular because of its low cost, small size, light weight and good characteristics.

Fig. 8 Capacitor filter with FWR

Clippers:
Shunt Clippers
Clipping above referencelevel
18
Using the ideal diode characteristic of Fig. 9(a), the clipping circuit shown in Fig. 9(b), has the transmission
characteristic shown in Fig. 9(c).
The transmission characteristic which is a plot of the output voltage v0as a function of the input voltage v,
also exhibits piece-wise linear discontinuity. The break point occurs at the reference voltage VR. To the left
of the break point i.e. for vt< VRthe diode is reverse biased (OFF) and the equivalent circuit shown in Fig.
9(d) results. In this region the signal v, may be transmitted directly to the output, since there is no load
across the output to cause a drop across the series resistor.
To the right of the break point i.e. for vo> VR the diode is forward biased (ON) and the equivalent circuit
shown in Fig. 9(e) results and increments in the inputs are totally attenuated and the output is fixed at V R.
Fig. 9(c) shows a sinusoidal input signal of amplitude large enough so that the signal makes excursions past
the break point.
The corresponding output exhibits a suppression of the positive peak of the signal. The output will appear as
if the positive peak had been clipped off or sliced off.

Clipping below reference level

If this clipping circuit of Fig. 9(b), is modified by reversing the diode as shown in Fig. 10(a), the
corresponding piece-wise linear transfer characteristic and the output for asinusoidal input will be as shown
in Fig. 10(b).
In this circuit, the portion of the waveform more positive than VR is transmitted without any attenuation but
the portion of the waveform less positive than VR is totally suppressed.
For Vj< VR, the diode conducts and acts as a short circuit and the equivalent circuit shown in Fig. 10(c)
results and the output is fixed at VR. For vi> VR, the diode is reverse biased and acts as an open circuit and
the equivalent circuit shown in Fig. 10(d) results and the output is the same as the input.

19
 Fig .9 (a) v-i characteristic of an ideal diode, (b) diode clipping circuit, which removes that part of the
waveform that is more positive than VR, (c) the piece-wise linear transmission characteristic of the circuit,
a sinusoidal input and the clipped output, (d) equivalent circuit for v(< VR, and (e) equivalent circuit for v,
> V R.

Fig. 10(a) A diode clipping circuit, which transmits that part of the sine wave that is more positive than
VR, (b) the piece-wise linear transmission characteristic, a sinusoidal input and the clipped output, (c)
equivalent circuit for v(< VR, and (d) equivalent circuit for v,- > VR.

CLAMPING CIRCUITS
Clamping circuits are circuits, which are used to clamp or fix the extremity of a periodic waveform to
some constant reference level V.R. Under steady-state conditions, these circuits restrain the extremity of the
waveform from going beyond VR. Clamping circuits may be one- way clamps or two-way clamps. When
only one diode is used and a voltage change in only one direction is restrained, the circuits are called one-
way clamps. When two diodes are used and the voltage change in both the directions is restrained, the
circuits are called two-way clamps.

The Clamping Operation

When a signal is transmitted through a capacitive coupling network (RC high-pass circuit), it loses its dc
component, and a clamping circuit may be used to introduce a dc component by fixing the positive or
negative extremity of that waveform to some referencelevel. For this reason, the clamping circuit is often
referred to as dc restorer or dc reinserter.
In fact, it should be called a dc inserter, because the dc component introduced may be different from the dc
component lost during transmission. The clamping circuit only changes the dc level of the input signal. It

20
does not affect its shape.

Negative Clamper
Fig.11 (a) shows the circuit diagram of a basic negative clamper. It is also termed a positive peak clamper
since the circuit clamps the positive peak of a signal to zero level.
Assume that the signal source has negligible output impedance and that the diode" is ideal, Rf= 0 n and Vy
= 0 V in that, it exhibits an arbitrarily sharp break at 0 V, and that its input signal shown in Fig.11(b) is a
sinusoid which begins at t = 0. Let the capacitor C be unchanged at t = 0.
During the first quarter cycle, the input signal rises from zero to the maximum value. The diode conducts
during this time and since we have assumed an ideal diode, the voltage across it is zero.
The capacitor C is charged through the series combination of the signal source and the diode and the
voltage across C rises sinusoidally.
At -the end of the first quarter cycle, the voltage across the capacitor, vc = [Link], after the first quarter
cycle, the peak has been passed and the input signal begins to fall, the voltage vcacross the capacitor is no
longer able to follow the input, because there is no path for the capacitor to discharge.
Hence, the voltage across the capacitor remains constant at vc = Vm, and the charged capacitor acts as a
voltage source of V.

Fig.11 (a) A negative clamping circuit, (b) a sinusoidal input, and (c) a steady-state clamped
output.

21
Positive Clamper
Fig. 12(a) shows a positive clamper. This is also termed as negative peak clamper since this circuit clamps
the negative peaks of a signal to zero level. The negative peak clamper, i.e. the positive clamper introduces
a positive dc.

Fig. 12: positive clamper

Let the input voltage be vi = Vmsinwt. When v, goes negative, the diode gets forward biased and conducts
and in a few cycles the capacitor gets charged to Vmwith the polarity shown in Figure 2.73(a). Under
steady-state conditions, the capacitor acts as a
Constant voltage source and the output is V0 = Vi - (-Vm)=Vi+Vm
Based on the above relation between v0and v,, the output voltage waveform is plotted. As seen in Figure
2.73(c) the negative peaks of the input signal are clamped to zero level. Peak-to- peak value of output
voltage = peak-to-peak value of input voltage = 2Vm. There is no distortion of waveform.

Clamping Circuit Theorem

Under steady-state conditions, for any input waveform, the shape of the outputwaveform of a clamping
circuit is fixed and also the area in the forward direction (when the diode conducts) and the area in the
reverse direction (when the diode does not conduct) arerelated.

22
The clamping circuit theorem states that, for any input waveform under steady-state conditions, the
ratio of the area Af under the output voltage curve in the forward direction to that in the reverse
direction Ar is equal to the ratio Rf/Rr.
In the time interval t1 to t2, D is ON. Hence, during this period, the charge builds up on the capacitor C.
If if is the diode current, the charge gained by the capacitor during the interval t1 to t2 is:

However, if = Vf/Rf, where Vf is the diode forward voltage:

During the interval t2 to t3, D is OFF. Hence, the capacitor discharges and the charge lost by C is:

Let q1=q2

Comparators
An amplitude comparator is a circuit that tells the time instant at which the input amplitude has reached a
reference level.
vo = 0 for t < t1
vo = V for t ≥ t1
The distinction between comparator circuits and the clipping circuits is that, in a comparator there is no
interest in reproducing any part of the signal waveform, whereas in a clipping circuit, part of the signal
waveform is needed to be reproduced without any distortion.

23
 Fig. 13. Diode Comparator
Comparators may be non-regenerative or regenerative.
Clipping circuits are non-regenerative comparators.
Schmitt trigger and oscillators are regenerative comparators.

24
 MODULE – II
BIPOLAR JUNCTION TRANSISTOR (BJT)

Principle of Operation and characteristics - Common Emitter, Common Base, Common Collector
Configurations, Operating point, DC & AC load lines, Transistor Hybrid parameter model,
Determination of h-parameters from transistor characteristics, Conversion of h-parameters.

COURSE OUTCOMES (COs):

After successful completion of the course, students will be able to:

CO No Course Outcomes Knowledge Level
(Bloom’s Taxonomy)
CO 4 Demonstrate the constructional features and principle of operation Understand
of bipolar and uni-polar devices for distinguishing between cut off,
active and saturation regions of operation.
CO 5 Establish the relations of current gain, voltage gain of bipolar Understand
junction transistor and field effect transistor respectively using their
characteristics
CO 6 Analyse the input and output characteristics of transistor Analyze
configurations for determining the input - output resistances, current
gain and voltage gain.
CO 8 Examine DC and AC load line analysis of BJT and FET amplifiers Analyze
for optimal operating level regardless of input, load placed on the
device.
CO 9 Design the various biasing techniques for BJT, JFET and MOSFETs Apply
amplifier circuits considering stability condition for establishing a
proper operating point.
CO 12 Design basic electronic circuits using active transistors Create
CO 13 Apply electronic circuits in global engineering applications Apply

Introduction

A bipolar junction transistor (BJT) is a three terminal device in which operation depends on the
interaction of both majority and minority carriers and hence the name bipolar. The BJT is analogues to
vacuum triode and is comparatively smaller in size. It is used in amplifier and oscillator circuits, and as a
switch in digital circuits. It has wide applications in computers, satellites and other modern
communication systems.

25
Construction of BJT and its symbols

The Bipolar Transistor basic construction consists of two PN-junctions producing three connecting
terminals with each terminal being given a name to identify it from the other two. These three terminals
are known and labelled as the Emitter (E), the Base (B) and the Collector (C) respectively. There are two
basic types of bipolar transistor construction, PNP and NPN, which basically describes the physical
arrangement of the P-type and N-type semiconductor materials from which they are made.

Transistors are three terminal active devices made from different semiconductor materials that can act as
either an insulator or a conductor by the application of a small signal voltage. The transistor's ability to
change between these two states enables it to have two basic functions: "switching" (digital electronics)
or "amplification" (analogue electronics). Then bipolar transistors have the ability to operate within three
different regions:
1. Active Region - the transistor operates as an amplifier and Ic = β.Ib
2. Saturation - the transistor is "fully-ON" operating as a switch and Ic = I(saturation)
3. Cut-off - the transistor is "fully-OFF" operating as a switch and Ic = 0
Bipolar Transistors are current regulating devices that control the amount of current flowing through them
in proportion to the amount of biasing voltage applied to their base terminal acting like a current-
controlled switch. The principle of operation of the two transistor types PNP and NPN, is exactly the
same the only difference being in their biasing and the polarity of the power supply for each type(fig. 1).

Fig.1 Transistor (a) NPN(b) PNP

Fig.2 Transistor symbol (a) NPN(b) PNP

26
Transistor circuit configurations:
Following are the three types of transistor circuit configurations:
1) Common-Base (CB)
2) Common-Emitter (CE)
3) Common-Collector (CC)
Here the term „Common‟ is used to denote the transistor lead which is common to the input and output
circuits. The common terminal is generally grounded.
It should be remembered that regardless the circuit configuration, the emitter is alwaysforward-
biased while the collector is always reverse-biased.

Fig. 3 Common – Base configuration

Fig.4 Common – emitter configuration

Fig. 5 Common – Collector configuration

27
Operating Point:
The basic function transistor is to do amplification. The process of raising the strength of a weak signal
without any change in its shape is known as faithful amplification. For faithful amplification, the
following three conditions must be satisfied:
i) The emitter-base junction should be forward biased,
ii) The collector-base junction should be reverse biased.
iii) Three should be proper zero signal collector current.
The proper flow of zero signal collector current (proper operating point of a transistor) and the
maintenance of proper collector-emitter voltage during the passage of signal is known as „transistor
biasing‟.

When a transistor is not properly biased, it work inefficiently and produces distortion in the output signal.
Hence a transistor is to be biased correctly. A transistor is biased either with the help of battery (or)
associating a circuit with the transistor. The latter method is generally employed. The circuit used with the
transistor is known as biasing circuit. In order to produce distortion-free output in amplifier circuits, the
supply voltages and resistances in the circuit must be suitably chose. These voltages and resistances
establish a set of d.c. voltage VCEQ and current ICQ to operate the transistor in the active region. These
voltages and currents are called quiescent values which determine the operating point (or) Q-Point for the
[Link] process of giving proper supply voltages and resistances for obtaining the desired QPoint is
called biasing.

DC Load Line:
Referring to the biasing circuit of Fig. 6(a), the values of V CC and RC are fixed and IC and VCE are
dependent on RB. Applying Kirchhoff‟s voltage law to the collector circuit in Fig. 6(a), we get V CC = IC
RC + VCE.
The straight line represented by AB in Fig. 6(b) is called the dc load line. The coordinates of the end point
A are obtained by substituting VCE = 0 in the above equation. Then

Therefore, the coordinates of A are VCE = 0 and

The coordinates of B are obtained by substituting IC = 0 in the above equation. Then VCE = VCC.
Therefore, the coordinates of B are VCE = VCC and IC = 0. Thus, the dc load line AB can be drawn if the
28
values of RC and VCC are known. As shown in Fig. 6(b), the optimum Q-point is located at the midpoint of
the dc load line AB between the saturation and cut-off regions, i.e., Q is exactly midway between A and
B. In order to get faithful amplification, the Q-point must be well within the active region of the transistor.
Even though the Q-point is fixed properly, it is very important to ensure that the operating point remains
stable where it is originally fixed. If the Q-point shifts nearer to either A or B, the output voltage and
current get clipped, thereby output signal is distorted.
In practice, the Q-point tends to shift its position due to any or all of the following three main factors:

(i) Reverse saturation current, ICO, which doubles for every 10°C increase in temperature.
(ii) Base-emitter voltage, VBE, which decreases by 2.5 mV per °C.
(iii) Transistor current gain, b, i.e., hFE which increases with temperature.

Fig. 6(a) Biasing circuit, (b) CE output characteristics and load line

AC Load Line

After drawing the dc load line, the operating point Q is properly located at the center of the dc load line.
This operating point is chosen under zero input signal condition of the circuit. Hence, the ac load line
should also pass through the operating point Q. The effective ac load resistance, Rac, is the combination of
RC parallel to RL, i.e., Rac = RC || RL. So the slope of the ac load line CQD will be . To draw an ac

load line, two end points, viz., maximum VCE and maximum IC when the signal is applied are required.
Maximum VCE = VCEQ + ICQ Rac, which locates the point D (OD) on the VCE axis.

Maximum IC = which locates the point C (OC) on the IC axis.

By joining points C and D, ac load line CD is constructed. As RC> Rac, the dc load line is less steep than
the ac load line. When the signal is zero, we have the exact dc conditions. From Fig. 6(b), it is clear that
the intersection of dc and ac load lines is the operating point Q.
29
Operating Point (or) Quiescent Point:
In designing a circuit, a point on the load line is selected as the dc bias point (or) quiescent point. The Q-
Point specifies the collector current IC and collector to emitter voltage VCE that exists when no input signal
is applied. The dc bias point (or) quiescent point is the point on the load line which represents the current
in a transistor and the voltage across it when no signal is applied. The zero signal values of IC ad VCE are
known as the operating point.
Biasing:

The process of giving proper supply voltages and resistances for obtaining the desired Q point is called
„biasing‟.
How to choose the operating point on DC load line:
The transistor acts as an amplifier when it is operated in active region. After the D.C. conditions are
established in the circuit, when an a.c. signal is applied to the input, the base current varies according to
the amplitude of the signal and causes IC to vary consequently producing an output voltage variation. This
can be seen from output characterizes.

Fig.7 Operating point near saturation region gives clipping at the positive peak.
Consider point P which is very near to the saturation point, even though the base current is varying
sinusoidally the output current and output voltage is seen to be clipped at the positive peaks. This results
in distortion of the signal. Consider point R which is very near to the cut-off region. The output signal is
now clipped at the negative peak. Hence this two is not a suitable operating point.

30
 Fig.8 Operating point near cut-off region given clipping at the negative peak.

Consider point Q which is the mid-point of the DC load line then the output signal will not be distorted. A
good amplifier amplifies signals without introducing distortion. Thus always the operating point is chosen
as the mid-point of the DC load line.

Fig.9operating point is center of the active region is more suitable

31
Two –Port Devices and Network Parameters

All the transistor amplifiers are two port networks having two voltages and two currents. The positive
directions of voltages and currents are shown in fig. 10.

Fig.10 Two port network model

A two-port network is represented by four external variables: voltage V1 and current I1 at the input port,
and voltage V2 and current I2at the output port, so that the two-port network can be treated as a black box
modeled by the relationships between the four variables,V1,V2, I1,I2 . Out of four variables two can be
selected as are independent variables and two are dependent variables. The dependent variables can be
expressed interns of independent variables. This leads to various two port parameters out of which the
following three are important:

1. Impedance parameters (z-parameters)

2. Admittance parameters (y-parameters)
3. Hybrid parameters (h-parameters)

z-parameters

A two-port network can be described by z-parameters as

In matrix form, the above equation can be rewritten as

Where

32
Input impedance with output port open circuited

Reverse transfer impedance with input port open circuited

Forward transfer impedance with output port open circuited

Output impedance with input port open circuited

Y-parameters

A two-port network can be described by Y-parameters as

In matrix form, the above equation can be rewritten as

Input admittance with output port short circuited

33
Reverse transfer admittance with input port short circuited

Forward transfer admittance with output port short circuited

Output admittance with input port short circuited

Hybrid parameters (h-parameters)

If the input current I1 and output voltage V2 are taken as independent variables, the dependent variables
V1 and I2 can be written as

Where h11, h12, h21, h22 are called as hybrid parameters.

at V2 = 0

Input impedance with o/p port short circuited

at I1 = 0

Reverse voltage transfer ratio with i/p port open circuited

at V2 = 0

Forward voltage transfer ratio with o/p port short circuited

at I1 = 0

34
output impedance with i/p port open circuited

The hybrid model for two port network:

Based on the definition of hybrid parameters the mathematical model for two pert networks known as h-
parameter model can be developed. The hybrid equations can be written as:

(The following convenient alternative subscript notation is recommended by the IEEE Standards: i=11=
input, o = 22 = output, f =21 = forward transfer, r = 12 = reverse transfer)
The below figure shows the construction of bjt using h parameters

Fig.11 Hybrid model for a two-port network

The hybrid circuit for any device indicated in below Figure. We can verify that the model of below Figure
satisfies above equations by writing Kirchhoff's voltage and current laws for input and output ports.

Fig.12 small signal model using h parameters

35
If these parameters are specified for a particular configuration, then suffixes e, b or c are also included,
e.g. hfe ,h ib are h parameters of common emitter and common collector amplifiers.

Common – Base (CB) configurations:

In this configuration, the input signal is applied between emitter and base while the output is taken from
collector and base. As base is common to input and output circuits, hence the namecommon-base
configuration. Figure show the common-base P-N-P transistor circuit.

Fig. 13 Common – base PNP transistor amplifier.

Current Amplification Factor (α) :

When no signal is applied, then the ratio of the collector current to the emitter current is called dc alpha (α
dc) of a transistor.

αdc=

(Negative sign signifies that IE flows into transistor while IC flows out of it).
„α‟ of a transistor is a measure of the quality of a transistor. Higher is the value of „α ‟, better is the
transistor in the sense that collector current approaches the emitter current.
By considering only magnitudes of the currents, IC = α IE and hence IB = IE - IC
Therefore,
IB = IE -α IE = IE(1-α)
When signal is applied, the ratio of change in collector current to the change in emitter current at constant
collector-base voltage is defined as current amplification factor,
αdc=

Total Collector Current:

The total collector current consists of the following two parts
36
i) IE , current due to majority carriers
ii) ICBO, current due to minority carriers
Total collector current IC = α IE + ICBO
The collector current can also be expressed as IC = α(IB+IC) + ICBO

Fig. 14 Circuit to determine CB static characteristics.

Input Characteristics:
To determine the input characteristics, the collector-base voltage VCB is kept constant at zero volts and the
emitter current IE is increased from zero in suitable equal steps by increasing VEB. This is repeated for
higher fixed values of VCB. A curve is drawn between emitter current IE and emitter-base voltage VEB at
constant collector-base voltage VCB.
The input characteristics thus obtained are shown in figure below.

Fig. 15 CB Input characteristics.

37
Early effect (or) Base – Width modulation:
As the collector voltage VCC is made to increase the reverse bias, the space charge width between
collector and base tends to increase, with the result that the effective width of the base decreases. This
dependency of base-width on collector-to-emitter voltage is known as early effect (or) Base-Width
modulation.

Fig. 16 CB configuration

Thus decrease in effective base width has following consequences:

i. Due to Early effect, the base width reduces, there is a less chance of recombination of holes with
electrons in base region and hence base current IB decreases.
ii. As IB decreases, the collector current IC increases.
iii. As base width reduces the emitter current IE increases for small emitter to base voltage.
iv. As collector current increases, common base current gain (α) increases.

Punch Through (or) Reach Through:

When reverse bias voltage increases more, the depletion region moves towards emitter junction and
effective base width reduces to zero. This causes breakdown in the transistor. This condition is called
“Punch Through” condition.

Output Characteristics:
To determine the output characteristics, the emitter current IE is kept constant at a suitable value by
adjusting the emitter-base voltage VEB. Then VCB is increased in suitable equal steps and the collector
current IC is noted for each value of IE. Now the curves of IC versus VCB are plotted for constant values of
IE and the output characteristics thus obtained is shown in figure below.

38
 Fig. 17 CB Output characteristics

From the characteristics, it is seen that for a constant value of IE, IC is independent of VCB and the curves
are parallel to the axis of VCB. Further, IC flows even when VCB is equal to zero. As the emitter-base
junction is forward biased, the majority carriers, i.e., electrons, from the emitter are injected into the base
region. Due to the action of the internal potential barrier at the reverse biased collector-base junction, they
flow to the collector region and give rise to IC even when VCB is equal to zero.

Transistor Parameters:
The slope of the CB characteristics will give the following four transistor parameters. Since these
parameters have different dimensions, they are commonly known as common base hybrid parameters (or)
h-parameters.

i) Input Impedance (hib):

It is defined as the ratio of change in (input) emitter to base voltage to the change in (input) emitter
current with the (output) collector to base voltage kept constant. Therefore,
, VCB Constant

It is the slope of CB input characteristics curve.

The typical value of hib ranges from 20 ohms to 50 ohms.

ii) Output Admittance (hob):

It is defined as the ratio of change in the (output) collector current to the corresponding change in the
(output) collector-base voltage, keeping the (input) emitter current IE constant. Therefore,
, IE Constant

39
It is the slope of CB output characteristics IC versus VCB.
The typical value of this parameter is of the order of 0.1 to 10μmhos.

iii) Forward Current Gain (hfb):

It is defined as a ratio of the change in the (output) collector current to the corresponding change in the
(input) emitter current keeping the (output) collector voltage VCB constant. Hence,
, VCB Constant

It is the slope of IC versus IE curve. Its typical value varies from 0.9 to 1.0.

iv) Reverse Voltage Gain (hrb):

It is defined as a ratio of the change in the (input) emitter voltage and the corresponding change in
(output) collector voltage with constant (input) emitter current, IE. Hence,
, IE Constant

It is the slope of VEB versus VCB curve. Its typical value is of the order of 10-5 to 10-4

Common-Emitter (CE) configuration:

In this configuration, the input signal is applied between base and emitter and the output is taken from
collector and emitter. As emitter is common to input and output circuits, hence the name common emitter
[Link] shows the common-emitter P-N-P transistor circuit.

Fig. 18Common-Emitter NPN transistor amplifier.

Current Amplification Factor (β):

When no signal is applied, then the ratio of collector current to the base current is called dc beta (βdc) of a
transistor.

40
Total Collector Current:
The Total collector current IC = β IB + ICEO
Where ICEO is the leakage current.

Characteristics of Common-Emitter Circuit:

The circuit diagram for determining the static characteristic curves of the N-P-N transistor in the common
emitter configuration is shown in figure below.

Fig. 19 Circuit to determine CE Static characteristics.

Input Characteristics:
To determine the input characteristics, the collector to emitter voltage is kept constant at zero volts and
base current is increased from zero in equal steps by increasing V BE in the circuit. The value of VBE is
noted for each setting of IB. This procedure is repeated for higher fixed valuesof VCE, and the curves of IB
versus VBE are drawn.
The input characteristics thus obtained are shown in figure below.

Fig. 20 CE Input Characteristics.

When VCE=0, the emitter-base junction is forward biased and he junction behaves as a forward biased
diode. When VCE is increased, the width of the depletion region at the reverse biased collector-base

41
junction will increase. Hence the effective width of the base will decrease. This effect causes a decrease in
the base current IB. Hence, to get the same value of IB as that for VCE=0, VBE should be increased.
Therefore, the curve shifts to the right as VCE increases.

Output Characteristics:
To determine the output characteristics, the base current IB is kept constant at a suitable value by adjusting
base-emitter voltage, VBE. The magnitude of collector-emitter voltage VCE is increased in suitable equal
steps from zero and the collector current IC is noted for each setting of VCE. Now the curves of IC versus
VCE are plotted for different constant values of IB. The output characteristics thus obtained are shown in
below figure.

Fig. 21 CE Output characteristics

The output characteristics of common emitter configuration consist of three regions: Active, Saturation
and Cut-off regions.

Active Region: The region where the curves are approximately horizontal is the “Active” region of the
CE configuration. In the active region, the collector junction is reverse biased. As V CE is increased,
reverse bias increase. This causes depletion region to spread more in base than in collector, reducing the
changes of recombination in the base.

Saturation Region: If VCE is reduced to a small value such as 0.2V, then collector-base junction becomes
forward biased, since the emitter-base junction is already forward biased by 0.7V. The input junction in
CE configuration is base to emitter junction, which is always forward biased to operate transistor in active
region. Thus input characteristics of CE configuration are similar to forward characteristics of p-n
junction diode. When both the junctions are forwards biased, the transistor operates in the saturation
region, which is indicated on the output characteristics. The saturation value of V CE, designated VCE(Sat) ,
usually ranges between 0.1V to 0.3V.
42
Cut-Off Region: When the input base current is made equal to zero, the collector current is the reverse
leakage current ICEO. Accordingly, in order to cut off the transistor, it is not enough to reduce IB=0.
Instead, it is necessary to reverse bias the emitter junction slightly. We shall define cut off as the condition
where the collector current is equal to the reverse saturation current ICO and the emitter current is zero.

Transistor Parameters:
The slope of the CE characteristics will give the following four transistor parameters. Since these
parameters have different dimensions, they are commonly known as Common emitter hybrid parameters
(or) h-parameters.
i) Input Impedance (hie):
It is defined as the ratio of change in (input) base voltage to the change in (input) base current with the
(output) collector voltage (VCE), kept constant. Therefore,
, VCE Constant

It is the slope of CB input characteristics IB versus VBE.

The typical value of hie ranges from 500Ωto 2000Ω.

ii) Output Admittance (hoe):

It is defined as the ratio of change in the (output) collector current to the corresponding change in the
(output) collector voltage. With the (input) base current IB kept constant. Therefore,
, IB constant

It is the slope of CE output characteristics IC versus VCE.

The typical value of this parameter is of the order of 0.1 to 10μmhos.

iii) Forward Current Gain (hfe):

It is defined as a ratio of the change in the (output) collector current to the corresponding change in the
(input) base current keeping the (output) collector voltage VCE constant. Hence,
, VCE constant

It is the slope of IC versus IB curve.

It‟s typical value varies from 20 to 200.

iv) Reverse Voltage Gain (hre):

43
It is defined as a ratio of the change in the (input) base voltage and the corresponding change in (output)
collector voltage with constant (input) base current, IB. Hence,
, IE constant

It is the slope of VBE versus VCE curve.

Its typical value is of the order of 10-5 to 10-4

Common – Collector (CC) Configuration:

In this configuration, the input signal is applied between base and collector and the output is taken from
the emitter. As collector is common to input and output circuits, hence the name common collector
configuration. Figure shows the common collector PNP transistor circuit.

Fig. 22Common collector NPN transistor amplifier.

Current Amplification Factor γ:

When no signal is applied, then the ratio of emitter current to the base current is called as dc gamma (γdc)
of the transistor.

Characteristics of common collector circuit:

The circuit diagram for determining the static characteristics of an N-P-N transistor in the common
collector configuration is shown in fig. below.

Fig. 23 Circuit to determine CC static characteristics.

44
Input Characteristics:
To determine the input characteristic, VEC is kept at a suitable fixed value. The base collector voltage VBC
is increased in equal steps and the corresponding increase in IB is noted. This is repeated for different
fixed values of VEC. Plots of VBC versus IB for different values of VEC shown in figure are the input
characteristics.

Fig. 24 CC Input Characteristics.

Output Characteristics:
The output characteristics shown in figure below are the same as those of the common emitter
configuration.

Fig. 25 CC output characteristics.

45
Conversion of h-parameters
Table 1 gives the conversion formulae to find the h-parameters for CC and CB configurations, given the
h-parameters for CE configuration.

Table1. Conversion of h-parameter from CE model

CC CB

hrc = 1

hfc = -(1+hfe)

hoc =hoe

46
 MODULE – III

TRANSISTOR BIASING AND STABILIZATION

Bias Stability, Fixed Bias, Collector to Base bias, Self-Bias, Bias Compensation using Diodes and
Transistors.
Analysis and Design of Small Signal Low Frequency BJT Amplifiers: Analysis of CE, CC, CB
Amplifiers and CE Amplifier with emitter resistance, low frequency response of BJT Amplifiers,
effect of coupling and bypass capacitors on CE Amplifier.

COURSE OUTCOMES (COs):

After successful completion of the course, students will be able to:

CO No Course Outcomes Knowledge Level

(Bloom’s
Taxonomy)
CO 6 Analyse the input and output characteristics of transistor configurations for Analyze
determining the input - output resistances, current gain and voltage gain.
CO 7 Estimate the characteristic parameters of BJT, FET amplifier circuits using Evaluate
low frequency model.
CO 9 Design the various biasing techniques for BJT, JFET and MOSFETs Apply
amplifier circuits considering stability condition for establishing a proper
operating point.
CO 12 Design basic electronic circuits using active transistors Create
CO 13 Apply electronic circuits in global engineering applications Apply

NEED FOR TRANSISTOR BIASING:

Biasing is the process of providing DC voltage which helps in the functioning of the
circuit. A transistor is based in order to make the emitter base junction forward biased and
collector base junction reverse biased, so that it maintains in active region, to work as an
amplifier.
In the previous chapter, we explained how a transistor acts as a good amplifier, if both the input
and output sections are biased.

47
Transistor Biasing

The proper flow of zero signal collector current and the maintenance of proper collector emitter
voltage during the passage of signal is known as Transistor Biasing. The circuit which provides
transistor biasing is called as Biasing Circuit.

Need for DC biasing

If a signal of very small voltage is given to the input of BJT, it cannot be amplified. Because, for
a BJT, to amplify a signal, two conditions have to be met.
 The input voltage should exceed cut-in voltage for the transistor to be ON.
 The BJT should be in the active region, to be operated as an amplifier.


If appropriate DC voltages and currents are given through BJT by external sources, so that BJT
operates in active region and superimpose the AC signals to be amplified, then this problem can
be avoided. The given DC voltage and currents are so chosen that the transistor remains in
active region for entire input AC cycle. Hence DC biasing is needed.
The below figure shows a transistor amplifier that is provided with DC biasing on both input
and output circuits.

For a transistor to be operated as a faithful amplifier, the operating point should be stabilized.
Let us have a look at the factors that affect the stabilization of operating point.

48
Factors affecting the operating point

The main factor that affect the operating point is the temperature. The operating point shifts due
to change in temperature.

As temperature increases, the values of ICE, β, VBE gets affected.

 ICBO gets doubled (for every 10o rise)

 VBE decreases by 2.5mv (for every 1o rise)

So the main problem which affects the operating point is temperature. Hence operating point
should be made independent of the temperature so as to achieve stability. To achieve this,
biasing circuits are introduced.

Stabilization

The process of making the operating point independent of temperature changes or variations in
transistor parameters is known as Stabilization.

Once the stabilization is achieved, the values of IC and VCE become independent of temperature
variations or replacement of transistor. A good biasing circuit helps in the stabilization of
operating point.

Need for Stabilization

Stabilization of the operating point has to be achieved due to the following reasons.

 Temperature dependence of IC

 Individual variations

 Thermal runaway

Let us understand these concepts in detail.

Temperature Dependence of IC

As the expression for collector current IC is

49
 IC=βIB+ICEO

=βIB+(β+1) ICBO

The collector leakage current ICBO is greatly influenced by temperature variations. To come out
of this, the biasing conditions are set so that zero signal collector current IC = 1 mA. Therefore,
the operating point needs to be stabilized i.e. it is necessary to keep IC constant.

Individual Variations

As the value of β and the value of VBE are not same for every transistor, whenever a transistor is
replaced, the operating point tends to change. Hence it is necessary to stabilize the operating
point.

Thermal Runaway

As the expression for collector current IC is

IC=βIB+ICEO

=βIB+(β+1) ICBO

The flow of collector current and also the collector leakage current causes heat dissipation. If
the operating point is not stabilized, there occurs a cumulative effect which increases this heat
dissipation.

The self-destruction of such an unstabilized transistor is known as Thermal run away.

In order to avoid thermal runaway and the destruction of transistor, it is necessary to stabilize
the operating point, i.e., to keep IC constant.

Stability Factor

It is understood that IC should be kept constant in spite of variations of ICBO or ICO. The extent to
which a biasing circuit is successful in maintaining this is measured by Stability factor. It
denoted by S.

50
By definition, the rate of change of collector current IC with respect to the collector leakage
current ICO at constant β and IB is called Stability factor.

S=dIC / dICOat constant IB and β

Hence we can understand that any change in collector leakage current changes the collector
current to a great extent. The stability factor should be as low as possible so that the collector
current doesn‟t get affected. S=1 is the ideal value.

The general expression of stability factor for a CE configuration can be obtained as under.

IC=βIB+(β+1) ICO

Differentiating above expression with respect to IC, we get

1=β dIB / dIC+(β+1) dICO / dIC

Or

1=β dIB / dIC+(β+1) S

Since dICO / dIC=1S

Or
S=β+1/ 1−β (dIB / dIC)
Hence the stability factor S depends on β, IB and IC.

The biasing in transistor circuits is done by using two DC sources VBB and VCC. It is economical
to minimize the DC source to one supply instead of two which also makes the circuit simple.

The commonly used methods of transistor biasing are

 Base Resistor method

 Collector to Base bias

 Biasing with Collector feedback resistor

 Voltage-divider bias

51
All of these methods have the same basic principle of obtaining the required value of IB and
IC from VCC in the zero signal conditions.

Base Resistor Method

In this method, a resistor RB of high resistance is connected in base, as the name implies. The
required zero signal base current is provided by VCC which flows through RB. The base emitter
junction is forward biased, as base is positive with respect to emitter.

The required value of zero signal base current and hence the collector current (as IC = βIB) can
be made to flow by selecting the proper value of base resistor RB. Hence the value of R B is to
be known. The figure below shows how a base resistor method of biasing circuit looks like.

Let IC be the required zero signal collector current. Therefore,

IB=ICβ

Considering the closed circuit from VCC, base, emitter and ground, while applying the
Kirchhoff‟s voltage law, we get,

VCC=IBRB+VBE

Or

IBRB=VCC−VBE

52
Therefore

RB=VCC−VBEIB

Since VBE is generally quite small as compared to VCC, the former can be neglected with little
error. Then,

RB=VCCIB

We know that VCC is a fixed known quantity and IB is chosen at some suitable value. As RB can
be found directly, this method is called as fixed bias method.

Stability factor

S=β+1 / 1−β (dIB / dIC)

In fixed-bias method of biasing, IB is independent of IC so that,

dIB / dIC= 0

Substituting the above value in the previous equation,

Stability factor, S=β+1

Thus the stability factor in a fixed bias is (β+1) which means that IC changes (β+1) times as
much as any change in ICO.
Advantages
 The circuit is simple.
 Only one resistor RE is required.

 Biasing conditions are set easily.

 No loading effect as no resistor is present at base-emitter junction.

Disadvantages

 The stabilization is poor as heat development can‟t be stopped.

 The stability factor is very high. So, there are strong chances of thermal run away.

Hence, this method is rarely employed.

53
Collector to Base Bias

The collector to base bias circuit is same as base bias circuit except that the base resistor R B is
returned to collector, rather than to VCC supply as shown in the figure below.

This circuit helps in improving the stability considerably. If the value of IC increases, the
voltage across RL increases and hence the VCE also increases. This in turn reduces the base
current IB. This action somewhat compensates the original increase.

The required value of RB needed to give the zero-signal collector current IC can be calculated as
follows.

Voltage drop across RL will be

RL=(IC+IB) RL≅ICRL

From the figure,

ICRL+IBRB+VBE=VCC

Or

IBRB=VCC−VBE−ICRL

Therefore

RB=VCC−VBE−ICRLIB
54
Or

RB=(VCC−VBE−ICRL) βIC

Applying KVL we have

(IB+IC) RL+IBRB+VBE=VCC

Or

IB(RL+RB)+ICRL+VBE=VCC

Therefore

IB=(VCC−VBE−ICRL) / (RL+RB)

Since VBE is almost independent of collector current, we get

dIB / dIC= −RL / (RL+RB)

We know that

S=(1+β) / 1−β (dIB/ dIC)

Therefore

S=(1+β) / 1+β (RL / RL+RB)

This value is smaller than (1+β) which is obtained for fixed bias circuit. Thus there is an
improvement in the stability.

This circuit provides a negative feedback which reduces the gain of the amplifier. So the
increased stability of the collector to base bias circuit is obtained at the cost of AC voltage gain.

Biasing with Collector Feedback resistor

In this method, the base resistor RB has its one end connected to base and the other to the
collector as its name implies. In this circuit, the zero signal base current is determined by
VCB but not by VCC.

55
It is clear that VCB forward biases the base-emitter junction and hence base current IB flows
through RB. This causes the zero signal collector current to flow in the circuit. The below figure
shows the biasing with collector feedback resistor circuit.

The required value of RB needed to give the zero-signal current IC can be determined as follows.

VCC=ICRC+IBRB+VBE

Or

RB=VCC−VBE−ICRCIB

=VCC−VBE−βIBRCIB

Since IC=βIB

Alternatively,

VCE=VBE+VCBVCE=VBE+VCB

Or

VCB=VCE−VBE

Since

56
 RB=VCBIB=VCE−VBEIB

Where

IB=ICβ

Mathematically,

Stability factor, S<(β+1)

Therefore, this method provides better thermal stability than the fixed bias.

The Q-point values for the circuit are shown as

IC=(VCC−VBE ) / ((RB/β)+RC)

VCE=VCC−ICRC

Advantages

 The circuit is simple as it needs only one resistor.

 This circuit provides some stabilization, for lesser changes.

Disadvantages

 The circuit doesn‟t provide good stabilization.

 The circuit provides negative feedback.

Voltage Divider Bias Method

Among all the methods of providing biasing and stabilization, the voltage divider bias
method is the most prominent one. Here, two resistors R1 and R2 are employed, which are
connected to VCC and provide biasing. The resistor RE employed in the emitter provides
stabilization.

The name voltage divider comes from the voltage divider formed by R1 and R2. The voltage
drop across R2 forward biases the base-emitter junction. This causes the base current and hence

57
collector current flow in the zero signal conditions. The figure below shows the circuit of
voltage divider bias method.

Suppose that the current flowing through resistance R1 is I1. As base current IB is very small,
therefore, it can be assumed with reasonable accuracy that current flowing through R 2 is also I1.
Now let us try to derive the expressions for collector current and collector voltage.

Collector Current, IC

From the circuit, it is evident that,

I1=VCCR1+R2

Therefore, the voltage across resistance R2 is

V2=(VCCR1+R2) R2

Applying Kirchhoff‟s voltage law to the base circuit,

V2=VBE+VE

V2=VBE+IERE

IE=V2−VBERE

Since IE ≈ IC,

58
 IC=V2−VBERE

From the above expression, it is evident that IC doesn‟t depend upon β. VBE is very small that
IC doesn‟t get affected by VBE at all. Thus IC in this circuit is almost independent of transistor
parameters and hence good stabilization is achieved.

Collector-Emitter Voltage, VCE

Applying Kirchhoff‟s voltage law to the collector side,

VCC=ICRC+VCE+IERE

Since IE ≅ IC

=ICRC+VCE+ICRE

=IC(RC+RE) +VCE

Therefore,

VCE=VCC− IC(RC+RE)

RE provides excellent stabilization in this circuit.

V2=VBE+ICRE

Suppose there is a rise in temperature, then the collector current IC decreases, which causes the
voltage drop across RE to increase. As the voltage drop across R2 is V2, which is independent of
IC, the value of VBE decreases. The reduced value of IB tends to restore IC to the original value.

Stability Factor

The equation for Stability factor of this circuit is obtained as

Stability Factor = S=(β+1) (R0+R3) / (R0+RE+βRE)

=(β+1)×(1+R0 / RE) / (β+1+R0 / RE)

Where

R0=R1R2 / (R1+R2)
59
If the ratio R0/RE is very small, then R0/RE can be neglected as compared to 1 and the stability
factor becomes

Stability Factor = S=(β+1)×1 / (β+1)=1

This is the smallest possible value of S and leads to the maximum possible thermal stability.

So far we have seen different stabilization techniques. The stabilization occurs due to negative
feedback action. The negative feedback, although improves the stability of operating point, it
reduces the gain of the amplifier.

As the gain of the amplifier is a very important consideration, some compensation techniques
are used to maintain excellent bias and thermal stabilization. Let us now go through such bias
compensation techniques.

Diode Compensation for Instability

These are the circuits that implement compensation techniques using diodes to deal with biasing
instability. The stabilization techniques refer to the use of resistive biasing circuits which permit
IB to vary so as to keep IC relatively constant.

There are two types of diode compensation methods. They are −

 Diode compensation for instability due to VBE variation

 Diode compensation for instability due to ICO variation

Let us understand these two compensation methods in detail.

Diode Compensation for Instability due to VBE Variation

In a Silicon transistor, the changes in the value of VBE results in the changes in IC. A diode can
be employed in the emitter circuit in order to compensate the variations in VBE or ICO. As the
diode and transistor used are of same material, the voltage VD across the diode has same
temperature coefficient as VBE of the transistor.

The following figure shows self-bias with stabilization and compensation.

60
The diode D is forward biased by the source VDD and the resistor RD. The variation in VBE with
temperature is same as the variation in VD with temperature, hence the quantity (VBE – VD)
remains constant. So the current IC remains constant in spite of the variation in VBE.

Diode Compensation for Instability due to ICO Variation

The following figure shows the circuit diagram of a transistor amplifier with diode D used for
compensation of variation in ICO.

61
So, the reverse saturation current IO of the diode will increase with temperature at the same rate
as the transistor collector saturation current ICO.

I=VCC−VBER≅VCCR=Constant

The diode D is reverse biased by VBE and the current through it is the reverse saturation current
IO.

Now the base current is,

IB=I−IO

Substituting the above value in the expression for collector current.

IC=β(I−IO)+(1+β)ICO

If β ≫ 1,
IC=βI−βIO+βICO
I is almost constant and if IO of diode and ICO of transistor track each other over the operating
temperature range, then IC remains constant.

Other Compensations

There are other compensation techniques which refer to the use of temperature sensitive devices
such as diodes, transistors, thermistors, Sensistors, etc. to compensate for the variation in
currents.

There are two popular types of circuits in this method, one using a thermistor and the other
using a Sensistor. Let us have a look at them.

Thermistor Compensation

Thermistor is a temperature sensitive device. It has negative temperature coefficient. The

resistance of a thermistor increases when the temperature decreases and it decreases when the
temperature increases. The below figure shows a self-bias amplifier with thermistor
compensation.

62
In an amplifier circuit, the changes that occur in ICO, VBE and β with temperature, increases the
collector current. Thermistor is employed to minimize the increase in collector current. As the
temperature increases, the resistance RT of thermistor decreases, which increases the current
through it and the resistor RE. Now, the voltage developed across RE increases, which reverse
biases the emitter junction. This reverse bias is so high that the effect of resistors R1 and
R2 providing forward bias also gets reduced. This action reduces the rise in collector current.

Thus the temperature sensitivity of thermistor compensates the increase in collector current,
occurred due to temperature.

Sensistor Compensation

A Sensistor is a heavily doped semiconductor that has positive temperature coefficient. The
resistance of a Sensistor increases with the increase in temperature and decreases with the
decrease in temperature. The figure below shows a self-bias amplifier with Sensistor
compensation.

63
In the above figure, the Sensistor may be placed in parallel with R1 or in parallel with RE. As the
temperature increases, the resistance of the parallel combination, thermistor and R1 increases
and their voltage drop also increases. This decreases the voltage drop across R 2. Due to the
decrease of this voltage, the net forward emitter bias decreases. As a result of this, IC decreases.

Hence by employing the Sensistor, the rise in the collector current which is caused by the
increase of ICO, VBE and β due to temperature, gets controlled.

Thermal Resistance

The transistor is a temperature dependent device. When the transistor is operated, the collector
junction gets heavy flow of electrons and hence has much heat generated. This heat if increased
further beyond the permissible limit, damages the junction and thus the transistor.

In order to protect itself from damage, the transistor dissipates heat from the junction to the
transistor case and from there to the open air surrounding it.

Let, the ambient temperature or the temperature of surrounding air = TAoC

And, the temperature of collector-base junction of the transistor = TJoC

As TJ > TA, the difference TJ - TA is greater than the power dissipated in the transistor PD will be
greater. Thus,

64
 TJ−TA∝PD

TJ−TA=HPD

Where H is the constant of proportionality, and is called as Thermal resistance.

Thermal resistance is the resistance to heat flow from junction to surrounding air. It is denoted
by H.

H= (TJ−TA) / PD

the unit of H is oC/watt.

If the thermal resistance is low, the transfer of heat from the transistor into the air, will be easy.
If the transistor case is larger, the heat dissipation will be better. This is achieved by the use of
Heat sink.

Heat Sink

The transistor that handle larger powers, dissipates more heat during operation. This heat if not
dissipated properly, could damage the transistor. Hence the power transistors are generally
mounted on large metal cases to provide a larger area to get the heat radiated that is generated
during its operation.

The metal sheet that helps to dissipate the additional heat from the transistor is known as
the heat sink. The ability of a heat sink depends upon its material, volume, area, shape, contact
between case and sink, and the movement of air around the sink.

65
 The heat sink is selected after considering all these factors. The image shows a power transistor
with a heat sink. A tiny transistor in the above image is fixed to a larger metal sheet in order to
dissipate its heat, so that the transistor doesn‟t get damaged.

Thermal Runaway

The use of heat sink avoids the problem of Thermal Runaway. It is a situation where an
increase in temperature leads to the condition that further increase in temperature, leads to the
destruction of the device itself. This is a kind of uncontrollable positive feedback.

Heat sink is not the only consideration; other factors such as operating point, ambient
temperature, and the type of transistor used can also cause thermal runaway.
Low frequency model

V-I characteristics of an active device such as BJT are non-linear. The analysis of a non- linear device is
complex. Thus to simplify the analysis of the BJT, its operation is restricted to the linear V-I
characteristics around the Q-point i.e. in the active region. This approximation is possible only with small
input signals. With small input signals transistor can be replaced with small signal linear model. This
model is also called small signal equivalent circuit.

Two Port Devices and Network Parameters

Small signal low frequency transistor Models:

All the transistor amplifiers are two port networks having two voltages and two currents. The positive
directions of voltages and currents are shown in below .

A two-port network is represented by four external variables: voltage V1 and current I1 at the input port,
and voltage V2 and current I2at the output port, so that the two-port network can be treated as a black box
modeled by the relationships between the four variables,V1,V2, I1,I2 . Out of four variables two can be
selected as are independent variables and two are dependent variables. The dependent variables can be

66
expressed interns of independent variables. This leads to various two port parameters out of which the
following three are important:

1. Impedance parameters (z-parameters)

2. Admittance parameters (y-parameters)
3. Hybrid parameters (h-parameters)

z-parameters

A two-port network can be described by z-parameters as

In matrix form, the above equation can be rewritten as

Where

Input impedance with output port open circuited

Reverse transfer impedance with input port open circuited

Forward transfer impedance with output port open circuited

Output impedance with input port open circuited

67
Y-parameters

A two-port network can be described by Y-parameters as

In matrix form, the above equation can be rewritten as

Input admittance with output port short circuited

Reverse transfer admittance with input port short circuited

Forward transfer admittance with output port short circuited

Output admittance with input port short circuited

Hybrid parameters (h-parameters)

If the input current I1 and output voltage V2 are taken as independent variables, the dependent variables
V1 and I2 can be written as

68
Where h11, h12, h21, h22 are called as hybrid parameters.

Input impedance with o/p port short circuited

Reverse voltage transfer ratio with i/p port open circuited

Forward voltage transfer ratio with o/p port short circuited

output impedance with ai/p port open circuited

THE HYBRID MODEL FOR TWO PORT NETWORK:

Based on the definition of hybrid parameters the mathematical model for two pert networks known as h-
parameter model can be developed. The hybrid equations can be written as:

i=11= input

o = 22 = output
69
f =21 = forward transfer

r = 12 = reverse transfer

Use the four h parameters to construct a mathematical model of the device of Fig.(1). The hybrid circuit
for any device indicated in Fig. It satisfies above equations by writing Kirchhoff's voltage and current laws
for input and output ports.

If these parameters are specified for a particular configuration, then suffixes e,b or c are also included, e.g.
hfe ,h ib are h parameters of common emitter and common collector amplifiers

Using two equations the generalized model of the amplifier can be drawn as shown in fig.

TRANSISTOR HYBRID MODEL:

The hybrid model for a transistor amplifier can be derived as follow:

Let us consider CE configuration as show in fig. The variables, iB, iC ,vC, and vB represent total
instantaneous currents and voltages iB and vC can be taken as independent variables and vB, IC as dependent
variables.
70
 Fig. CE configuration

VB = f1 (iB ,vC ) IC = f2 (iB ,vC).

Using Taylor 's series expression, and neglecting higher order terms we obtain.

The partial derivatives are taken keeping the collector voltage or base current constant. The Δ vB, Δ vC, Δ iB,
Δ iC represent the small signal (incremental) base and collector current and voltage and can be represented
as vB,iC, iB ,vC

The model for CE configuration is shown in fig..

71
 Fig. Hybrid model for CE configuration

To determine the four h-parameters of transistor amplifier, input and output characteristic are used. Input
characteristic depicts the relationship between input voltage and input current with output voltage as
parameter. The output characteristic depicts the relationship between output voltage and output current
with input current as parameter. Fig, shows the output characteristics of CE amplifier.

Fig. output characteristics of CE amplifier

The current increments are taken around the quiescent point Q which corresponds to iB = IB and to the
collector voltage VCE = VC

The value of hoe at the quiescent operating point is given by the slope of the output characteristic at the
operating point (i.e. slope of tangent AB).

72
hie is the slope of the appropriate input on fig. , at the operating point (slope of tangent EF at Q).

Fig. hie is the slope of the appropriate input

A vertical line on the input characteristic represents constant base current. The parameter hre can be
obtained from the ratio (VB2– V B1 ) and (VC2– V C1 ) for at Q.

hie = 1000 ohm.

hre = 2.5 * 10 4
hfe = 50
hoe = 25 * 10 -6 A/ V

ANALYSIS OF A TRANSISTOR AMPLIFIER USING H-PARAMETERS:

To form a transistor amplifier it is only necessary to connect an external load and signal source as
indicated in fig. and to bias the transistor properly.

73
 Fig. Transistor Amplifier

Consider the two-port network of CE amplifier. RS is the source resistance and ZL is the load impedance
h-parameters are assumed to be constant over the operating range. The ac equivalent circuit is shown in
fig. (Phasor notations are used assuming sinusoidal voltage input). The quantities of interest are the
current gain, input impedance, voltage gain, and output impedance.

Fig. AC equivalent circuit

Current Gain or Current Amplification (Ai)

For transistor amplifier the current gain Ai is defined as the ratio of output current to input current,i.e,
Ai =IL /I1 = -I2 / I1
From the circuit of Fig
I2= hf I1 + hoV2

Substituting V2 = ILZL = -I2ZL

I2= hf I1- I2ZL ho

I2 + I2ZL ho = hf I1

74
 I2( 1+ ZL ho) = hf I1

Ai = -I2 / I1 = - hf / ( 1+ ZL ho)

Therefore, Ai = - hf / ( 1+ ZL ho)

Input Impedance (Zi)

In the circuit of Fig, RS is the signal source resistance .The impedance seen when looking into the
amplifier terminals (1,1‟) is the amplifier input impedance Zi,

Zi = V1 / I1

From the input circuit of Fig V1 = hi I1 + hrV2

Zi = ( hiI1 + hrV2) / I1

= hi + hr V2 / I1

Substituting

V2 = -I2 ZL = A1I1ZL

Zi = hi + hr A1I1ZL / I1

= hi + hr A1ZL

Substituting for Ai

Zi = hi - hfhr ZL / (1+ hoZL)

= hi - hfhr ZL / ZL(1/ZL+ ho)

Taking the Load admittance as YL =1/ ZL

Zi = hi - hfhr / (YL + ho)

Voltage Gain or Voltage Gain Amplification Factor (Av)

The ratio of output voltage V2 to input voltage V1 gives the voltage gain of the transistor i.e,

Av = V2 / V1

75
Substituting

V2 = -I2 ZL = A1I1ZL

Av = A1I1ZL /V1= AiZL / Zi

Output Admittance (Yo)

Yo is obtained by setting VS to zero, ZL to infinity and by driving the output terminals from a generator V2.
If the current V2 is I2 then Yo= I2/V2 with VS=0 and RL= ∞.

From the circuit of fig

I2= hf I1 + hoV2

Dividing by V2,

I2 / V2 = hf I1/V2 + ho

With V2= 0, by KVL in input circuit,

RSI1 + hi I1 + hrV2 = 0

(RS + hi)I1 + hrV2 = 0

Hence, I2 / V2 = -hr/ (RS + hi)

= hf (-hr/( RS + hi)+ho

Yo= ho- hf hr/( RS + hi)

The output admittance is a function of source resistance. If the source impedance is resistive then Yois
real.

Voltage Amplification Factor(Avs) taking into account the resistance (Rs) of the source

Fig. Thevenin‟s Equivalent Input Circuit

76
This overall voltage gain Avs is given by

Avs = V2 / VS = V2V1 / V1VS = Av V1/ VS

From the equivalent input circuit using Thevenin‟s equivalent for the source shown in Fig. 5.6

V1 = VS Zi / (Zi + RS)

V1 / VS = Zi / ( Zi + RS)

Then, Avs= Av Zi / ( Zi + RS)

Substituting Av = AiZL / Zi

Avs= AiZL / ( Zi + RS)

Avs = AiZL RS / ( Zi + RS) RS

Avs = AisZL/ RS

Current Amplification (Ais) taking into account the source Resistance (RS)

Fig. Norton‟s Equivalent Input Circuit

The modified input circuit using Norton‟s equivalent circuit for the calculation of Ais is shown in Fig. 1.7
Overall Current Gain, Ais = -I2 / IS = - I2I1 /I1 IS = Ai I1/IS
From Fig. 1.7 I1= IS RS / (RS + Zi)
I1 / IS = RS / (RS + Zi)
and hence, Ais = Ai RS / (RS + Zi)

Operating Power Gain (AP)

The operating power gain AP of the transistor is defined as

77
 AP = P2 / P1 = -V2 I2 / V1 I1 = AvAi= AiAiZL/ Zi
AP = Ai2(ZL/ Zi)

Small Signal analysis of a transistor amplifier

Ai = - hf / ( 1+ ZL ho) Av = AiZL / Zi
Avs= Av Zi / ( Zi + RS) = AiZL / ( Zi + RS)
Zi = hi + hr A1ZL = hi - hfhr / (YL + ho)
= AisZL / RS
Yo= ho- hf hr/( RS + hi) = 1/ Zo Ais = Ai RS / (RS + Zi) = Avs = Ais RS/ ZL

Simplified common emitter hybrid model:

In most practical cases it is appropriate to obtain approximate values of AV , A ietc rather than calculating
exact values. How the circuit can be modified without greatly reducing the accuracy. Fig. shows the CE
amplifier equivalent circuit in terms of h-parameters Since 1 / hoe in parallel with RL is approximately
equal to RL if 1 / hoe>> RL then hoe may be neglected. Under these conditions.

Ic = hfeIB .

hrevc = hreIc RL = hrehfeIbRL .

Fig. CE amplifier equivalent circuit in terms of h-parameters

Since h [Link] = 0.01(approximately), this voltage may be neglected in comparison with h icIb drop across h
ie provided RL is not very large. If load resistance RL is small than hoe and hre can be neglected.

78
Output impedance seems to be infinite. When Vs = 0, and an external voltage is applied at the output we
fined Ib = 0, I C = 0. True value depends upon RS and lies between 40 K and 80K.

On the same lines, the calculations for CC and CB can be done.

Comparison of Transistor Amplifier Configuration

The characteristics of three configurations are summarized in Table .Here the quantities Ai,Av,Ri,Ro and
AP are calculated for a typical transistor whose h-parameters are given in table .The values of RL and Rs
are taken as 3KΩ.

Table: Performance schedule of three transistor configurations

Quantity CB CC CE
AI 0.98 47.5 -46.5
AV 131 0.989 -131
AP 128.38 46.98 6091.5
Ri 22.6 Ω 144 kΩ 1065 Ω
Ro 1.72 MΩ 80.5 Ω 45.5 kΩ

The values of current gain, voltage gain, input impedance and output impedance calculated as a
function of load and source impedances.

Characteristics of Common Base Amplifier

1. Current gain is less than unity and its magnitude decreases with the increase of load resistance RL,
2. Voltage gain AV is high for normal values of RL,
3. The input resistance Ri is the lowest of all the three configurations, and
4. The output resistance Ro is the highest of all the three configurations.

79
Applications: The CB amplifier is not commonly used for amplification purpose. It is used for

1. Matching a very low impedance source

2. As a non inverting amplifier to voltage gain exceeding unity.
3. For driving a high impedance load.
4. As a constant current source.

Characteristics of Common Collector Amplifier

 For low RL (< 10 kΩ), the current gain Ai is high and almost equal to that of a CE amplifier.
 The voltage gain AV is less than unity.
 The input resistance is the highest of all the three configurations.
 The output resistance is the lowest of all the three configurations.

Applications The CC amplifier is widely used as a buffer stage between a high impedance source and a
low impedance load.

Characteristics of Common Emitter Amplifier

 The current gain Ai is high for RL< 10 kΩ.

 The voltage gain is high for normal values of load resistance RL.
 The input resistance Riis medium.
 The output resistance Ro is moderately high.

Applications: CE amplifier is widely used for amplification.

Simplified common emitter hybrid model:

In most practical cases it is appropriate to obtain approximate values of AV , A ietc rather than calculating
exact values. How the circuit can be modified without greatly reducing the accuracy. Fig shows the CE
amplifier equivalent circuit in terms of h-parameters Since 1 / hoe in parallel with RL is approximately
equal to RL if 1 / hoe>> RL then hoe may be neglected. Under these conditions.

Ic = hfeIB .

hrevc = hreIc RL = hrehfeIbRL .

80
 Fig CE amplifier equivalent circuit

Since h [Link]» 0.01, this voltage may be neglected in comparison with h icIb drop across h ie provided RL is
not very large. If load resistance RL is small than hoe and hre can be neglected.

Output impedance seems to be infinite. When Vs = 0, and an external voltage is applied at the output we
fined Ib = 0, I C = 0. True value depends upon RS and lies between 40 K and 80K.

On the same lines, the calculations for CC and CB can be done.

Small Signal CE Amplifiers:

CE amplifiers are very popular to amplify the small signal ac. After a transistor has been biased with a Q
point near the middle of a dc load line, ac source can be coupled to the base. This produces fluctuations in
the base current and hence in the collector current of the same shape and frequency. The output will be
enlarged sine wave of same frequency.

The amplifier is called linear if it does not change the wave shape of the signal. As long as the input signal
is small, the transistor will use only a small part of the load line and the operation will be linear. On the
other hand, if the input signal is too large. The fluctuations along the load line will drive the transistor into
either saturation or cut off. This clips the peaks of the input and the amplifier is no longer linear.

The CE amplifier configuration is shown in fig.

81
 Fig. CE amplifier

The coupling capacitor (CC ) passes an ac signal from one point to another. At the same time it does not
allow the dc to pass through it. Hence it is also called blocking capacitor.

For example in fig., the ac voltage at point A is transmitted to point B. For this series reactance X C should
be very small compared to series resistance RS. The circuit to the left of A may be a source and a series
resistor or may be the Thevenin equivalent of a complex circuit. Similarly RL may be the load resistance
or equivalent resistance of a complex network. The current in the loop is given by

82
As frequency increases, decreases, and current increases until it reaches to its maximum value vin / R.
Therefore the capacitor couples the signal properly from A to B when XC<< R. The size of the coupling
capacitor depends upon the lowest frequency to be coupled. Normally, for lowest frequency X C0.1R is
taken as design rule.

The coupling capacitor acts like a switch, which is open to dc and shorted for ac. The bypass capacitor Cb
is similar to a coupling capacitor, except that it couples an ungrounded point to a grounded point. The C b
capacitor looks like a short to an ac signal and therefore emitter is said ac grounded. A bypass capacitor
does not disturb the dc voltage at emitter because it looks open to dc current. In a transistor amplifier, the
dc source sets up quiescent current and voltages. The ac source then produces fluctuations in these current
and voltages. The simplest way to analyze this circuit is to split the analysis in two parts: dc analysis and
ac analysis. One can use superposition theorem for analysis .

AC & DC Equivalent Circuits:

For dc equivalent circuit, reduce all ac voltage sources to zero and open all ac current sources and open all
capacitors. With this reduced circuit shown in fig. dc current and voltages can be calculated.

For ac equivalent circuits reduce dc voltage sources to zero and open current sources and short all
capacitors. This circuit is used to calculate ac currents and voltage as shown in fig..

83
The total current in any branch is the sum of dc and ac currents through that branch. The total voltage
across any branch is the sum of the dc voltage and ac voltage across that branch.

Phase Inversion:

Because of the fluctuation is base current; collector current and collector voltage also swings above and
below the quiescent voltage. The ac output voltage is inverted with respect to the ac input voltage,
meaning it is 180o out of phase with input.

During the positive half cycle base current increase, causing the collector current to increase. This
produces a large voltage drop across the collector resistor; therefore, the voltage output decreases and
negative half cycle of output voltage is obtained. Conversely, on the negative half cycle of input voltage
less collector current flows and the voltage drop across the collector resistor decreases, and hence
collector voltage increases we get the positive half cycle of output voltage as shown in fig.

84
AC Load line:

Consider the dc equivalent circuit as shown in figure.

Fig. 1

Assuming IC = IC (approx), the output circuit voltage equation can be written as

The slop of the d.c load line is.

When considering the ac equivalent circuit, the output impedance becomes RC || RL which is less than (RC
+RE).

In the absence of ac signal, this load line passes through Q point. Therefore ac load line is a line of slope
(-1 / ( RC || RL) ) passing through Q point. Therefore, the output voltage fluctuations will now be
corresponding to ac load line as shown in below figure. Under this condition, Q-point is not in the middle
of load line, therefore Q-point is selected slightly upward, means slightly shifted to saturation side.

85
Fig. AC & DC load line

86
 MODULE – IV

JUNCTION FIELD EFFECT TRANSISTOR

Construction, Principle of Operation, Pinch-Off Voltage, Volt- Ampere Characteristic, comparison

of BJT and FET, Biasing of FET, FET as Voltage Variable Resistor, MOSFET Construction and its
Characteristics in Enhancement and Depletion modes.

COURSE OUTCOMES (COs):

After successful completion of the course, students will be able to:

CO No Course Outcomes Knowledge Level
(Bloom’s Taxonomy)
CO 4 Demonstrate the constructional features and principle of operation of Understand
bipolar and uni-polar devices for distinguishing between cut off,
active and saturation regions of operation.
CO 5 Establish the relations of current gain, voltage gain of bipolar Understand
junction transistor and field effect transistor respectively using their
characteristics
CO 6 Analyse the input and output characteristics of transistor Analyze
configurations for determining the input - output resistances, current
gain and voltage gain.
CO 8 Examine DC and AC load line analysis of BJT and FET amplifiers for Analyze
optimal operating level regardless of input, load placed on the device.
CO 9 Design the various biasing techniques for BJT, JFET and MOSFETs Apply
amplifier circuits considering stability condition for establishing a
proper operating point.
CO 10 Compute the characteristic parameters of FET and MOSFETs in Apply
common source, common drain and common gate amplifiers using
the drain and the transfer characteristics.
CO 12 Design basic electronic circuits using active transistors Create
CO 13 Apply electronic circuits in global engineering applications Apply

INTRODUCTION

 The Field effect transistor is abbreviated as FET, it is another semiconductor device like a BJT
which can be used as an amplifier or switch.
 The Field effect transistor is a voltage operated device. Whereas Bipolar junction transistor is a
current controlled device. Unlike BJT a FET requires virtually no input current.
 This gives it an extremely high input resistance, which is its most important advantage over a
bipolar transistor.
87
 FET is also a three terminal device, labeled as source, drain and gate.
 The source can be viewed as BJT‟s emitter, the drain as collector, and the gate as the counter part
of the base.
 The material that connects the source to drain is referred to as the channel.
 FET operation depends only on the flow of majority carrier,therefore they are called unipolar
devices. BJT operation depends on both minority and majority carriers.
 As FET has conduction through only majority carriers it is less noisy than BJT.
 FETs are much easier to fabricate and are particularly suitable for ICs because they occupy less
space than BJTs.
 FET amplifiers have low gain bandwidth product due to the junction capacitive effects and
produce more signal distortion except for small signal operation.
 The performance of FET is relatively unaffected by ambient temperature changes. As it has a
negative temperature coefficient at high current levels, it prevents the FET from thermal
breakdown. The BJT has a positive temperature coefficient at high current levels which leads to
thermal breakdown.

CLASSIFICATION OF FET:

There are two major categories of field effect transistors:

1. Junction Field Effect Transistors

2. MOSFETs

These are further sub divided in to P- channel and N-channel devices.

MOSFETs are further classified in to two types Depletion MOSFETs and Enhancement. MOSFETs

When the channel is of N-type the JFET is referred to as an N-channel JFET,when the channel is of P-
type the JFET is referred to as P-channel JFET. The schematic symbols for the P-channel and N-
channel JFETs are shown in the figure.

88
CONSTRUCTION AND OPERATION OF N- CHANNEL FET

If the gate is an N-type material, the channel must be a P-type material.

CONSTRUCTION OF N-CHANNEL JFET

A piece of N- type material, referred to as channel has two smaller pieces of P-type material attached to
its sides, forming PN junctions. The channel ends are designated as the drain and source. And the two
pieces of P-type material are connected together and their terminal is called the gate. Since this channel is
in the N-type bar, the FET is known as N-channel JFET.

OPERATION OF N-CHANNEL JFET:-

The overall operation of the JFET is based on varying the width of the channel to control the drain
current. A piece of N type material referred to as the channel, has two smaller pieces of P type material
attached to its sites, farming PN –Junctions. The channel‟s ends are designated the drain and the source.
And the two pieces of P type material are connected together and their terminal is called the gate. With
the gate terminal not connected and the potential applied positive at the drain negative at the source a
drain current Id flows. When the gate is biased negative with respective to the source the PN junctions are
reverse biased and depletion regions are formed. The channel is more lightly doped than the P type gate
blocks, so the depletion regions penetrate deeply into the channel. Since depletion region is a region
depleted of charge carriers it behaves as an Insulator. The result is that the channel is narrowed. Its
resistance is increased and Id is reduced. When the negative gate bias voltage is further increased, the
depletion regions meet at the center and Id is cut off completely.

There are two ways to control the channel width

 By varying the value of Vgs

 And by Varying the value of Vds holding Vgs constant
89
By varying the value of Vgs :-

The width of the channel and in turn vary the amount of drain current. This can be done by varying the
value of Vgs. This point is illustrated in the fig below. Here we are dealing with N channel FET. So
channel is of N type and gate is of P type that constitutes a PN junction. This PN junction is always
reverse biased in JFET [Link] reverse bias is applied by a battery voltage Vgs connected between
the gate and the source terminal i.e positive terminal of the battery is connected to the source and negative
terminal to gate.

1. When a PN junction is reverse biased the electrons and holes diffuse across junction by leaving
immobile ions on the N and P sides, the region containing these immobile ions is known as
depletion regions.
2. If both P and N regions are heavily doped then the depletion region extends symmetrically on both
sides.
3. But in N channel FET P region is heavily doped than N type thus depletion region extends more in
N region than P region.
4. So when no Vds is applied the depletion region is symmetrical and the conductivity becomes Zero.
Since there are no mobile carriers in the junction.
5. As the reverse bias voltage is increases the thickness of the depletion region also increases. i.e. the
effective channel width decreases.
6. By varying the value of Vgs we can vary the width of the channel.

Varying the value of Vds holding Vgs constant :-

 When no voltage is applied to the gate i.e. Vgs=0 ,Vds is applied between source and drain the
electrons will flow from source to drain through the channel constituting drain current Id .
 With Vgs= 0 for Id= 0 the channel between the gate junctions is entirely open .In response to a
small applied voltage Vds , the entire bar acts as a simple semiconductor resistor and the current
Id increases linearly with Vds .
 This increasing drain current Id produces a voltage drop across rd which reverse biases the gate to
source junction,(rd>rs) .Thus the depletion region is formed which is not symmetrical .
 The depletion region i.e. developed penetrates deeper in to the channel near drain and less
towards source because Vrd>>Vrs. So reverse bias is higher near drain than at source.

90
  As a result growing depletion region reduces the effective width of the channel. Eventually a
voltage Vds is reached at which the channel is pinched off. This is the voltage where the current
Id begins to level off and approach a constant value.
 So, by varying the value of Vds we can vary the width of the channel holding Vgs constant.
When both Vgs and Vds is applied:-

In principle not possible for the channel to close Completely and there by reduce the current Id to Zero
for, if such indeed, could be the case the gate voltage Vgs is applied in the direction to provide additional
reverse bias

 When voltage is applied between the drain and source with a battery Vdd, the electrons flow
from source to drain through the narrow channel existing between the depletion regions. This
constitutes the drain current Id, its conventional direction is from drain to source.
 The value of drain current is maximum when no external voltage is applied between gate and
source and is designated by Idss.
 When Vgs is increased beyond Zero the depletion regions are widened. This reduces the
effective width of the channel and therefore controls the flow of drain current through the
channel.
 When Vgs is further increased a stage is reached at which to depletion regions touch each other
that means the entire channel is closed with depletion region. This reduces the drain current to
Zero.
CHARACTERISTICS OF N-CHANNEL JFET :-

The family of curves that shows the relation between current and voltage are known as characteristic
curves.

There are two important characteristics of a JFET.

1) Drain or VI Characteristics
2) Transfer characteristics
 Drain Characteristics:-

Drain characteristics shows the relation between the drain to source voltage Vds and drain current Id. In
order to explain typical drain characteristics let us consider the curve with Vgs= 0.V.

1. When Vds is applied and it is increasing the drain current ID also increases linearly up to knee
point.

91
 Fig: Drain Characteristics

2. This shows that FET behaves like an ordinary [Link] region is called as ohmic region.
3. ID increases with increase in drain to source voltage. Here the drain current is increased slowly as
compared to ohmic region.
4) It is because of the fact that there is an increase in VDS .This in turn increases the reverse bias
voltage across the gate source junction .As a result of this depletion region grows in size thereby
reducing the effective width of the channel.
5) All the drain to source voltage corresponding to point the channel width is reduced to a minimum
value and is known as pinch off.
6) The drain to source voltage at which channel pinch off occurs is called pinch off voltage(Vp).

PINCH OFF Region:

1. This is the region shown by the curve as saturation region.

2. It is also called as saturation region or constant current region. Because of the channel is
occupied with depletion region, the depletion region is more towards the drain and less
towards the source, so the channel is limited, with this only limited number of carriers are only
allowed to cross this channel from source drain causing a current that is constant in this region.
To use FET as an amplifier it is operated in this saturation region.
3. In this drain current remains constant at its maximum value IDSS.

92
 4. The drain current in the pinch off region depends upon the gate to source voltage and is given
by the relation

Id =Idss [1-Vgs/Vp]2

This is known as shokley‟s relation.

BREAKDOWN REGION:

The region is shown by the [Link] this region, the drain current increases rapidly as the drain to source
voltage is increased. It is because of the gate to source junction due to avalanche effect. The avalanche
break down occurs at progressively lower value of VDS because the reverse bias gate voltage adds to the
drain voltage thereby increasing effective voltage across the gate junction. This causes the maximum
saturation drain current is smaller, the ohmic region portion decreased.
It is important to note that the maximum voltage VDS which can be applied to FET is the lowest voltage
which causes available break down.

TRANSFER CHARACTERISTICS:

These curves shows the relationship between drain current ID and gate to source voltage VGS for
different values of VDS.

i) First adjust the drain to source voltage to some suitable value, then increase the gate to source
voltage in small suitable value.
ii) Plot the graph between gate to source voltage along the horizontal axis and current ID on the
vertical axis. We shall obtain a curve like this.
iii) As we know that if Vgs is more negative curves drain current to reduce . where V gs is made
sufficiently negative, Id is reduced to zero. This is caused by the widening of the depletion region to a
point where it is completely closes the channel. The value of V gs at the cutoff point is designed as
Vgsoff
iv) The upper end of the curve as shown by the drain current value is equal to Idss that is when Vgs = 0
the drain current is maximum.
v) While the lower end is indicated by a voltage equal to Vgsoff
vi) If Vgs continuously increasing, the channel width is reduced, then Id =0
It may be noted that curve is part of the parabola; it may be expressed as
Id=Idss[1-Vgs/Vgsoff]2

93
 Fig: The relationship between drain current ID and gate to source voltage VGS

DIFFERENCE BETWEEN Vp AND Vgsoff –

Vp is the value of Vgs that causes the JFET to become constant current component, It is measured at V gs
=0V and has a constant drain current of Id =Idss .WhereVgsoff is the value of Vgs that reduces Id to
approximately zero.

Why the gate to source junction of a JFET be always reverse biased.

The gate to source junction of a JFET is never allowed to become forward biased because the gate
material is not designed to handle any significant amount of current. If the junction is allowed to become
forward biased, current is generated through the gate material. This current may destroy the component.

There is one more important characteristic of JFET reverse biasing i.e. J FET „s have extremely high
characteristic gate input impedance. This impedance is typically in the high mega ohm range. With the
advantage of extremely high input impedance it draws no current from the source. The high input
impedance of the JFET has led to its extensive use in integrated circuits. The low current requirements of
the component makes it perfect for use in ICs. Where thousands of transistors must be etched on to a
single piece of silicon. The low current draw helps the IC to remain relatively cool, thus allowing more
components to be placed in a smaller physical area.

JFET PARAMETERS

The electrical behavior of JFET may be described in terms of certain parameters. Such parameters are
obtained from the characteristic curves.

A C Drain resistance (rd):

94
It is also called dynamic drain resistance and is the [Link] between the drain and source terminal,
when the JFET is operating in the pinch off or saturation region. It is given by the ratio of small change in
drain to source voltage ∆Vdsto the corresponding change in drain current ∆Id for a constant gate to
source voltage Vgs.

Mathematically it is expressed as rd=∆Vds/ ∆Id where Vgsis held constant.

TRANCE CONDUCTANCE (gm):

It is also called forward transconductance. It is given by the ratio of small change in drain current (∆Id) to
the corresponding change in gate to source voltage (∆Vds)

Mathematically the transconductance can be written as

gm=∆Id/∆Vds

AMPLIFICATION FACTOR (µ)

It is given by the ratio of small change in drain to source voltage (∆Vds) to the corresponding change in
gate to source voltage (∆Vgs)for a constant drain current (Id).

Thus µ=∆Vds/∆Vgs when Id held constant

The amplification factor µ may be expressed as a product of transconductance (gm)and ac drain resistance
(rd)

µ=∆Vds/∆Vgs=gmrd

THE FET SMALL SIGNAL MODEL:

The linear small signal equivalent circuit for the FET can be obtained in a manner similar to that used to
derive the corresponding model for a transistor. We can express the drain current iD as a function f of the
gate voltage and drain voltage Vds.

Id =f(Vgs,Vds)------------------(1)

The transconductance gm and drain resistance rd:-

If both gate voltage and drain voltage are varied, the change in the drain current is approximated by using
taylors series considering only the first two terms in the expansion

95
 ∆id= |vds=constant .∆vgs |vgs=constant∆vds

we can write ∆id=id

∆vgs=vgs

∆vds=vds

Id=gm v Vds→(1)

Where gm= |Vds |Vds

gm= |Vds

Is the mutual conductance or transconductance. It is also called as common source forward conductance .

The second parameter rd is the drain resistance or output resistance is defined as

rd= |Vgs |Vgs= |Vgs

rd= |Vgs

The reciprocal of the rd is the drain conductance gd .It is also designated by Yos and Gos and called the
common source output conductance. So the small signal equivalent circuit for FET can be drawn in two
different ways.

[Link] signal current –source model

[Link] signal voltage-source model.

These small signal models for FET can be used for analyzing the three basic FET amplifier
configurations:

[Link] source (CS)

[Link] drain (CD) or source follower

3. common gate(CG).

96
MOSFET:

The insulated gate FET or metal oxide semiconductor FET which is having the greater commercial
importance than the junction FET. Most MOSFETS however are triodes, with the substrate internally
connected to the source. The circuit symbols used by several manufacturers are indicated in the Fig
below.

Fig: Enhancement type MOSFET

Here are two basic types of MOSFETS

(1) Depletion type (2) Enhancement type MOSFET.

D-MOSFETS can be operated in both the depletion mode and the enhancement mode. E MOSFETS
are restricted to operate in enhancement mode. The primary difference between them is their physical
construction.

The E MOSFET on the other hand has no such channel physically. It depends on the gate voltage to form
a channel between the source and the drain terminals. Both MOSFETS have an insulating layer between
the gate and the rest of the component. This insulating layer is made up of SIO 2 a glass like insulating
material. The gate material is made up of metal conductor .Thus going from gate to substrate, we can
have metal oxide semiconductor which is where the term MOSFET comes from. Since the gate is
insulated from the rest of the component, the MOSFET is sometimes referred to as an insulated gate FET
or IGFET. The foundation of the MOSFET is called the substrate. This material is represented in the
schematic symbol by the center line that is connected to the source. In the symbol for the MOSFET, the
arrow is placed on the substrate. As with JFET an arrow pointing in represents an N-channel device, while
an arrow pointing out represents p-channel device.

97
CONSTRUCTION OF AN N-CHANNEL MOSFET:

The N- channel MOSFET consists of a lightly doped p type substance into which two heavily doped n+
regions are diffused as shown in the Fig. These n+ sections, which will act as source and drain. A thin
layer of insulation silicon dioxide (SIO2) is grown over the surface of the structure, and holes are cut into
oxide layer, allowing contact with the source and drain. Then the gate metal area is overlaid on the oxide,
covering the entire channel region. Metal contacts are made to drain and source and the contact to the
metal over the channel area is the gate terminal. The metal area of the gate, in conjunction with the
insulating dielectric oxide layer and the semiconductor channel, forms a parallel plate capacitor. The
insulating layer of sio2. Is the reason why this device is called the insulated gate field effect transistor.
This layer results in an extremely high input resistance (10 10 to 10power 15ohms) for MOSFET.

DEPLETION MOSFET

The basic structure of D –MOSFET is shown in the fig. An N-channel is diffused between source and
drain with the device an appreciable drain current IDSS flows foe zero gate to source voltage, Vgs=0.

Depletion mode operation:-

1) The above fig shows the D-MOSFET operating conditions with gate and source terminals shorted
together(VGS=0V)
2) At this stage ID= IDSS where VGS=0V, with this voltage VDS, an appreciable drain current IDSS
flows.
3) If the gate to source voltage is made negative i.e. VGs is [Link] charges are induced in
the channel through the SIO2 of the gate capacitor.
4) Since the current in a FET is due to majority carriers(electrons for an N-type material) , the induced
positive charges make the channel less conductive and the drain current drops as Vgs is made more
negative.
5) The re distribution of charge in the channel causes an effective depletion of majority carriers ,
which accounts for the designation depletion MOSFET.
6) That means biasing voltage Vgs depletes the channel of free carriers This effectively reduces the
width of the channel, increasing its resistance.
Enhancement mode operation of the D-MOSFET:

 This operating mode is a result of applying a positive gate to source voltage Vgs to the device.
 When Vgs is positive the channel is effectively widened. This reduces the resistance of the
channel allowing ID to exceed the value of IDSS

98
  When Vgs is given positive the majority carriers in the p-type are holes. The holes in the p type
substrate are repelled by the +ve gate voltage.
 At the same time, the conduction band electrons (minority carriers) in the p type material are
attracted towards the channel by the +gate voltage.
 With the build up of electrons near the channel , the area to the right of the physical channel
effectively becomes an N type material.
 The extended n type channel now allows more current, Id>Idss

Fig: Depletion mode operation of the D-MOSFET

Characteristics of Depletion MOSFET:

The fig. shows the drain characteristics for the N channel depletion type MOSFET

1) The curves are plotted for both Vgs positive and Vgs negative voltages
2) When Vgs=0 and negative the MOSFET operates in depletion mode when Vgs is positive ,the
MOSFET operates in the enhancement mode.
3) The difference between JFET and D MOSFET is that JFET does not operate for positive values of
Vgs.
4) When Vds=0, there is no conduction takes place between source to drain, if Vgs<0 and Vds>0
then Id increases linearly.
5) But as Vgs,0 induces positive charges holes in the channel, and controls the channel width. Thus
the conduction between source to drain is maintained as constant, i.e. Id is constant.
6) If Vgs>0 the gate induces more electrons in channel side, it is added with the free electrons
generated by source. again the potential applied to gate determines the channel width and
maintains constant current flow through it as shown in Fig

99
TRANSFER CHARACTERISTICS:

The combination of 3 operating states i.e. Vgs=0V, VGs<0V, Vgs>0V is represented by the D
MOSFET transconductance curve shown in Fig.

 Here in this curve it may be noted that the region AB of the characteristics similar to that of JFET.
 This curve extends for the positive values of Vgs
 Note that Id=Idss for Vgs=0V when Vgs is negative,Id<Idss when Vgs= Vgs(off) ,Id is reduced to
approximately [Link] is positive Id>[Link] obviously Idss is not the maximum possible
value of Id for a MOSFET.
 The curves are similar to JFET so thet the D MOSFET have the same transconductance equation.

APPLICATION OF MOSFET

One of the primary contributions to electronics made by MOSFETs can be found in the area of digital
(computer electronics). The signals in digital circuits are made up of rapidly switching dc levels. This
signal is called as a rectangular wave,made up of two dc levels (or logic levels). These logic levels are 0V
and +5V.

A group of circuits with similar circuitry and operating characteristics is referred to as a logic family. All
the circuits in a given logic family respond to the same logic levels, have similar speed and power-
handling capabilities, and can be directly connected together. One such logic family is complementary
MOS (or CMOS) logic. This logic family is made up entirely of MOSFETs.

BIASING FET:

For the proper functioning of a linear FET amplifier, it is necessary to maintain the operating point Q
stable in the central portion of the pinch off region The Q point should be independent of device
parameter variations and ambient temperature variations

This can be achieved by suitably selecting the gate to source voltage VGS and drain current ID which is
referred to as biasing. JFET biasing circuits are very similar to BJT biasing circuits. The main difference
between JFET circuits and BJT circuits is the operation of the active components themselves

There are mainly two types of Biasing circuits

1. Self bias
2. Voltage divider bias.

100
SELF BIAS
Self bias is a JFET biasing circuit that uses a source resistor to help reverse bias the JFET gate. A self
bias circuit is shown in the fig. Self bias is the most common type of JFET bias. This JFET must be
operated such that gate source junction is always reverse biased. This condition requires a negative VGS
for an N channel JFET and a positive VGS for P channel JFET. This can be achieved using the self bias
arrangement as shown in Fig. The gate resistor RG doesn‟t affect the bias because it has essentially no
voltage drop across it, the gate remains at 0V .RG is necessary only to isolate an ac signal from ground in
amplifier applications. The voltage drop across resistor RS makes gate source junction reverse biased.

For the dc analysis coupling capacitors are open circuits produces a voltage drop across RS and makes the
source positive w.r.t ground. In any JFET circuit all the source current passes through the device to the
drain circuit. This is due to the fact that there is no significant gate current. We can define source current
as IS = ID

(VG =0 because there is no gate current flowing in RG So VG across RG is zero)

VG =0 then VS= ISRS =ID RS

VGS = VG-VS =0-ID RS=- ID RS

DC analysis of self Bias:

In the following DC analysis, the N channel J FET shown in the fig. is used for illustration.

For DC analysis we can replace coupling capacitors by open circuits and we can also replace the resistor
RG by a short circuit equivalent.:. IG = [Link] relation between ID and VGS is given by

Id=Idss[1- ]2

VGS for N channel JFET is =-id Rs

101
Substuting this value in the above equation

Id=Idss[1- ]2

Id=Idss[1+ ]2

For the N-chanel FET in the above figure

Is produces a voltage drop across Rs and makes the source positive w.r.t ground in any JFET circuit all the

source current passes through the device to drain circuit this is due to the fact that there is no significant gate
current. Therefore we can define source current as Is=Id and Vg=0 then

Vs= Is Rs =IdRs

Vgs=Vg-Vs=0-IdRs=-IdRs

Drawing the self biasline:

Typical transfer characteristics for a self biased JFET are shown in the fig.

The maximum drain current is 6mA and the gate source cut off voltage is -3V. This means the gate
voltage has to be between 0 and -3V.

Now using the equation VGS = -IDRS and assuming RS of any suitable value we can draw the self bias
line.

Let us assume RS = 500Ω

With this Rs , we can plot two points corresponding to ID = 0 and Id = IDSS

for ID = 0
102
 VGS = -ID RS

VGS = 0X (500.Ω) = 0V

So the first point is (0 ,0)

( Id, VGS)

For ID= IDSS=6mA

VGS = (-6mA) (500 Ω) = -3V

So the 2nd Point will be (6mA,-3V)

By plotting these two points, we can draw the straight line through the points. This line will intersect the
transconductance curve and it is known as self bias [Link] intersection point gives the operating point of
the self bias JFET for the circuit.

At Q point , the ID is slightly > than 2mA and VGS is slightly > -1V. The Q point for the self bias JFET
depends on the value of [Link] Rs is large, Q point far down on the transconductance curve ,ID is small,
when Rs is small Q point is far up on the curve , ID is large.

VOLTAGE DIVIDER BIAS:

The fig. shows N channel JFET with voltage divider bias. The voltage at the source of JFET must be more
positive than the voltage at the gate in order to keep the gate to source junction reverse biased. The source
voltage is

VS = IDRS

The gate voltage is set by resistors R1 and R2 as expressed by the following equation using the voltage
divider formula.

Vg= Vdd

103
For dc analysis

Applying KVL to the input circuit

VG-VGS-VS =0

:: VGS = VG-Vs=VG-ISRS

VGS = VG-IDRS :: IS = ID

Applying KVL to the input circuit we get

VDS+IDRD+VS-VDD =0

::VDS = VDD-IDRD-IDRS

VDS = VDD-ID ( RD +RS )

The Q point of a JFET amplifier , using the voltage divider bias is

IDQ = IDSS [1-VGS/VP]2

VDSQ = VDD-ID ( RD+RS )

COMPARISON OF MOSFET WITH JFET

1. In enhancement and depletion types of MOSFET, the transverse electric field induced across an
insulating layer deposited on the semiconductor material controls the conductivity of the
channel.

2. In the JFET the transverse electric field across the reverse biased PN junction controls the
conductivity of the channel.
104
3. The gate leakage current in a MOSFET is of the order of 10-12A. Hence the input resistance of a
MOSFET is very high in the order of 1010 to 1015 Ω. The gate leakage current of a JFET is of
the order of 10-9A., and its input resistance is of the order of 108Ω.

4. The output characteristics of the JFET are flatter than those of the MOSFET, and hence the
drain resistance of a JFET (0.1 to 1MΩ) is much higher than that of a MOSFET (1 to 50kΩ).

5. JFETs are operated only in the depletion mode. The depletion type MOSFET may be operated in
both depletion and enhancement mode.

6. Comparing to JFET, MOSFETs are easier to fabricate.

7. Special digital CMOS circuits are available which involve near zero power dissipation and very
low voltage and current requirements. This makes them suitable for portable systems.

105
 MODULE – V

FET AMPLIFIERS

Small Signal Model, Analysis of CS, CD, CG JFET Amplifiers. Basic Concepts of MOSFET
Amplifiers.
Special Purpose Devices: Zener Diode - Characteristics, Voltage Regulator; Principle of Operation -
SCR, Tunnel diode, UJT, Varactor Diode.

COURSE OUTCOMES (COs):

After successful completion of the course, students will be able to:

CO No Course Outcomes Knowledge Level
(Bloom’s Taxonomy)
CO 7 Estimate the characteristic parameters of BJT, FET amplifier Evaluate
circuits using low frequency model.
CO 11 Demonstrate the working principle of special purpose Understand
semiconductor diodes and transistors for triggering and voltage
regulation applications.
CO 12 Design basic electronic circuits using active transistors Create
CO 13 Apply electronic circuits in global engineering applications Apply

INTRODUCTION
Field Effect Transistor (FET) amplifiers provide an excellent voltage gain and high input impedance.
Because of high input impedance and other characteristics of JFETs they are preferred over BJTs for
certain types of applications.
There are 3 basic FET circuit configurations:
i)Common Source
ii)Common Drain
iii)Common Gain
Similar to BJT CE,CC and CB circuits, only difference is in BJT large output collector current is
controlled by small input base current whereas FET controls output current by means of small input
voltage. In both the cases output current is controlled variable. FET amplifier circuits use voltage
controlled nature of the JFET. In Pinch off region, ID depends only on VGS.

106
Common Source (CS) Amplifier

Fig. (a) CS Amplifier (b) Small-signal equivalent circuit

A simple Common Source amplifier is shown in Fig. (a) Associated small signal equivalent circuit using
voltage-source model of FET is shown in Fig. (b)
Voltage Gain
Source resistance (RS) is used to set the Q-Point but is bypassed by CS for mid-frequency operation. From
the small signal equivalent circuit , the output voltage
VO = -RDµVgs(RD + rd)
Where Vgs= Vi , the input voltage,
Hence, the voltage gain,
AV = VO / Vi = -RDµ(RD + rd)
Input Impedance
From Fig. Input Impedance is
Zi = RG
For voltage divider bias as in CE Amplifiers of BJT
RG= R1 ║ R2
Output Impedance
Output impedance is the impedance measured at the output terminals with the input voltage VI = 0
From the Fig. when the input voltage Vi = 0, Vgs= 0 and hence
µ Vgs = 0
The equivalent circuit for calculating output impedance is given in Fig.
Output impedance Zo= rd ║ RD
Normally rd will be far greater than RD . Hence Zo ≈ RD

107
Common Drain Amplifier
A simple common drain amplifier is shown in Fig. and associated small signal equivalent circuit using
the voltage source model of FET is shown in Fig. Since voltage Vgd is more easily determined than Vgs,
the voltage source in the output circuit is expressed in terms of Vgs and Thevenin‟s theorem.

Fig. (a)CD Amplifier Fig (b)Small-signal equivalent circuit

Voltage Gain
The output voltage,
VO = RSµVgd / (µ + 1) RS + rd
Where Vgd = Vi the input voltage.
Hence, the voltage gain,
Av = VO / Vi = RSµ / (µ + 1) RS + rd

Input Impedance
From Fig. Input Impedance Zi = RG

Output Impedance
From Fig., Output impedance measured at the output terminals with input voltage Vi = 0 can be calculated
from the following equivalent circuit.
As Vi = 0: Vgd = 0: µvgd / (µ + 1) = 0
Output Impedance
ZO = rd / (µ + 1) ║RS
When µ » 1
ZO = ( rd / µ) ║RS = (1/gm) ║RS

108
BIASING FET:-

For the proper functioning of a linear FET amplifier, it is necessary to maintain the operating point Q
stable in the central portion of the pinch off region The Q point should be independent of device
parameter variations and ambient temperature variations

This can be achieved by suitably selecting the gate to source voltage VGS and drain current ID which is
referred to as biasing. JFET biasing circuits are very similar to BJT biasing circuits. The main difference
between JFET circuits and BJT circuits is the operation of the active components themselves

There are mainly two types of Biasing circuits

1. Self bias
2. Voltage divider bias.

SELF BIAS:-

Self bias is a JFET biasing circuit that uses a source resistor to help reverse bias the JFET gate.

A self bias circuit is shown in the fig

Self bias is the most common type of JFET bias. This JFET must be operated such that gate source
junction is always reverse biased. This condition requires a negative VGS for an N channel JFET and a
positive VGS for P channel JFET. This can be achieved using the self bias arrangement as shown in Fig.
The gate resistor RG doesn‟t affect the bias because it has essentially no voltage drop across it, the gate
remains at 0V. RG is necessary only to isolate an ac signal from ground in amplifier applications. The
voltage drop across resistor RS makes gate source junction reverse biased.

109
DC analysis of self Bias:-

In the following DC analysis, the N channel J FET shown in the fig. is used for illustration. For DC
analysis we can replace coupling capacitors by open circuits and we can also replace the resistor RG by
a short circuit equivalent.

IG = 0

The relation between ID and VGS is given by

Id=Idss[1- ]2

VGS for N channel JFET is =-id Rs

Substuting this value in the above equation

Id=Idss[1- ]2

Id=Idss[1+ ]2

For the N-chanel FET in the above figure

Is produces a voltage drop across Rs and makes the source positive w.r.t ground. in any JFET circuit all the

source current passes through the device to drain circuit this is due to the fact that there is no significant gate

current therefore we can define source current as Is=Id and Vg=0 then

Vs= Is Rs =IdRs

Vgs=Vg-Vs=0-IdRs=-IdRs

Now using the equation VGS = -IDRS and assuming RS of any suitable value we can draw the self bias
line.

Let us assume RS = 500Ω

With this Rs , we can plot two points corresponding to ID = 0 and Id = IDSS

for ID = 0

VGS = -ID RS

VGS = 0X (500.Ω) = 0V
110
 So the first point is (0 ,0)

( Id, VGS)

For ID= IDSS=6mA

VGS = (-6mA) (500 Ω) = -3V

So the 2nd Point will be (6mA,-3V)

By plotting these two points, we can draw the straight line through the points. This line will intersect the
transconductance curve and it is known as self-bias line. The intersection point gives the operating point
of the self-bias JFET for the circuit.

At Q point, the ID is slightly > than 2mA and VGS is slightly > -1V. The Q point for the self-bias JFET
depends on the value of [Link] Rs is large, Q point far down on the transconductance curve, ID is small,
when Rs is small Q point is far up on the curve , ID is large.

VOLTAGE DIVIDER BIAS:

The fig shows N channel JFET with voltage divider bias. The voltage at the source of JFET must be more
positive than the voltage at the gate in order to keep the gate to source junction reverse biased. The source
voltage is

VS = IDRS

The gate voltage is set by resistors R1 and R2 as expressed by the following equation using the voltage
divider formula.

111
 Vg= Vdd

Applying KVL to the input circuit

VG-VGS-VS =0

:: VGS = VG-Vs=VG-ISRS

VGS = VG-IDRS :: IS = ID

Applying KVL to the input circuit we get

VDS+IDRD+VS-VDD =0

::VDS = VDD-IDRD-IDRS, VDS = VDD-ID ( RD +RS )

The Q point of a JFET amplifier , using the voltage divider bias is

IDQ = IDSS [1-VGS/VP]2

VDSQ = VDD-ID ( RD+RS )

When the variation of the rd with VGS can be closely approximated by the expression

rd= ) Where ro = drain resistance at zero gate bias.K = a constant, dependent upon FET
type.

Zener Diode – Characteristics

A basic semiconductor diode can operate in forward bias but it cannot conduct during reverse bias. The
special type of diode that can conduct in reverse bias is referred to as a Zener diode. This diode can
conduct in forward bias just like a normal diode. The junction for the Zener diode will be heavily doped.
Because of this reason, it can work as normally as a basic junction in forwarding bias and can tolerate the
reverse currents during reverse bias. The main purpose of it is to use in stabilizers.

A diode in which the flow of current is from anode to cathode and cathode to anode defining that it has
the capacity of conducting in both forward and reverse biases are referred to a Zener diode.

Symbol of Zener Diode

112
Working Principle:

The condition of the diode with basic p-n as its junction during reverse bias is that there is no chance of
conduction because the depletion region width is comparatively high. As the applied reverse voltage tends
to increase that result in the increment of the width of the depletion region. Even there exist some
minority carriers which gain some energy because of increment of reverse voltage.

Due to the gain in kinetic energy of the minority carriers, these free electrons in movement collide with
the stationary ions. This results in the formation of more free electrons. Further, these again collide with
remaining stationary ions and this process continues it is referred to as carrier multiplication. Because of
carrier multiplication, a huge multiple of free electrons are created and the complete region of the diode
becomes conductive resulting in the breakdown known as avalanche breakdown.

Generally, this is not the case in the Zener diode. In Zener diode, the junction is doped with the highest
concentration. Because of this reason when the reverse voltage has applied the width of the depletion
region tends to minimize. As there exist the maximum concentration of the impure atoms in it. It creates
the maximum number of ions in it. As soon as the diode exceeds the threshold value the electrons that are
in the covalent bonds tend to come out in the depletion region so that it can make depletion region
conductive.

Hence this type of breakdown is referred to as Zener breakdown. The occurrence of this breakdown will
be at certain voltage termed as Zener voltage. Just as cut in voltage in normal diode here it is Zener
voltage. Once the applied voltage exceeds the value of voltage it tends to conduct. This value of the Zener
voltage is properly adjusted at the time of manufacturing by the proper concentration in doping.

In case of occurring of break down further, there is no possibility of occurrence of avalanche breakdown.
This is the principle lying behind the functioning of the diode.

The circuit for this type of diode is very simple. One has to connect the highly doped junction in reverse
bias. The circuit can be represented as follows.

113
Characteristics

The graphical representation can give basic characteristics. These are normally termed as V-I
characteristics.

Zener Diode V-I Characteristics Curve

As per the above analysis, it is evident that during forwarding bias Zener diode characteristics will remain
the same as that of the normal diode. Whereas after the applied voltage crosses the value of Zener voltage
(Vz ) the Zener breakdown takes place. After the breakdown, the flow of the current in the circuit tends to
increase immediately.

Zener Diode as Voltage Regulators

The function of a regulator is to provide a constant output voltage to a load connected in parallel with it in
spite of the ripples in the supply voltage or the variation in the load current and the zener diode will
continue to regulate the voltage until the diodes current falls below the minimum IZ(min) value in the
reverse breakdown region. It permits current to flow in the forward direction as normal, but will also
allow it to flow in the reverse direction when the voltage is above a certain value - the breakdown voltage
known as the Zener voltage. The Zener diode specially made to have a reverse voltage breakdown at a
specific voltage. Its characteristics are otherwise very similar to common diodes. In breakdown the
voltage across the Zener diode is close to constant over a wide range of currents thus making it useful as a
shunt voltage regulator.

The purpose of a voltage regulator is to maintain a constant voltage across a load regardless of variations
in the applied input voltage and variations in the load current. A typical Zener diode shunt regulator is
shown in Figure. The resistor is selected so that when the input voltage is at Vin (min) and the load current
is at IL(max) that the current through the Zener diode is at least Iz(min). Then for all other combinations
of input voltage and load current the Zener diode conducts the excess current thus maintaining a constant

114
voltage across the load. The Zener conducts the least current when the load current is the highest and it
conducts the most current when the load current is the lowest.

Fig: Zener diode shunt regulator

If there is no load resistance, shunt regulators can be used to dissipate total power through the series
resistance and the Zener diode. Shunt regulators have an inherent current limiting advantage under load
fault conditions because the series resistor limits excess current.

A zener diode of break down voltage Vz is reverse connected to an input voltage source Vi across a load
resistance RL and a series resistor RS. The voltage across the zener will remain steady at its break down
voltage VZ for all the values of zener current IZ as long as the current remains in the break down region.
Hence a regulated DC output voltage V0 = VZ is obtained across RL, whenever the input voltage remains
within a minimum and maximum voltage.

Basically there are two type of regulations such as:

a) Line Regulation
In this type of regulation, series resistance and load resistance are fixed, only input voltage is changing.
Output voltage remains the same as long as the input voltage is maintained above a minimum value.

Percentage of line regulation can be calculated by =

Where V0 is the output voltage and VIN is the input voltage and ΔV0 is the change in output voltage for a
particular change in input voltage ΔVIN.

b) Load Regulation

In this type of regulation, input voltage is fixed and the load resistance is varying. Output volt remains
same, as long as the load resistance is maintained above a minimum value.
Percentage of load regulation =

115
where VNL is the null load resistor voltage (ie. remove the load resistance and measure the voltage across
the Zener Diode) and VFL is the full load resistor voltage

Calculating voltage and current

The total current drawn from the source is the same as that through the series resistor

The current through the load resistor is

and the zener diode current is

If the voltage source is greater than Vz

If the voltage source is less than Vz

Zener Breakdown vs Avalanche Breakdown

The main difference between Zener breakdown and avalanche breakdown is their mechanism of
occurrence. Zener breakdown occurs because of the high electric field whereas, the avalanche breakdown
occurs because of the collision of free electrons with atoms. Both these breakdowns can occur
simultaneously. Let us look at the other differences between them in the below table.
Zener Breakdown Avalanche Breakdown
The process in which the electrons move across The process of applying high voltage and increasing
the barrier from the valence band of p-type the free electrons or electric current in
material to the conduction band of n-type material semiconductors and insulating materials is called an
is known as Zener breakdown. avalanche breakdown.
This is observed in Zener diodes having a Zener This is observed in Zener diode having a Zener
breakdown voltage Vz of 5 to 8 volts. breakdown voltage Vz greater than 8 volts.
116
The valence electrons are pulled into conduction The valence electrons are pushed to conduction due
due to the high electric field in the narrow to the energy imparted by accelerated electrons,
depletion region. which gain their velocity due to their collision with
other atoms.
The increase in temperature decreases the The increase in temperature increases the
breakdown voltage. breakdown voltage.
The VI characteristics of a Zener breakdown has a The VI characteristic curve of the avalanche
sharp curve. breakdown is not as sharp as the Zener breakdown.
It occurs in diodes that are highly doped. It occurs in diodes that are lightly doped.

SCR : Silicon Controlled Rectifier

The Silicon Controlled Rectifier (SCR) is a unidirectional device that allows the current in one direction
and opposes in another direction. SCR can be used for different applications like rectification, regulation
of power and inversion, etc. Like a diode.

SCR is a three terminal device; anode, cathode and gate as shown in figure. SCR has built in feature to
turn ON or OFF and its switching is controlled by biasing conditions and gate input terminal. This results
in varying the average power delivered at the load, by varying the ON periods of the SCR. It can handle
several thousands of voltages and currents. SCR symbol and its terminals are shown in figure.

Construction of Silicon Controlled Rectifier

The SCR is a four layer and three terminal device. The four layers made of P and N layers, are arranged
alternately such that they form three junctions J1, J2 and J3. These junctions are either alloyed or diffused
based on the type of construction.
The outer layers (P and N-layers) are heavily doped whereas middle P and N-layers are lightly doped. The
gate terminal is taken at the middle P-layer, anode is from outer P- layer and cathode is from N- layer
terminals. The SCR is made of silicon because compared to germanium leakage current in silicon is very
small.

117
Working or Modes of Operation of SCR
Depending on the biasing given to the SCR, the operation of SCR is divided into three modes. They are
1. Forward blocking Mode
2. Forward Conduction Mode and
3. Reverse Blocking Mode

Forward Blocking Mode

In this mode of operation, the Silicon Controlled Rectifier is connected such that the anode terminal is
made positive with respect to cathode while the gate terminal kept open. In this state junctions J1 and J3
are forward biased and the junction J2 reverse biased.
Due to this, a small leakage current flows through the SCR. Until the voltage applied across the SCR is
more than the break over voltage of it, SCR offers a very high resistance to the current flow. Therefore,
the SCR acts as a open switch in this mode by blocking forward current flowing through the SCR as
shown in the VI characteristics curve of the SCR.

Forward Conduction Mode

In this mode, SCR or thyristor comes into the conduction mode from blocking mode. It can be done in
two ways as either by applying positive pulse to gate terminal or by increasing the forward voltage (or
voltage across the anode and cathode) beyond the break over voltage of the SCR. Once any one of these
methods is applied, the avalanche breakdown occurs at junction J2. Therefore the SCR turns into
conduction mode and acts as a closed switch thereby current starts flowing through it.
In the VI characteristic figure, if the gate current value is high, the minimum will be the time to come in
conduction mode as Ig3 > Ig2 > Ig1. In this mode, maximum current flows through the SCR and its value
depends on the load resistance or impedance. It is also noted that if gate current is increasing, the voltage
required to turn ON the SCR is less if gate biasing is preferred. The current at which the SCR turns into
conduction mode from blocking mode is called as latching current (IL). And also when the forward
current reaches to level at which the SCR returns to blocking state is called as holding current (IH). At
this holding current level, depletion region starts to develop around junction J2. Hence the holding current
is slightly less than the latching current.

118
Reverse Blocking Mode
In this mode of operation, cathode is made positive with respect to anode. Then the junctions J1 and J3
are reverse biased and J2 is forward biased. This reverse voltage drives the SCR into reverse blocking
region results to flow a small leakage current through it and acts as an open switch as shown in figure. So,
the device offers a high impedance in this mode until the voltage applied is less than the reverse
breakdown voltage VBR of the SCR. If the reverse applied voltage is increased beyond the VBR, then
avalanche breakdown occurs at junctions J1 and J3 which results to increase reverse current flow through
the SCR. This reverse current causes more losses in the SCR and even to increase the heat of it. So there
will be a considerable damage to the SCR when the reverse voltage applied more than VBR.

Two Transistor Analogy of SCR

The two transistor analogy or two transistor model of SCR expresses the easiest way to understand the
working of SCR by visualizing it as a combination of two transistors as shown in figure. The collector of
each transistor is connected to the base of the other transistor.
The load resistance is connected between the anode and cathode terminals and a small voltage is applied
at the gate and cathode terminals. When there is no gate voltage, the transistor 2 is in cut-off mode due to
zero base current. Therefore, no current flows through the collector and hence the base of transistor T1.
Hence, both transistors are open circuited and thereby no current flows through the load.
When a particular voltage is applied between the gate and cathode, a small base current flows through the
base of the transistor 2 and thereby collector current will increase. And hence the base current at the
transistor T1 drives the transistor into saturation mode and thus load current will flow from anode to
cathode. From the above figure the base current of transistor T2 becomes the collector current of
transistor T1 and vice-versa.

119
UNI JUNCTION TRANSISTOR (UJT)

Another device whose construction is similar to that of the FET is shown in the figure.

It is a three terminal device, having two [Link] consists of a slab of lightly doped N-type silicon
material. The two base contacts are attached to both ends of this N-type surface. These are denoted as B1
and B2 respectively. A P-type material is used to form a pn junction at the boundary of the aluminium rod
and N-type slab. The N-type is lightly doped while P-type is heavily doped. That is N-type provides high
resistivity and P-type provides low resistivity.

This device was originally described in the literature as the double-base diode, but is now commercially
available under the designation Uni Junction transistor (UJT).

The standard symbol for this device is shown in the fig.

Here the emitter arrow is inclined and points toward B1 and This emitter arrow which is at an angle to the
vertical line representing N-type material. This arrow indicates the direction of flow of conventional
current when UJT is forward biased.
120
EQUIVALENT CIRCUIT OF UJT

The circuit of UJT is shown in the fig.

In the construction, the terminal emitter is closer to B2 as compared to B1.

If we see the equivalent circuit of UJT, The internal resistances of the two bases are represented as R b1and
Rb2. Hence Rb1 is greater than Rb2. The pn junction is represented by a normal diode with V das the drop
across it. When the emitter diode is not conducting then the resistance between the two bases B 1 and B2
is called interbase resistance denotes Rbb

Rbb=Rb1+Rb2

Its value ranges from 4kΩ to 12kΩ

Intrinsic stand off ratio (η)

Consider UJT as shown in the fig. to which supply Vbbis connected. With Ie=0, That is emitter diode is not
conducting,

Rbb=Rb1+Rb2

Then the voltage drop across Rb1 can be obtained by using potential divider rule.

121
Replacing with its equivalent circuit

Rbb=Rb1+Rb2

When Ie =0

VRB1= ) VBB =η.VBB When Ie=0

η = Intrinsic stand off ratio = ) when Ie=0

η= ) when Ie=0

The value of η is from 0.5 to 0.8 the voltage Vrb1 is called intrinsic stand-off voltage, because it keeps the
emitter diode reverse biased for all emitter voltages less than Vrb1.

VI Characteristics

The graph of Ie against emitter voltage plotted for a particular value of V bbis called the characteristics of
UJT.

The characteristics can be divided in to three main regions.

[Link] off 2. Negative resistance region 3. Saturation region.

122
[Link] off: The Ve<Vp and the pn junction is reverse biased. A small amount of reverse saturation current
Ie0 flows through the device which is negligibly small of the order of micro amps. This condition remains
till the peak point.

2. Negative resistance region: When emitter voltage V e becomes equal to Vp then p n junction becomes
forward biased and Ie starts flowing. The voltage across the device decreases in this region though the
current through the device increases. Hence the region is called negative resistance region. This decreases
the resistance Rb1. This region is stable and used in many applications. This region continues till valley
point.

3. Saturation region: The region to the right of the valley point is called saturation region. In the valley
point, the resistance changes from negative to positive. The resistance remains positive in the saturation
region. As Vbb increases , the potential Vp corresponding to peak point will increase.

Applications of UJT

The UJT is mainly used in the triggering of other devices such as SCR. It is also used in the sawtooth
wave generators and some timing circuits. The most popular application of UJT is as a relaxation
oscillator to obtain short pulses for triggering of SCRs.

The relaxation oscillator using UJT which is ment for generating sawtooth waveform. It consists of a UJT
and a capacitor, which is charged through emitter resistor as the supply voltage Vbb is switched 0N.

TUNNEL DIODE

PRINCIPLE OF OPERATION AND CHARACTERISTICS OF TUNNEL DIODE:

A tunnel diode or Esaki diode is a type of semiconductor diode which is capable of very fast operation,
well into the microwave frequency region, by using quantum mechanical [Link] was invented in
August 1957 by Leo Esaki when he was with Tokyo Tsushin Kogyo, now known as Sony. In 1973 he
received the Nobel Prize in Physics, jointly with Brian Josephson, for discovering the electron tunneling
effect used in these diodes. Robert Noyce independently came up with the idea of a tunnel diode while
working for William Shockley, but was discouraged from pursuing it.

Fig: Tunnel diode schematic symbol

123
These diodes have a heavily doped p–n junction only some 10 nm (100 Å) wide. The heavy doping
results in a broken band gap, where conduction band electron states on the n-side are more or less aligned
with valence band hole states on the p-side.

Tunnel diodes were manufactured by Sony for the first time in 1957 followed by General Electric and
other companies from about 1960, and are still made in low volume today. Tunnel diodes are usually
made from germanium, but can also be made in gallium arsenide and silicon materials. They can be used
as oscillators, amplifiers, frequency converters and detectors.

Tunnelling Phenomenon:
In electronics, Tunneling is known as a direct flow of electrons across the small depletion region from n-
side conduction band into the p-side valence band. In a p-n junction diode, both positive and negative ions
form the depletion region. Due to these ions, in-built electric potential or electric field is present in the
depletion region. This electric field gives an electric force to the opposite direction of externally applied
voltage.

As the width of the depletion layer reduces, charge carriers can easily cross the junction. Charge carriers
do not need any form of kinetic energy to move across the junction. Instead, carriers punch through
junction. This effect is called Tunneling and hence the diode is called Tunnel Diode.

124
Due to Tunneling, when the value of forward voltage is low value of forward current generated will be
high. It can operate in forward biased as well as in reverse biased. Due to high doping, it can operate in
reverse biased. Due to the reduction in barrier potential, the value of reverse breakdown voltage also
reduces. It reaches a value of zero. Due to this small reverse voltage leads to diode breakdown. Hence,
this creates negative resistance region.
Tunnel Diode Working Phenomenon

Unbiased Tunnel Diode

In an unbiased tunnel diode, no voltage will be applied to the tunnel diode. Here, due to heavy doping
conduction band of n – type semiconductor overlaps with valence band of p – type material. Electrons
from n side and holes from p side overlap with each other and they will be at same energy level. Some
electrons tunnel from the conduction band of n-region to the valence band of p-region when temperature
increases. Similarly, holes will move from valence band of p-region to the conduction band of n-region.
Finally, the net current will be zero since equal numbers of electrons are holes flow in opposite direction.

125
Small Voltage Applied to the Tunnel Diode

When a small voltage, that has lesser value than the built-in voltage of the depletion layer, is applied to
the tunnel diode, there is no flow of forward current through the junction. Nevertheless, a minimal
number of electrons from the conduction band of n region will start tunneling to valence band in p region.
Therefore, this movement creates a small forward biased tunnel current. When a small voltage is applied,
tunnel current starts to flow.

Increased Voltage Applied to the Tunnel Diode

When the amount of voltage applied is increased, the number of free electrons generated at n side and
holes at p side is also increased. Due to voltage increase, overlapping between the bands are also
increased.
Maximum tunnel current flows when the energy level of n-side conduction band and the energy level of a
p-side valence band becomes equal.

Further Increased Voltage Applied to the Tunnel Diode

A further increase in the applied voltage will cause a slight misalignment of the conduction band and
valence band. Still there will be an overlap between conduction band and valence band. The electrons
move from conduction band to valence band of p region. Therefore, this causes small current to flow.
Hence, tunnel current starts decreasing.
126
Largely Increased Voltage Applied to the Tunnel Diode

The tunneling current will be zero when applied voltage is increased more to the maximum. At this
voltage levels, the valence band and the conduction band does not overlap. This makes tunnel diode to
operate same as a PN junction diode.

When applied voltage is more than the built-in potential of the depletion layer the forward current starts
flowing through the tunnel diode. In this condition, current portion in the curve decreases when the
voltage increases and this is the negative resistance of tunnel diode. Such diodes operating in negative
resistance region is used as amplifier or oscillator.
V-I Characteristics of Tunnel Diode
Due to forward biasing, because of heavy doping conduction happens in the diode. The maximum current
that a diode reaches is Ip and voltage applied is Vp. The current value decreases, when more amount of
voltage is applied. Current keeps decreasing until it reaches a minimal value.

127
Advantages of tunnel diodes:

 Environmental immunity i.e peak point is not a function of temperature.

 low cost.
 low noise.
 low power consumption.
 High speed i.e tunneling takes place very fast at the speed of light in the order of nanoseconds
 simplicity i.e a tunnel diode can be used along with a d.c supply and a few passive elements to
obtain various application circuits.

Applications for tunnel diodes:

 local oscillators for UHF television tuners

 Trigger circuits in oscilloscopes
 High speed counter circuits and very fast-rise time pulse generator circuits
 The tunnel diode can also be used as low-noise microwave amplifier.

VARACTOR DIODE:

Varactor diode is a special type of diode which uses transition capacitance property i.e voltage variable
capacitance .These are also called as varicap, VVC (voltage variable capacitance) or tuning diodes. The
varactor diode symbol is shown below with a diagram representation.

128
 Fig: Equivalent circuit and symbol of varactor diode

When a reverse voltage is applied to a PN junction, the holes in the p-region are attracted to the anode
terminal and electrons in the n-region are attracted to the cathode terminal creating a region where there is
little current. This region ,the depletion region, is essentially devoid of carriers and behaves as the
dielectric of a capacitor.

The depletion region increases as reverse voltage across it increases; and since capacitance varies
inversely as dielectric thickness, the junction capacitance will decrease as the voltage across the PN
junction increases. So by varying the reverse voltage across a PN junction the junction capacitance can be
varied .This is shown in the typical varactor voltage-capacitance curve below.

Fig: voltage- capacitance curve

Notice the nonlinear increase in capacitance as the reverse voltage is decreased. This nonlinearity allows
the varactor to be used also as a harmonic generator.

Major varactor considerations are:

(a) Capacitance value
(b) Voltage
(c) Variation in capacitance with voltage.
(d) Maximum working voltage
(e) Leakage current

129
Applications:

a. Tuned circuits.
b. FM modulators
c. Automatic frequency control devices
d. Adjustable bandpass filters
e. Parametric amplifiers
f. Television receivers.

PHOTO DIODE:

The photo diode is a semiconductor p-n junction device whose region of operation is limited to the
reverse biased region. The figure below shows the symbol of photodiode

Fig: Symbol for photodiode.

Principle of operation:

A photodiode is a type of photo detector capable of converting light into either current or voltage,
depending upon the mode of operation. The common, traditional solar cell used to generate electric solar
power is a large area photodiode. A photodiode is designed to operate in reverse bias. The deletion region
width is large. Under normal conditions it carries small reverse current due to minority charge carriers.
When light is incident through glass window on the p-n junction, photons in the light bombard the p-n
junction and some energy s imparted to the valence electrons. So valence electrons break covalent bonds
and become free electrons. Thus more electron-hole pairs are generated. Thus total number of minority
charge carriers increases and hence reverse current increases. This is the basic principle of operation of
photo diode.
5.

130
Characteristics of photodiode:

When the P-N junction is reverse-biased, a reverse saturation current flows due to thermally generated
holes and electrons being swept across the junction as the minority carriers. With the increase in
temperature of the junction more and more hole-electron pairs are created and so the reverse saturation
current I0 increases. The same effect can be had by illuminating the junction. When light energy bombards
a P-N junction, it dislodges valence electrons. The more light striking the junction the larger the reverse
current in a diode. It is due to generation of more and more charge carriers with the increase in level of
illumination. This is clearly shown in ‘ figure for different intensity levels. The dark currentis the current
that exists when no light is incident. It is to be noted here that current becomes zero only with a positive
applied bias equals to VQ. The almost equal spacing between the curves for the same increment in
luminous flux reveals that the reverse saturation current I0 increases linearly with the luminous flux as
shown in figure. Increase in reverse voltage does not increase the reverse current significantly, because all
available charge carriers are already being swept across the junction. For reducing the reverse saturation
current I0 to zero, it is necessary to forward bias the junction by an amount equal to barrier potential. Thus
the photodiode can be used as a photoconductive device.

Fig: Characteristics of photodiode

On removal of reverse bias applied across the photodiode, minority charge carriers continue to be swept
across the junction while the diode is illuminated. This has the effect of increasing the concentration of
holes in the P-side and that of electrons in the N-side But the barrier potential is negative on the P-side
and positive on the N-side, and was created by holes flowing from P to N-side and electrons from N to P-
side during fabrication of junction. Thus the flow of minority carriers tends to reduce the barrier potential.

131
When an external circuit is connected across the diode terminals, the minority carrier; return to the
original side via the external circuit. The electrons which crossed the junction from P to N-side now flow
out through the N-terminal and into the P-terminal This means that the device is behaving as a voltage
cell with the N-side being the negative terminal and the P-side the positive terminal. Thus, the photodiode
is & photovoltaic device as well as photoconductive device.

Fig: Illumination vs current

Advantages:
The advantages of photodiode are:
1. It can be used as variable resistance device.
2. Highly sensitive to the light.
3. The speed of operation is very high.

Disadvantages:
1. Temperature dependent dark current.
2. Poor temperature stability.
3. Current needs amplification for driving other circuits.

Applications:

1. Alarm system.
2. Counting system.

132