Sequential Circuits

One bit Memory Cell

• Two cross coupled inverters i.e., the output of the first inverter is connected as an input to the second
inverter and the output of second inverter is connected as an input to the first inverter.
• The basic bistable element circuit has two stable states logic 0 and logic 1
• When A = 0, the output of inverter 1 is 1 (Ā), i.e., Q = 1. Since the output of inverter 1 is the input to the
inverter 2, Ā = B = 1. Consequently, the output of inverter 2, i.e., B̅ is 0. Since the output of the inverter
2 is connected to the input of the inverter 1, Q̅ = B̅ = A = 0. We have assumed same value for A. Thus,
the circuit is stable with Q̅ = A = B̅ = 0 and Q = Ā = B = 1.
• Similarly for A = 1 , the basic bistable element is stable with Q̅ = A = B̅ = 1 and Q = Ā = B = 0. This is a
second stable condition of the basic bistable element.
One bit Memory Cell
• The two stable states of basic bistable elements are used to store two binary elements, 0 and 1.
• In positive logic system, state Q = 1 is used to store logic 1, and state Q = 0 is used to store logic 0. It is
important to note that the two outputs are complementary. That is when Q = 0, Q̅ = 1; and when Q = 1, Q̅ = 0.
• From the above discussion we can note following things about the basic bistable element.
• The outputs Q and Q̅ are always complementary.
• The circuit has two stable states.
• Q = 1 , set state and Q = 0 , Reset state.
• If the circuit is in the set (1) state, it will remain in the set state and if the circuit is in the reset (0) state, it
will remain in the reset state.
• This property of the circuit shows that it can store 1-bit of digital information. Therefore, the circuit is called a 1-bit memory cell.
• The 1-bit information stored in the circuit is locked or latched in the circuit. Therefore, this circuit is also
referred to as a latch.
Latch
• Case 1 : S = R = 0
• In this case, S̅ = R̅ = 1.
• If Q = 1, Q and B inputs for NAND gate 2 are both 1 and hence output Q̅ = 0.
Since Q̅ = 0 and S̅ = 1, the output of NAND gate 1 is 1, i.e., Q = 1.
• If Q = 0, Q and R̅ inputs for NAND gate 2 are 0 and 1, and hence output Q̅ = 1.
Since Q̅ = 1 and S̅ = 1, the output of NAND gate 1 is 0, i.e., Q = 0.
• Thus, the circuit is stable in both states.
• This shows that when S = R = 0, the outputs do not change.
Latch
• Case 2 : S = 1 and R = 0
• In this case, S̅ = 0 and R̅ = 1.
• Since S̅ = 0, the output of NAND gate 1, Q = 1
• For NAND gate 2, both inputs Q and R̅ are 1, thus output Q̅ = 0.
• The inputs S = 1 and R = 0, makes Q = 1, i.e., set state.

• Case 3 : S = 0 and R = 1
• In this case, S̅ = 1 and R̅ = 0.
• Since R̅ = 0, the output of NAND gate 2, Q̅ = 1.
• For NAND gate 1, both inputs Q̅ and S̅ are 1, thus output Q = 0.
• The inputs S = 0 and R = 1, makes Q = 0, i.e., reset state.

• Case 4 : S = 1 and R = 1
• When S = R = 1, both the outputs Q and Q̅ try to become 1 which is not allowed.
Therefore, this input condition is prohibited.
Latches Vs Flip Flops
Level Triggering
Edge Triggering
SR Flip Flop
SR Flip Flop
• Characteristics Equation :
D Flip Flop
JK Flip Flop
JK Flip Flop
JK Flip Flop
JK Flip Flop
T Flip Flop
Race Around Condition
• In JK flip-flop, when J = K = 1, the output toggles (output changes either from 0 to 1 or from 1 to 0).
• Consider that initially Q = 0 and J = K = 1.
• After a time interval Δt equal to the propagation delay through two NAND gates in series, the output will
change to Q = 1 and after another time interval of Δt the output will change back to Q = 0.
• This toggling will continue until the flip-flop is enabled and J = K = 1.
• At the end of the clock pulse the flip-flop is disabled and the value of Q is uncertain.
 Master Slave JK Flip Flop
• A master-slave flip-flop is constructed from two flip-flops. One
circuit serves as a master and the other as a slave, and the
overall circuit is referred to as a master-slave flip-flop
• Positive clock pulses are applied to the first flip-flop and inverted
(negative) clock pulses are applied to the second flip-flop.
• When CK = 1, the first flip-flop (Master) is enabled and the
outputs QM​ and 𝑄𝑀 respond to the inputs J and K. At this time,
the second flip-flop (Slave) is inhibited because its clock is low
𝐶𝐾 = 0
• When CK = 0 (𝐶𝐾 = 1), the first flip-flop is inhibited and the
second flip-flop is enabled. At this time, the output of the
second flip-flop (Q and 𝑄ത ) follows the outputs QM​ and 𝑄𝑀 ,
respectively.
• Since the second flip-flop follows the first one, it is referred to as
the slave and the first one as the master.
• In the master-slave JK flip-flop, state change occurs when the
flip-flop goes through both the positive transition (first half) of
the clock and the negative transition (second half). Thus, the
race-around condition does not exist in the master-slave JK flip-
flop.
 Preset and Clear
• For the flip-flops, SR, D, JK, and T, the inputs are called synchronous inputs
because data on these inputs are transferred to the flip-flop’s output only
on the triggering edge of the clock pulse; that is, the data are transferred
synchronously with the clock.
• When power is turned ON, the state of the flip-flop is uncertain. It may
come to set (Q = 1) or reset (Q = 0) state.
• In many applications, it is necessary to initially set or reset the flip-flop.
Such an initial state of the flip-flop can be accomplished by using the direct
or asynchronous inputs of the flip-flop. These inputs are: 𝑃𝑟𝑒𝑠𝑒𝑡 (𝑃)and ത
𝐶𝑙𝑒𝑎𝑟 (𝐶)ҧ
• They can be applied at any time between clock pulses and are not in
synchronism with the clock.
• The Fig. shows the SR and D flip-flops with preset and clear inputs.
• These are active-low inputs and thus when , 𝑃ത = 𝐶ҧ = 1 the circuit operates
in accordance with the truth table of SR flip-flop. If 𝑃ത = 1 and 𝐶ҧ = 0, the flip-
flop is reset and if 𝑃ത = 0 and 𝐶ҧ = 1, the flip-flop is set.
•REFER NOTEBOOK for TOPICS
•Excitation Table for each Flip flop
•Convert one type of Flip flop into other
type Flip flop
Registers
• A group of flip-flops connected together forms
a register.
• A register is used solely for storing and
shifting data which is in the form of 1s and/or
0s, entered from an external source.
• n – bit register has a group of n flip flops and
is capable of storing any binary info or no.
containing n-bits
• Fig. shows a 3-bit register using three D flip-
flops.
• Preset, reset, and clock inputs are connected
in parallel, and the 3-bit input is applied to the
D inputs of the flip-flops.
• During the positive edge of the clock, the D
inputs of the flip-flops are stored within the
flip-flops and are available at the outputs of
the D flip-flops.
Shift Registers
• The binary information (data) in a register can be moved from stage to stage within the register
or into or out of the register upon application of clock pulses.
• This type of bit movement or shifting is essential for certain arithmetic and logic operations
used in microprocessors.
• This gives rise to a group of registers called shift registers.
• They are very important in applications involving the storage and transfer of data in a digital
system.
• Modes of operations of shift registers
• Serial-in Serial-out (SISO)
• Serial-in, Parallel-out (SIPO)
• Parallel-in, Serial-out (PISO)
• Parallel-in, Parallel-out (PIPO)
Shift Registers
• Types of Shift Registers:
• Serial In Serial Out (SISO) Shift Register
• Serial In Parallel Out (SIPO) Shift Register
• Parallel In Serial Out (PISO) Shift Register
• Parallel In Parallel Out (PIPO) Shift Register
Serial In Serial Out (SISO) Shift Registers
• Shift left mode

Initially
Serial In Serial Out (SISO) Shift Registers
• Shift left mode
Serial In Serial Out (SISO) Shift Registers
• Shift left mode
Serial In Serial Out (SISO) Shift Registers
• Shift left mode
Serial In Serial Out (SISO) Shift Registers
• Shift Right mode

Initially
SISO Shift Registers
• Shift right mode
Serial In Serial Out (SISO) Shift Registers
• Shift right mode
Serial In Serial Out (SISO) Shift Registers
• Shift right mode
Serial In Parallel Out (SIPO) Shift Registers
Parallel In Serial Out (PIPO) Shift Registers
Parallel In Parallel Out (PIPO) Shift Registers
Bidirectional Shift Registers
Counters
• Counters are a specific type of sequential
circuit.
• Like registers, the state, or the flip-flop values
themselves, serves as the “output.”
• The output value increases / decreases by
one on each clock cycle.
• After the largest / smallest value, the output
“wraps around” back to original state. 1
00 01

1 1

1
11 10
Counters
• A counter is a register capable of counting the number of clock pulses arriving at its clock input.
• Count represents the number of clock pulses arrived. On arrival of each clock pulse, the counter is
incremented by one.
• In case of down counter, it is decremented by one.
• Fig. shows 3-bit counter. It consists of three flip-flops.
• A counter with n flip-flops has 2ⁿ possible states. Therefore, the 3-bit counter can count from
decimal 0 to 7.
Counters
• Fig. shows the logic symbol of a binary counter.
• External clock is applied to the clock input of the counter.
• The counter can be positive edge triggered or negative edge triggered.
• The n-bit binary counter has n flip-flops and it has 2ⁿ distinct states of outputs.
• For example, 2-bit counter has 2 flip-flops and it has 4 (2²) distinct states : 00, 01, 10 and 11.
• Similarly, the 3-bit binary counter has 3 flip-flops and it has 8 (2³) distinct states : 000, 001, 010,
011, 100, 101, 110 and 111.
• The maximum count that the binary counter can count is 2ⁿ − 1.
• For example, in 2-bit binary counter, the maximum count is 2² − 1 = 3 (11 in binary).
• After reaching the maximum count the counter resets to 0 on arrival of the next clock pulse and
it starts counting again.
• Counters are basically of two types :
• Asynchronous or ripple counters :
• For these counters the external clock signal is applied to one flip-flop and
then the output of preceding flip-flop is connected to the clock of next flip-
flop.
• Synchronous counters :
• In synchronous counters all the flip-flops receive the external clock pulse; it is
applied to all the flip-flops simultaneously.
• Ring counter and Johnson counter are the examples of synchronous counters.

Synchronous
Counters
Asynchronous
Modulus N Counter (MOD - N Counter)
• Modulus of the Counter (MOD-N Counter)
• Modulus (MOD) of a counter represents the number of states through which the
counter progresses during its operation.
• It is denoted by N.
• MOD-N counter means the counter progresses through N states.
• MOD-4 counter means it will have 4 states.
• MOD-6 counter means it will have 6 states
• MOD Number=2n
Asynchronous Counters
• 2-bit ripple up counter
• The number of flip-flops used is 2. Note that the number of bits will always be equal to the number of
flip-flops. Thus a 4-bit counter will use four flip-flops.
• The toggle (T) flip-flops are being used. But we can use the JK flip-flops also with J and K connected
permanently to logic 1.
• External clock is applied to the clock input of flip-flop A which is the LSB flip-flop and QA output is
applied to the clock input of the next flip-flop i.e. FF-B.
Asynchronous Counters
• 2-bit ripple up counter
• Operations
• Initially let both the flip-flops be in reset condition.
QBQA=00
QBQA=01 ….. After the first CLK pulse
QBQA= 10 ……..After the second CLK pulse
QBQA= 11 ….. After the third CLK pulse
QBQA=00 ….. After the fourth CLK pulse

Timing diagram for a 2-bit ripple up counter

3-bit ripple counter

• Number of states: Number of states = 2n=23=8.

• Maximum Count: QCQBQA = 111
3-bit ripple counter
4-Bit Asynchronous Counter
4-Bit Asynchronous Counter
Asynchronous Down Counter
• Counters which can count in the downward direction i.e. from the maximum count to zero are
called down counters.
• 3-Bit Asynchronous Down Counter
Asynchronous Down Counter
• 3-Bit Asynchronous Down Counter
• Thus counting takes place as follows :QCQBQA=111,110,101,100,011,010,001,000
• From this sequence it is evident that FF-A should toggle at every negative going QA changes
from LOW (0) to HIGH (1) and QC should change only when QB changes from LOW to HIGH.
• The clock input is applied directly to the clock input of FF-A. But Q𝐴 is connected to clock of
FF-B, Q𝐵 to clock of FF-C and so on.
Asynchronous Down Counter
• 3-Bit Asynchronous Down Counter
• H. W.
• 2 – bit asynchronous Down Counter
• 4 – bit asynchronous Down Counter
 Synchronous Counter
• Synchronous Counters are so called because the clock input of all the
individual flip-flops within the counter are all clocked together at the same
time by the same clock signal.
• The clock signal is directly applied to all Flip flops in a parallel sequence.
2-bit Synchronous Up Counter
3-bit Synchronous Up Counter
3-bit Synchronous Up Counter
4-bit Synchronous Up Counter

• Write truth table

4-bit Synchronous Up Counter
3-bit Synchronous Down Counter
3-bit Synchronous Down Counter
3-bit Asynchronous UP/Down Counter
3-bit Asynchronous UP/Down Counter
3-bit Asynchronous UP/Down Counter
3-bit Synchronous UP/Down Counter
•This counter performs both UP counting & DOWN counting using only one counter.
•When M = 1 → the counter performs UP counting.
•When M = 0 → performs DOWN counting.
•For UP & DOWN counters we have used the following input connections for 3-bit counter.
UP Counter (M=1) DOWN Counter (M=0)
TA = 1 (High) TA= 1 (High)
TB = QA TB= 𝑄𝐴
TC = QA·QB TC = 𝑄𝐴·𝑄𝐵
Ring Counter
• An application of shift registers.
• Output of FF-3 is connected to data input D₀ of FF-0.
• Ring counter is a special type of shift register.
• Operations
• Initially a low clear (CLR) pulse is applied to all the flip-flops.
• Hence FF-3, FF-2 and FF-1 will reset but FF-0 will be preset.
• So the outputs of the shift register are:
Q3Q2Q1Q0=0001
• Now the clear terminal is made inactive by applying a high level to it.
• The clock signal is then applied to all the flip-flops simultaneously.
Ring Counter
• Operations
• On the first negative going CLK edge
• As soon as the first falling edge of the clock hits, only FF-1 will be set because Q₀ = D₁ = 1.
• FF-0 will reset because D₀ = Q₃ =0, and there is no change in the status of FF-2 and FF-3.
• Hence after the first clock pulse the outputs are:
Q3Q2Q1Q0=0010
• On the second falling edge of clock
• At the second falling edge of the clock, only FF-2 will be set because D₂ = Q₁ = 1.
• FF-1 will reset since D₁ = Q₀ = 0. There is no change in status of FF-3 and FF-0.
• So after the second clock pulse the outputs are:
Q₃ Q₂ Q₁ Q₀ = 0100
• Similarly after the third clock pulse the outputs are:
Q₃ Q₂ Q₁ Q₀ = 1000
• And after the fourth clock pulse the outputs are:
Q₃ Q₂ Q₁ Q₀ = 0001
• These are the outputs from where we started. Hence the operation repeats from this
point onwards.
Ring Counter
•
 Ring Counter using JK Flip Flop
•
• H. W.
• Johnson Counter or Twisted Ring Counter
BCD Counter
• BCD means 0 – 9 states
BCD Counter
BCD Counter