Computer Systems and Architecture
Sushma B.
Assistant Professor (Selection Grade)
Dept. of Electronics & Communication Engineering
ASB, Bangalore
Sushma B R
Course details
Course name : Computer Systems and Architecture
Course code : 23ECE301
Course Instructor details:
Sushma B
Email: [Link]@[Link]
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Input and Output Organization
Accessing I/O devices
Interrupts (Interrupt hardware, Enabling and disabling
interrupts, Handling multiple devices, controlling device
requests, Exceptions, Use of interrupts in OS)
Direct memory access
Buses
Interface circuits
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Accessing I/O devices
A single bus architecture
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Single bus: A simple arrangement to connect I/O devices to a
computer
Bus enables devices to communicate: It consists three
sets-Address, data and control lines
Processor requests for read or write, data is transmitted
through data lines
When I/O devices and memory share the same address space,
the arrangement is called memory mapped I/O
A machine instruction which can access memory can also be
used to transfer data to and from I/O devices : Examples:
Move DATAIN, RO, Move RO, DATAOUT
DATAIN is the input buffer, DATAOUT is the output buffer
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Some processors consists special I/O instructions. Otherwise
most of the processor s are memory mapped I/O devices
Designer as an option to use separate address space for I/O
devices. Most of the processors use memory address space.
Having separate I/O address space enables I/O devices to have
only few address lines. Address lines used for memory access
are only used for I/O but lower order lines. A special signal on
the bus indicates whether it is memory operation or I/O.
When I/O, devices examine only lower order bits in the
address
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Hardware required to connect an I/O device
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Address decoder enables the device to recognize its address
when this address appears on the address lines
Data register holds the data being transferred to or from the
processor
Status register contains information relevant tot he operation
of the I/O device
Address decoder, data and status registers and the control
circuitry need to coordinate I/O transfers forming the device’s
interface circuit
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Implementing I/O operations
Three commonly used I/O operation mechanisms are:
Program-controlled I/O, Interrupts and Direct memory access.
Program controlled I/O-Processor repeatedly checks a status
flag to achieve the required synchronization between the
processor and an input/output device. This is called polling
the device.
Interrupts: Synchronization is achieved by having the I/O
device send a special signal over the bus whenever it is ready
for a data transfer operation.
Direct memory access: Technique used for high speed I/O
devices. It involves having the device interface transfer data
directly to or from the memory without continuous
involvement by the processor.
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Interrupts
One mechanism to serve the I/O device is to continuously
monitor the status of the I/O device. During this period
processor can perform many other tasks.
In another method, I/O device can alert the processor when it
is ready. It can do this by sending a hardware signal called
interrupt to the processor. One of the bus control line is
dedicated for this called as interrupt-request line.
Processor no need to check the status of the external devices
contnously, it can utilize the available time for executing other
tasks.
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Interrupt request arrives during execution of instruction i
Processor first completes execution of instruction i. It loads
the PC with the address of first instruction in ISR
After ISR, processor has to come back to instruction i+1.
A return from interrupt instruction at the end of ISR reloads
the PC from temporary storage location causing execution to
resume at instruction i+1. In many cases the return address is
saved on the processor stack.
In some cases, return address is saved in the special register
provided for this purpose.
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ISR (Interrupt service routine): The routine executed in
response to an interrupt request is called the ISR.
While handling the interrupts, processor must inform the
device that its request has been recognized and it should
remove its interrupt request signal. For this, a special control
signal on the bus called interrupt-acknowledge signal is used.
ISR execution is similar to regular subroutine. A subroutine
performs a function required by the program from which it is
called.
Before calling ISR, any information altered during execution
must be saved. This information must be restored before
execution of the interrupted program.
Information that needs to be saved and restored includes the
condition code flags and contents of any registers used by
both the interrupted program and ISR.
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Interrupt hardware
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I/O device requests an interrupt by activating a bus line called
interrupt-request. Most computers consists several I/O
devices that can request an interrupt.
A single interrupt request line can be used to serve n devices.
All the devices are connected to a line and switch to ground.
Switch is closed for the request.
When all the switches are open, voltage on the line-Vdd. If
any of the switch is closed, the voltage 0 appears on the line
causing the interrupt request.
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Enabling and Disabling Interrupts
Processor status register (PS) on the stack. One bit in the PS
register called interrupt-enable bit indicates whether the
interrupts are enabled.
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Handling multiple devices
Device-X may request an interrupt, while device Y is being
serviced.
Device X and Y may request for the service, several devices
may request interrupts exactly at the same time
When request is received from the device, additional
information is used to identify the particular device
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Vectored Interrupts
A vectored interrupt is a type of interrupt mechanism in which
the processor automatically jumps to a specific memory
address (interrupt vector) associated with the interrupt source.
Each interrupting device has a unique interrupt vector, which
directly points to its Interrupt Service Routine (ISR).
This eliminates the need for additional polling or interrupt
identification steps, allowing for faster and more efficient
interrupt handling.
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When an interrupt occurs,
The interrupting device provides its vector number or address
to the CPU.
The CPU uses this vector to locate the corresponding ISR in
memory.
Control is transferred directly to that ISR for execution.
The interrupting device must wait to put data on the bus only
when the processor is ready to receive
When the processor is ready to receive the interrupt vector
code, it activates the interrupt acknowledge line, INTA.
The I/O device responds by sending its interrupt vector code
and turning off the INTR signal.
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Interrupt Nesting
Interrupt nesting is the mechanism that allows an Interrupt
Service Routine (ISR) to be interrupted by another (usually
higher-priority) interrupt.
Instead of finishing the current ISR before servicing another
interrupt, the processor can nest ISRs so higher-priority events
get serviced immediately.
Delay in responding to the request must be small
I/o devices must be organized in a priority structure. Interrupt
request from high-priority device should be accepted while the
processor is serving low priority device.
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Multiple-level priority
During execution of the main program, requests are accepted
only from few devices, depending upon device’s priority.
Priority can be assigned to the processor program. Processor
accepts requests only from devices with higher priority than
the processor. Processor’s priority can be changed by program
control
When it is executing the ISR of one device, it’s priority is
raised the the device level
Processor’s priority is encoded in a few bits of the processor’s
status word. This can be changed by privileged instructions.
Processor is in supervisor model while executing OS routines
Switiches to user mode before begining to execute the
application programs which prevents application programs
changing the priority of the processor
If application program executes the privilege instruction while
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in user mode leads to raise in special interrupt called privilege
Multiple priority scheme can be implemented by using
separate interrupt request and interrupt acknowledge lines
Each of the interrupt request lines is assigned a different
priority level. Interrupt requests over these lines are sent to a
priority arbitration circuit in the processor.
A request is accepted only if it has higher priority level than
that currently assigned to the processor
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Simultaneous requests
How the simultaneous requests from two or more devices are
handled?
Processor accepts the request with highest priority
When several devices are sharing the common interrupt
request line-one method to serve the device is by polling.
Polling the status registers of the I/O devices is the simplest
mechanism in which priority is determined by the order in
which the devices are polled.
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Dasiy Chain: When INTR line is common to all the devices,
INTA is connected in daisy chain fashion. INTA signal
propagates serially through the devices. Device-1 has a
pending request for interrupt, it blocks the INTA signal. Else
it passes to device-2 and so on.
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Daisy Chain
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Arrangement of devices in priority groups
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Controlling device requests
Allow the devices to generate the interrupts by using
interrupt-enable bit in control register.
Enable-bit=1 allows the device to generate the interrupt
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Exceptions
Interrupts: I/O devices requests
Exception: Any event that causes an interruption
Few types of exceptions are: Recovery from errors,
Debugging, Privilege exception
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Recovery from errors
Computers use a variety of techniques to ensure that all
hardware components are operating properly.
Many computers include an error-checking code in the main
memory, which allows detection of errors in the stored data. If
an error occurs, the control hardware detects it and informs
the processor by raising an interrupt.
The processor may also interrupt a program if it detects an
error or an unusual condition while executing the instructions
of this program.
Example: The OP-code field of an instruction may not
correspond to any legal instruction, or an arithmetic
instruction may attempt a division by zero.
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When exception processing is initiated as a result of such
errors, the processor proceeds in exactly the same manner as
in the case of an I/O interrupt request.
It suspends the program being executed and starts an
exception-service routine, which takes appropriate action to
recover from the error.
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Privilege exception
To protect the OS of a computer from being corrupted by
user programs, certain instructions can be executed only when
the processor is in supervisor mode. These instructions are
called privileged instructions
When the processor is in running in user mode, it will not
execute an instructions that changes the priority level of the
processor or that enables a user program to access areas in
the computer memory that have been allocated to other users.
An attempt to execute such an instruction will produce a
privilege exception.
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Direct Memory Access
For the data transfer between processor and I/O device,
processor either polls a status flag in the device interface or
waits for the device to send an interrupt request. In both the
cases considerable overhead is required.
To transfer large blocks of data at high speed, an alternative
approach is used. A special control unit may be provided to
allow transfer of a block of data directly between an external
device and the main memory, without continuous intervention
by the processor. This approach is called direct memory
access (DMA).
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DMA Controller: DMA transfers are performed by a control
circuit that is part of the I/O device interface. The circuit is
called as DMA controller.
DMA controller performs operations which are done by the
processor during main memory access
For each word transfer, DMA has to increment the address to
keep track of the number of transfers
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Though processor does not interfere in DMA controller, its
operation is under the control of a program executed by the
processor.
To initiate the transfer of a block of words, the processor
sends the starting address, number of words in the block, and
direction of transfer.
On receiving this information DMA proceeds to perform the
requested information. When the entire block is transferred,
DMA interrupts the processor by raising the interrupt.
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Bus Arbitration
In a computer system, bus arbitration is the process that
determines which device gets control of the system bus when
multiple devices request access at the same time.
The bus is a shared communication pathway used by the
CPU, memory, and I/O devices, only one device can use it at
a time to avoid conflicts.
Multiple devices (CPU, DMA controller, I/O devices) may
need to use the bus simultaneously.
Device that is allowed to initiate data transfers on the bus at
any given time is called bus master.
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Some times it is transferred to another device. Bus arbitration
is the process by which the next device will become the
master.
The selection of the bus master must take into account the
needs of various devices by establishing a priority system for
gaining access to the bus.
Two main approaches: Centralized arbitration and distributed
arbitration
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Bus-arbitration process
Bus Request (BR): A device that needs the bus sends a
request signal to the bus arbiter (controller).
Bus Grant (BG) : The arbiter checks all requests, decides
which device has priority, and sends a grant signal.
Bus Busy (BB) : Once a device gains control, it asserts the
bus busy signal to prevent others from using it.
Bus Release : After completing its operation, the device
releases the bus so another device can use it.
Two types: Centralized and Distributed bus arbitration
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Centralized Bus arbitration
Only single bus arbiter performs the required arbitration and it
can be either a processor or a separate DMS controller.
Daisy Chaining - It is a simple and cheaper method where all
the masters use the same line for making bus requests.
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Distributed arbitration
Distributed bus arbitration is a method in which no single
device or controller has complete authority over the bus.
Instead, all devices connected to the bus participate equally in
the process of deciding who gets control of it.
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Buses
The processor, main memory and I/O devices can be
interconnected by means of a common bus whose primary
function is to provide a communication path for the transfer
of data.
Bus protocol: Set of rules govern the bahaviour of various
devices connected to the bus as to when to place the
information on the bus, asser control signals etc
Device which initiates the transfer is called master and the
other device is called slave
Synchronous bus and Asynchronous bus
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Synchronous bus
All devices share a common clock signal that defines precise
timing for all operations. Every data transfer such as sending
an address, reading, or writing data occurs at predetermined
intervals based on this clock.
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Asynchronous Bus
An asynchronous bus is a bus system in which no common
clock signal is shared among the connected devices.
Instead of being synchronized by a central clock, data
transfers are coordinated through handshaking signals
exchanged between the communicating devices (the sender
and receiver).
In an asynchronous bus, all devices operate independently, and
each data transfer is initiated and completed by a sequence of
handshaking signals between the devices involved, rather than
being controlled by a clock.
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The master device (e.g., CPU) sends a request signal to
indicate that it wants to start a data transfer.
The slave device (e.g., memory or I/O) responds with an
acknowledge signal once it is ready.
The transfer is completed when both devices agree that the
data has been successfully sent and received.
The timing of these signals depends on the response speed of
the devices, not a fixed clock cycle.
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Parallel processing
Large computing capacity using supercomputers
Supercomputers : A Supercomputer is a high-performance
computing system that uses thousands (or even millions) of
processing cores working in parallel to perform trillions of
calculations per second (measured in FLOPS -Floating Point
Operations Per Second).
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Forms of parallel processing
A task is divided into subtasks.. Subtasks are done in parallel
bi different hardware components. Example: Processor
computation and I/O transfer
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Classification of Parallel Structures
SISD (Single instruction, single data)
SIMD (single instruction multiple data) ; Single stream of
instructions are broadcasted to many processors, each will
operate on its own data.
MISD (multiple instructions, single data) : Common data is
manipulated by separate processors, each executing the
different program
MIMD (multiple instructions, multiple data): Different
programs accessing its own sequence of data.
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Structure of General-Purpose processors
Possible ways of implementing multiprocessor systems
Uniform memory access (UMA) processor: In this an
interconnection network permits n-processors to access k-memories
so that any of the processors can access any of the memories
Non-uniform memory access (NUMA) processor: Memory modules
are directly attached to the processors. Processors can also access
the other modules and these accesses can take more time. So,
called as non-uniform.
in UMA and NUMA, processors can access any memory without the
intervention of the other processors. Memory is treated as global
memory
Distributed memory system: Processor can access the memory
attached to other processors with the intervention of the processor
through message passing.
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Interconnection networks
Interconnection network allows information transfer between
any pair of modules in the system
Helps in broadcasting the info from one module to many
modules
Single Bus, Crossbar networks
Mesh Networks, Tree networks, Ring networks
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Single Bus
Processor is connected to the memory modules using a single
bus
Bus is dedicated to a particular source-destination pair. It will
be idle till it completes one complete request.
Split-transaction protocol makes it possible to use the idle
period to serve another request.
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Crossbar network
Any model Qi can connect to any other model Qj through switches
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Mesh network
A natural way of connecting a large number of nodes is with a
two-dimensional mesh,
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Tree network and Ring network
Parent node enables the communication between the child
nodes
Ring network: Point to point communication
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Cache coherence
(discussed in Memory organization)
Cache coherence
Write through protocol
Write back protocol
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Local area networks
Ethernet
Token Ring: In token ring protocol, a single encoded short
message called token circulates across the ring. Any node has
the message to transmit, it blocks the token and transmits the
packet. Packet is accepted when it reaches the correct
destination node
Network of workstations
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