Chapter 4: Mapping

Chapter 4
Mapping

1 Mapping of a 140 Mbit/s Signal into the STM-1

Fig. 1

1.1 "Mapping" of a 140 Mbit/s Signal to the Container C-4

Prior to its transmission in the STM-1 frame, the 140 Mbit/s PDH signal is
interleaved into a container C-4. The position of the signal bits in the container
is exactly defined. The term "mapping" describes this fixed bit arrangement.

The size of the container C-4 amounts to 2340 byte. For a better
understanding, a two-dimensional representation of the container is shown
below (9 x 260):

2
Chapter 4: Mapping

A C-4 is provided as network-synchronous transmission capacity every 125

µs.

A comparison of the number of possible, usable bits per container C-4

260 byte x 9 = 2340 byte x 8 = 18720 bit

Fig. 2

And the number of bits (nominal bit rate: 139,264 Mbit) actually to be
transmitted per container

139,264 Mbit/s: 8000 Hz = 17408 bit,

Reveals an over-capacity of the C-4.

3
Chapter 4: Mapping

Fig. 3

Beside the pure tributary information bits (140 Mbit/s) the following bits are
transmitted in the container C-4:

 Fixed justification bits and bytes (approximate clock alignment.

 Justification opportunity bits (positive justification for precise clock
alignment).
 Justification control bits (justification information bits).
 Overhead bits (no function specified) 140 Mbit/s in C-4.

The 140-Mbit/s

Plesiochronous signal is aligned to the C-4 container bit rate through bit-by-bit
positive justification. 1 justification opportunity bit and 5 justification control
bits are provided per container row. The exact mapping of these bits in the
container is shown in fig. 5.

4
Chapter 4: Mapping

Fig. 4 Plesiochronous 139,264-kbit/s signal in VC-4 VC-4 block structure

Fig. 5 Plesiochronous 139,264 k-bit/s signal in VC-4 1 VC-4 row

5
Chapter 4: Mapping

The C-4 container has a total transmission capacity of 260 x 9 x 8 bits/125 s.

A capacity of 2080 bits is available per container row.

The 140-Mbit/s signal has a nominal bit rate of 139.264 Mbit/s, corresponding
to 17408 bit/125 µs. This, results in 1934.222 bits per signal container row.
The C-4 container provides 1934 I-bits and 1 stuffable bit per row for
transmission of this useful information. Each row further contains 5 stuff
check bits as well as overhead and fixed stuff bits and bytes respectively.

1.2 Interleaving of the C-4 into the STM-1

In order to transmit the container C-4 in the STM-1, container-specific

supplementing must be effected:

1. Addition of the Path OverHead (POH)

The VC-4 includes a "Path OverHead" (POH) with a size of 9 byte.

Fig. 6

6
Chapter 4: Mapping

Additional Information about Path:

The route which a container and its overhead take through the SDH network is
also called "path".

The path is defined by the operator. At the beginning of the path, every
container is assigned a trace, which can be checked at the end of the path.

The block resulting from the container C-4 and the POH is called

Virtual Container 4 = VC-4.

Fig. 7

2. Addition of the Pointer (PTR)

There is a floating embedding of the Virtual Container VC-4 into the STM-1
frame of the payload. Part of the Virtual Container VC-4 is transmitted in one
STM-1 frame, and another part in the next frame.

7
Chapter 4: Mapping

Fig. 8

The Pointer (PTR) indicates the start of the Virtual Container (VC-4) in the
payload.

That component of the STM-1, inside which the

VC-4 is able to "float" and which is made up of
PTR and payload, is designated

Administrated Unit 4 = AU-4

The AU-4 Pointer is abbreviated AU-4 PTR.

3. Addition of the Section OverHead (SOH)

In order to complete the STM-1 frame, the Section OverHead (SOH) is

added to the AU-4.

8
Chapter 4: Mapping

2 Mapping of a 34 Mbit/s Signal to the Container C-3

2.1 3 x 34 Mbit/s -> STM-1

Fig. 9

Prior to its transmission in the STM-1 frame, the 34 Mbit/s PDH signal is
interleaved into a container C-3 (=Mapping).

The size of the container C-3 amounts to 756 byte. For a better understanding,
a two-dimensional representation of the container is shown below (9 x 84):

A C-3 is provided as network-synchronous transmission capacity every 125

μs.

A comparison of the number of possible, usable bits per container C-3

9 byte x 84 =756 byte x 8 = 6048 bit

And the number of bits (nominal bit rate: 34,368 Mbit/s) actually to be
transmitted per container
9
Chapter 4: Mapping

34,368 Mbit/s: 8000 Hz = 4296 bit

Reveals an over-capacity of the container C-3!

Fig. 10

The reason for the over-capacity is a recommendation by ITU-T specifying

that the transmission of a 44, 736 Mbit/s signal (ANSI) must also be carried
out in the container C-3.

= 44, 736 Mbit/s: 8000 Hz = 5593 bit.

Fig. 11

10
Chapter 4: Mapping

When considering the number of payload bits per STM-1 frame

9 byte x 261 x 8 = 18720 bit,

it emerges that only three C-3 (3 x 6048 bit) at maximum can be transmitted
per STM-1 frame => this means only 3 x 34 Mbit/s instead of the 4 x 34
Mbit/s which can be transmitted in a 140 Mbit/s PDH signal.

Beside the pure tributary information bits (34 Mbit/s)! the following bits are
transmitted in the container C-3:

 Fixed justification bits and bytes (approximate clock alignment).

 Justification opportunity bits (positive/negative justification for precise
clock alignment).
 Justification control bits (indicate whether there is a positive, negative, or
no justification).
 Overhead bits (no function specified).

34 Mbit/s in C-3

The positive/zero/negative justification method is used for transmission of the

34 Mbit/s plesiochronous signal in the C-3 container. For this purpose 2
justification opportunity bits within 3 container rows are provided (fig. 13).

11
Chapter 4: Mapping

Fig. 12 Plesiochronous 34,368 kbit/s signal in VC-3 Block structure

Fig. 13 Plesiochronous 34,368-kbit/s signal in VC-3 3 rows of the VC-3

Three C-3 container rows at a time provide 2016 bits for transmission. These
bits comprise 1431 I-bits, 2 justification opportunity bits, 2 x 5 justification
control bits as well as overhead and fixed stuff bits. The 34 Mbit/s signal has a
nominal bit rate of 34,368 Mbit/s.
12
Chapter 4: Mapping

1432 bits must thus be transmitted per 3 C-3 container rows. The 1431 I-bits
in the container are used up by the incoming signal at the nominal bit rate.
One justification opportunity bit must permanently be used as an I-bit. One
justification opportunity bit is transmitted as a justification bit (without
information).

However, if the bit rate of the incoming signal is below the nominal value, the
second s-bit (an I-bit in the nominal case) must also be stuffed if necessary
(positive justification).

If the bit rate of the incoming signal exceeds the nominal value, the first S-bit
(a justification bit in the nominal case) is used as an I-bit if required (negative
justification).

2.2 Interleaving of Three C-3 into the VC-4

The transmission of three C-3 in the STM-1 requires some container-specific

supplementing to be effected for every C-3.

Fig. 14

13
Chapter 4: Mapping

2.3 Creation of the Tributary Unit 3 (TU3)

Every C-3 receives a "Path OverHead" (POH) with a size of 9 byte. The block
resulting from the C-3 and POH is termed Virtual Container-3 = VC-3.

Every Virtual Container VC-3 (=LOWER ORDER VC) is assigned a 3-byte

Pointer PTR, which allows the VC-3 to float. The area in which the VC-3 can
float with the aid of the Pointer PTR is called Tributary Unit 3 = TU-3. The
3-byte pointer in the TU-3 is called TU-3 Pointer. The PTR contains an
address which indicates the start of the VC-3 in the TU-3.

Fig. 15

2.4 Creation of the Tributary Unit Group 3 (TUG-3)

A Tributary Unit TU-3 is always supplemented with six fixed justification

bytes which do not contain any information. The block resulting from the
TU-3 and the fixed justification bytes is called Tributary Unit Group 3 =
TUG-3.

14
Chapter 4: Mapping

Fig. 16

2.5 Interleaving of TUG-3 into VC-4

The three resulting TUG-3 (#1, #2 and #3) are byte-interleaved into a Virtual
Container VC-4 (=HIGHER ORDER VC ).

To adjust the three byte-interleaved TUG-3 to the VC-4 it is necessary to add

two columns of fixed justification bytes.

Fig. 17
15
Chapter 4: Mapping

2.6 Interleaving of the VC-4 into the STM-1

The Virtual Container VC-4 is transmitted directly in the STM-1 frame

(Payload).

In this case, the pointer (PTR) embedded in the STM-1 frame contains an
address indicating the beginning of the VC-4 in the payload.

That component of the STM-1, inside which the VC-4 can "float" and which
comprises the two blocks PTR and Payload is designated.

Administrative Unit 4 = AU-4.

In the AU-4, the pointer is abbreviated AU-4 PTR.

Fig. 18

To supplement the STM-1 frame, the Section OverHead (SOH) is added to the
AU-4.
16
Chapter 4: Mapping

Fig. 19

3 Mapping of a 2 Mbit/s Signal to STM-1

Fig. 20

17
Chapter 4: Mapping

3.1 "Mapping" of a 2 Mbit/s Signal to the Container C-12

Prior to its transmission in the STM-1 frame, the 2 Mbit/s PDH signal is
interleaved into a container C-12 (=Mapping).

The size of the container C-12 amounts to 34 byte. For a better understanding,
you can find a two-dimensional representation of the container below:

Fig. 21

A comparison of the number of possible, usable bits per container C-12

= 34 byte x 8 = 272 bit

And the number of bits (nominal bit rate: 2,048 Mbit/s) actually to be
transported per container

2,048 Mbit/s: 8000 Hz = 256 bit,

Reveals an over-capacity of the container C-12.

Beside the pure tributary information bits (2 Mbit/s),

18
Chapter 4: Mapping

The following bits are transmitted in the container C-12:

 Fixed justification bits and bytes (approximate clock alignment).

 Justification opportunity bits (positive/negative justification for precise
clock alignment).
 Justification control bits (indicates whether there is a positive, negative or
no justification).
 Overhead bits (no function specified).

Fig. 22

3.2 Creating a VC-12 Frame

In order to transmit 63 containers C-12 (with an own 2 Mbit/s signal in each

case) in the STM-1 frame, container-specific supplementing is necessary for
every C-12.

A "Path OverHead" (POH) with the size of 1 byte is added to every C-12.
The function of these bytes will be explained in chapter 6.
19
Chapter 4: Mapping

A VC-12 is provided as network-synchronous transmission capacity every 125 µs.

Fig. 23

3.3 Creating the Tributary Unit TU-12

Fig. 24

20
Chapter 4: Mapping

3.4 Creation of the Tributary Unit Group TUG-2

Three TU-12 (= 3 x 2 Mbit/s signals) from different multiframe TU-12 are

multiplexed byte-by-byte to form a "Tributary Unit Group-2" (TUG-2).

For a better understanding, again a two-dimensional representation of a TU-12

partial fame will be shown.

Fig. 25

21
Chapter 4: Mapping

3.5 Creation of a Tributary Unit Group TUG-3

In a next step, seven TUG-2 (=21 x 2 Mbit/s signals) are combined to form a
TUG-3, i.e. byte-interleaved.

Fig. 26

22
Chapter 4: Mapping

3.6 Interleaving of TUG-3 into a Virtual Container VC-4

The three resulting TUG-3 (#1 #2 and #3) are byte-interleaved into a Virtual
Container VC-4 (=HIGHER ORDER VC).

Fig. 27

3.7 Interleaving of the VC-4 into the STM-1

The Virtual Container VC-4 is transmitted directly in the STM-1 frame

(Payload).

In this case, the pointer (PTR) embedded in the STM-1 frame contains an
address indicating the beginning of the VC-4 in the payload.

23
Chapter 4: Mapping

Fig. 28

That component of the STM-1, inside which the VC-4 can "float" and which
comprises the two blocks PTR and Payload is designated.

Administrative Unit 4 = AU-4.

In the AU-4, the pointer is abbreviated AU-4 PTR.

To supplement the STM-1 frame, the Section OverHead (SOH) is added to the
AU-4.

Fig. 29
24
Chapter 4: Mapping

3.8 Creation of a VC-12 Multiframe

In order to transmit 63 containers C-12 (with an own 2 Mbit/s signal in each

case) in the STM-1 frame, container-specific supplementing is necessary for
every C-12.

A "Path OverHead" (POH) with the size of 1 byte is added to every C-12.

The function of these bytes will be explained in chapter 6.

There can be four different POH bytes for one C-12:

Caution: A multiframe VC-12 is transmitted via four or five STM-1 frames!

Fig. 30

25
Chapter 4: Mapping

Fig. 31 Plesiochronous 2Mbit/s mapping

When a byte-synchronous 2Mbit/s signal is transmitted, the individual 64-

kbit/s channels occupy exactly one byte for each channel in the STM 1 frame.
Hence after the interpretation of the individual pointer levels, it is possible to
access a 64-kbit/s directly, irrespective of the transmission mode. However,
two pointers must be evaluated the AU and the TU pointers.

26
Chapter 4: Mapping

Fig. 32

3.9 Numbering of TU-12s in a VC 4

Each TUG-2 can comprise three TU-12s which shall be numbered #1 to #3(#K).

Thus any TU-12 can be allocated a two-figure address in the form #L, #M,
where L designates the TUG-2 number (1 to 7) and M designates the TU-12
number (1 to 3).

Thus TU-12 #1 (1, 1) resides in columns 10, 73, 136 and 199 of the VC-4, and
TU-12 #2(7, 3) resides in columns 71, 134, 197 and 260 of the VC-4. A full
listing of the location of the TU-12 columns with the VC-4 frame follows.

NOTE – The Time Slot number contained in the diagrams below should
not be interpreted as the tributary port number, as the time slots and port
numbers are independent from each other. It is only during configuration
of the equipment that port is assigned a time slot.
27
Chapter 4: Mapping

An external tributary signal may be assigned to a particular payload capacity

using a connection function.

For example at the VC-12 level,

– Tributary #1 – TU-12 (1, 1, 1)

– Tributary #2 – TU-12 (1, 1, 2)
– Tributary #3 – TU-12 (1, 1, 3)
– Tributary #4 – TU-12 (1, 2, 1)


– Tributary #63 – TU-12 (3, 7, 3)

Fig. 33

28
Chapter 4: Mapping

Fig. 34

3.10 Creating Tributary Units

That component, inside which the multiframe VC-12 can "float" with the aid
of a pointer, is termed multiframe TU-12. The four pointer bytes also count
as part of the multiframe TU-12. Every 125 µs one pointer byte is transmitted,
i.e. the transmission of the complete pointer takes 500 µs.

Three TU-12 (= 3 x 2 Mbit/s signals) from different multiframe TU-12 are

multiplexed byte-by-byte to form a "Tributary Unit Group-2" (TUG-2).

29
Chapter 4: Mapping

In a next step, seven TUG-2 (=21 x 2 Mbit/s signals) are combined to form a
TUG-3, i.e. byte-interleaved.

The three resulting TUG-3 (#1 #2 and #3) are byte-interleaved into a Virtual
Container VC-4 (=HIGHER ORDER VC ) and so on (see 3.6).

Fig. 35

4 Concatenation of Payloads

4.1 Introduction

There is an increasing need to have ultra high capacity interfaces which

require several 155Mbit/s channels in today's Data applications.

Therefore if we can transmit data in one channel rather than several individual
channels, then we would have better utilization of the available channel
bandwidth. This would also prove to be a much less expensive solution for our
customers.

30
Chapter 4: Mapping

These large channels are called "Clear Channels". Concatenation is the merger
of multiple channels (say 155Mbit/s) into one large Clear Channel.

There are TWO distinct methods of CONCATENATION

1. CONTIGUOUS CONCATENATION.
2. VIRTUAL CONCATENATION.
An example of where this feature is used is when there is a requirement to
carry IP packets over the SDH network.

This is a detailed subject which is not covered in this course.

For further reading, an introduction, in the form of a tutorial, can be found in

the Appendix of this training manual. Please take some time later to read this
as it gives good background information on this topic.

4.2 Contiguous Concatenation of Payloads

To illustrate the form of concatenation we will use the concatenation of VC4's

initially, then describe the TU 2's AU4's can be concatenated to form and AU4
Xc which can transport payloads requiring greater than one Container 4
capacity.

The concatenation indication is used so that the multi container VC4 Xc

payload should be kept together, and is part of the VC 4 pointer. The X
indicates the number of VC 4 concatenated, e.g. VC 4 4c means 4 VC 4
concatenated i.e. capacity of 599.040 Mbit/s.

The first AU 4 of an AU4 Xc has the normal range of pointer values. All
subsequent AU 4 within the AU4 Xc will have their pointer set to

31
Chapter 4: Mapping

Concatenation Indication (CI) "1001" in bits 1 to 4, with bits 5 & 6

unspecified, and the 10 bit decimal pointer values will have all 1's.

The CI indicates that the pointer processors will perform the same operations
as performed on the first AU4 of the AU4 Xc.

Recommendation G707 also describes the contiguous concatenation of TU 2

in VC3. The term VC 2mc is used where "m" indicates the number of
concatenated Tu 2's carried.

The first TU 2 of an TU 2mc has the normal range of pointer values. All
subsequent Tu 2's within the TU 2 mc will have their pointer set to
Concatenation Indication (CI) "1001" in bits 1 to 4, with bits 5 & 6
unspecified, and the 10 bit decimal pointer values will have all 1's.

The CI indicates that the pointer processors will perform the same operations
as performed on the first TU2 of the TU 2mc.

4.3 Virtual Concatenation of Payloads

The standard G707 describes the use of Virtual Concatenation of TU 2

payloads only. The Virtual Concatenation of VC 4 payloads is understudy,
however, it is expected that the process will remain the same.

This method of concatenation has been initially developed for the transport of
a single VC 2 mc, m times TU 2 without the use of CI of the pointer bytes.
This method only requires the path termination equipment to provide
concatenation functions.

32
Chapter 4: Mapping

Virtual Concatenation requires that all TU signals to be concatenated at the

origin of the path are to have the same pointer value. These TU's are then
carried in one VC4. When the VC4 is then terminated, all the concatenated
TU's must be passed unaltered from one interface to another and remain
within the VC4 with their time sequence unchanged.

With Virtual Concatenation the available capacity is lower than that for a
Contiguous Concatenation, therefore, care should be taken to base the required
capacity of VC 2mc's to the lower value to allowed the interconnections of
both types of concatenation. The reasons for this is because Virtual
concatenations need a separate POH for every VC 2 whereas contiguous
concatenation only requires a POH for the first VC signal. Byte stuffing
techniques are used to fill up the spare capacity in the Contiguously
concatenated TU 2mc.

Fig. 36 Two methods of concatenation

33
Chapter 4: Mapping

Fig. 37

Fig. 38
34
Chapter 4: Mapping

The diagram above shows the following:

1. The normal multiplex structure that has been already introduced.

2. The STM 0 multiplex structure are used Radio Relay products, such as:

 SRT1S.
 SRA1S.

3. The concatenated multiplex structure, also it can be seen that an STM

4/16/64/256 can carry both concatenated and non-concatenated signals.

35