CISC vs RISC Architectures
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CISC – Complex Instruction Set Computer
• CISC is a computer architecture in which the processor supports a large
number of complex instructions.
• Each instruction can perform multiple low-level operations, such as
loading data from memory, performing an arithmetic operation, and storing
the result back to memory — all in a single instruction.
CISC instruction
ADD A, B
This might read A and B directly from memory, add them, and store
the result back — all in one instruction.
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Main Objectives of CISC:
• Reduce the number of instructions in a program
• Make programming easier (especially in assembly)
• Reduce memory usage by writing fewer lines of code
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Characteristics of CISC
1. Large Instruction Set
•CISC processors may have hundreds of instructions
•Some instructions are very complex and take many steps to execute
2. Variable-Length Instructions
•Instructions can be 1 byte, 2 bytes, or more
•This makes instruction decoding slow and complex
3. Memory-to-Memory Operations
•Many CISC instructions can access memory directly
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4. Multiple Clock Cycles
•A single instruction may take multiple clock cycles to complete
5. Microprogrammed Control Unit
•CISC processors usually use a microprogrammed control unit
•This increases hardware complexity but supports complex instructions
6. Many Addressing Modes
•Supports many ways to access memory (direct, indirect, indexed, etc.)
7. Difficult to Pipeline
•Because instructions vary in length and execution time, pipelining is inefficient
Examples of CISC:
•Intel x86 family (8086, 80286, Pentium, etc.)
•VAX
•Motorola 68000
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RISC (Reduced Instruction Set Computer)
• RISC is a CPU design approach that uses simple instructions,
fixed length format, and many registers to improve speed
and efficiency.
• RISC is a computer architecture designed to use a small set of
simple and fast instructions. Each instruction is designed to
execute in one clock cycle (ideally) and only load and store
instructions access memory.
• one machine instruction per machine cycle. A machine
cycle is defined to be the time it takes to fetch two operands
from registers, perform an ALU operation, and store the result in
a register.
• Example: ARM, MIPS, SPARC, RISC-V
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Main Objective of RISC:
• Increase execution speed
• Improve performance via pipelining
• Simplify hardware design
• Instead of performing many things in one instruction (like CISC),
RISC uses many simple instructions to perform a task.
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Basic Principles of RISC
1. Load/Store Architecture
• Only two types of instructions can access memory:
• LOAD – Transfers data from memory to register
• STORE – Transfers data from register to memory
• All other operations are done between registers
LOAD R1, A
LOAD R2, B
ADD R3, R1, R2
STORE R3, C
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2. Fixed-Length Instructions
• All instructions are same length (usually 32 bits)
• This allows:
• Faster fetching
• Easier decoding
• Efficient pipelining
3. Large Number of Registers
• RISC processors have more general-purpose registers
• This:
• Reduces memory access
• Increases speed.
4. Simple Addressing Modes
• Very few addressing modes (usually 3–5)
• Makes circuit design simple
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5. Hardwired Control Unit
• Uses a hardwired control unit instead of microprogramming
• This is faster and more efficient
6. Easy Pipelining
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Advantages of RISC
•Faster execution
•Simple hardware
•Low power consumption
•Easy pipelining
•Better performance per watt
Disadvantages of RISC
•More lines of code
•Requires better compiler optimization
•Higher memory usage
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• Advantages of CISC
• Less code required
• Easier for assembly language programming
• More powerful single instructions
• Disadvantages of CISC
• Complex hardware
• Slower execution
• High power consumption
• Difficult pipelining
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RISC vs RISC Architectures
CISC (Complex Instruction RISC (Reduced Instruction
Feature
Set Computer) Set Computer)
Supports a large number of Supports small number of
Meaning
complex instructions simple instructions
Instruction length Variable length instructions Fixed length instructions
One instruction may take Usually one clock cycle per
Execution time
multiple clock cycles instruction
Uses Load/Store architecture
Instructions can directly
Memory access (only LOAD/STORE access
access memory
memory)
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Control unit Usually microprogrammed Usually hardwired
Addressing modes Many addressing modes Few addressing modes
Smaller code (due to Larger code (more
Code size
complex instructions) instructions needed)
Difficult (varied instruction
Pipelining Easy & efficient
length)
Power consumption Higher Lower
Performance Slower due to complexity Faster due to simplicity
Intel x86, VAX, Motorola ARM, MIPS, SPARC, RISC-
Examples
68000 V
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RISC designs may benefit from the inclusion of some CISC
features.
CISC designs may benefit from the inclusion of some RISC
features.
The result is that the more recent RISC designs, notably the
PowerPC, are no longer “pure” RISC and the more recent CISC
designs, notably the Pentium II and later Pentium models, do
incorporate some RISC characteristics.
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