MODULE 2

REGISTER TRANSFER LOGIC:

Digital system is a collection of digital hardware modules. A digital system is a sequential logic
system constructed with flip flops and gates. The sequential circuit can be specified by means
of a state table. Specifying a large digital system with a state table would be very difficult, since
the number of states would be very large.

To overcome this difficulty, digital systems are designed using a modular approach, where
each modular subsystem performs some functional task. The modules are constructed from
such digital functions as registers, counters, decoders, multiplexers, arithmetic elements and
control logic. Various modules are interconnected with data and control path.

The information flow and the processing task among the data stored in the registers can be
described by means of register transfer logic.

Components of Register Transfer Logic

1. The set of registers in the system and their functions :A register also encompasses all
type of registers including shift registers, counters and memory units.

2. The binary-coded information stored in the registers: The binary information stored in
registers may be binary numbers, binary coded decimal numbers, alphanumeric characters,
control information or any other binary coded information.
3. The operations performed on the information stored in the registers: The operations
performed on data stored in registers are called micro operations. Examples are shift, count,
add, clear and load 4. The control functions that initiate the sequence of operations: The control
functions that initiate the sequence of operations consists of timing signals that sequence the
operations one at a time

Micro-Operation: Operations performed in data stored in registers. Elementary operation that

can be performed parallel during one clock pulse period. The result of operation may replace
the previous binary information of a register or may be transfered to another register. Example:
Shift, count, clear, add & load A micro-operation requires one clock pulse for the execution if
the operation done in parallel.

Types of Micro-Operations in digital system

 Interregister transfer micro-operation: Do not change the information content when the binary
information moves from one register to another

 Arithmetic operation: Perform arithmetic on numbers stored in registers.

 Logic microoperation: Perform operations such as AND and OR on individual pairs of bits
stored in registers.

 Shift microoperation: Specify operations for shift registers.

INTER REGISTER TRANSFER
Computer registers are designated by capital letters (sometimes followed by numerals) to
denote the function of the register. [Example: R1 - Processor Register, MAR - Memory
Address Register (holds an address for a memory unit), PC - Program Counter, IR - Instruction
Register, SR: Status Register].The cells or flipflops of n-bit register are numbered in sequence
from1 to n (from 0 to n-1) starting either from left or from right
The register can be represented in 4 ways:

 Rectangular box with name of the register inside,

 The individual cells is assigned a letter with a subscript number

 The numbering of cells from right to left can be marked on top of the box as the 12 bit register
Memory Buffer Register (MBR).

 16 bit register is partitioned into 2 parts , bits 1 to 8 are assigned the letter L(for low) and bits
9 to 16 are assigned the letter H(for high)

Registers can be specified in a register transfer language with a declaration statement.

For example: Registers in the above figure can be defined with declaration statement such as
DECLARE REGISTER A(8), MBR(12), PC(16)
DECLARE SUBREGISTER PC(L) = PC(1-8), PC(H) = PC(9-16).
Conditional transfer occurs only under a control condition:

The condition that determines when the transfer is to occurs called a control function. A control
function is a Boolean function that can be equal to 1 or 0. The control function is included with
the statement as follows
x’T1: A ← B
The control function is terminated with a colon. It symbolizes the requirement that the transfer
operation be executed by the hardware only when the Boolean function x’T1 = 1. ie; when
variable x = 0 and timing variable T1 = 1.
Hardware implementation of a controlled transfer: x’T1: A ← B is as follows
The outputs of register B are connected to the input of register A and the number of lines in
this connection is equal to the number of bits in the registers. Register A must have a load
control input so that it can be enabled when the control function is 1. It is assumed that register
A has an additional input that accepts continuous synchronized clock pulses. The control
function is generated by means of an inverter and an AND gate. It is also assumed that the
control unit that generates the timing variable T1 i synchronized with the same clock pulses
that are applied to register A. The control function stays on during one clock pulse period (when
the timing variable is equal to 1) and the transfer occurs during the next transaction of a clock
pulse
Destination register receives information from two sources but not at the same time.
Consider,
T1 : C ← A
T5 : C ← B

The first line states that the contents of register A are to be transferred to register C when
timimg variable T1 occurs. The second statement uses the same destination register C as the
first but with a different source register and a different timing variable. The connections of two
source registers to the same destinationr register cannot be done direcly but requires a
multiplexer circuit to select between the two possibe paths. The block diagram of the circuit
that implements the two statement is shown in the figure. For registers with four bits each, we
need a quadruple 2 to 1 line multiplexer inorder to select either A or B. When T5 =1, register
B is selected but when T1=1, register A is selected (because T5 must be 0 when T1 is 1). The
multiplexer and the load input of register C are enabled everytime T1 and T5 occurs. This
causes a transfer of information from the selected source register to destination register.
ARITHMETIC, LOGIC AND SHIFT MICRO OPERATION
Arithmetic Micro-Operation
The basic arithmetic micro-operations are:

 Addition,

 Subtraction,

 Increment,

 Decrement

 Arithmetic shift

The increment and decrement micro-operations are implemented with a combinational circuit
or with a binary up-down counter as these micro-operations use plus-one and minus-one
operation respectively.
The arithmetic add microoperations are defined by the statement
F ← A + B.

It states that the contents of register A are to be added to the contents of register B and the sum
is transferred to register F To implement this statement require 3 registers A, B and F and a
digital function that performs the addition operation such as parallel adder.
There must be a direct relationship between the statements written in a register transfer
language and the registers and digital functions which are required for the implementation
Consider the statements
T2 : A ← A + B
T5 : A ← A + 1

Timing variable T2 initiates an operation to add the contents of register B to the present
contents of A with a parallel adder. Timing variable T5 increments register A with a counter.
The transfer of the sum from parallel adder into register A can be activated with a load input
in the register. Register be a counter with parallel load capability. The parallel adder receives
input information from registers A and B. The sum bits from the parallel adder are applied to
the inputs of A and timing variable T2 loads the sum into register A. Timing variable T5
increments there by enabling increment input register

Logic Micro-Operations
Logic micro-operations specify binary operations for strings of bits stored in registers. These
operations consider each bit of the register separately and treat them as binary variables. For
example, the exclusive-OR micro-operation with the contents of two registers A and B is
symbolized by the statement

F←A⊕B
 It specifies a logic micro-operation that consider each pair of bits in the registers as a binary
variable. Let the content of register A is 1010 and the content of register B is 1100. The
exclusive-OR micro-operation stated above symbolizes the following logic computation:

The content of F, after the execution of the micro-operation, is equal to the bit-by-bit exclusive-
OR operation on pairs of bits in B and values of A

The + symbol has different meaning. When + occurs in a microoperation , it denotes arithmetic
plus.. When it occurs in a control or Boolean function, it denotes a logical OR operation.

Example: T1 + T2 : A ← A + B, C ← D ∨ F

The + between T1 and T2 is an OR operation between 2 timing variables of a control function

and the + between A & B specifies an add microoperation

Shift Micro-Operations
Shift micro-operations shift the contents of a register either left or right. These microoperations
are generally used for serial transfer of data. They are also used along with arithmetic, logic,
and other data-processing operations
Registers can be shifted to the left or right. There are no conventional symbols for shift. Here
we are adopting the symbols shl and shr for shift left and shift right operations respectively
Here when we are shifting to left the bit at position A0 is vacant. This gap can be filled by
transferring the bit of position An in the original register A. This can be considered as a circular
shift.

Example 2: Shr A

When we are shifting the register content to the right, the bit at position An is vacant. This gap
can be tilled by receiving the value of the 1 bit register E.

PROCESSOR ORGANIZATION
The processor part of a computer CPU is sometimes referred to as the data path of the CPU
because the processor forms the paths for the data transfers between the registers in the unit.
The various paths are said to be controlled by means of gates that open the required path and
close all others. A processor unit can be designed to fulfill the requirements of a set of data
paths for a specific application. In a processor unit, the data paths are formed by means of buses
and other common lines. The control gates that formulate the given path are essentially
multiplexers and decoders whose selection lines specify the required path.

Bus Organization
A bus organization for four processor registers is shown in Figure. Each register is connected
to two multiplexers (MUX) to form input buses A and B. The selection lines of each
multiplexer select one register for the particular bus. The A and B buses are applied to a
common arithmetic logic [Link] function selected in the ALU determines the particular
operation that is to be performed. The shift micro-operations are implemented in the shifter
.The result of the micro-operation goes through the output bus S into the inputs of all registers.
The destination register that receives the information from the output bus is selected by a
decoder.

When enabled, this decoder activates one of the register load inputs to provide a transfer path
between the data on the S bus and the inputs of the selected destination register. The output bus
S provides the terminals for transferring data to an external destination. One input of
multiplexer A or B can receive data from the outside The control unit that supervises the
processor bus system directs the information flow through the ALU by selecting the various
components in the unit.

For example, to perform the microoperation:

R1←R2+ R3
The control must provide binary selection variables to the following selector inputs:
1. MUX A selector: to place the contents of R2 onto bus A.
2. MUX B selector: to place the contents of R3 onto bus B.
3. ALU function selector: to provide the arithmetic operation A + B.
4. Shift selector: for direct transfer from the output of the ALU onto output bus S (no shift).
5. Decoder destination selector: to transfer the contents of bus S into R 1.

Scratchpad memory
The register in a processor unit can be enclosed in a small memory unit. When included in a
processor unit,a small memory is sometime called a scratchpad [Link] use of a small
memory is a cheaper alternative to collecting processor registers through a bus [Link]
difference between the two system is the manner in which information is selected for transfer
into the ALU. In a bus system, the information transfer is selected by the multiplexer that form
the buses.

Processor unit that uses scratchpad memory is shown in figure. Resource register is selected
from memory and loaded into register A. A Second source register is selected from memory
and loaded into register B. The information in A and B is manipulated in the ALU and shifter.
Result of the operation is transferred to a memory register specifying its word address and
activating the memory-write input control.

Assume that the memory has eight words, so that an address must be specified with three bits.
To perform the operation
R1 ← R2 + R3

The control must provide binary selection variable to perform the following sequence of micro-
operations

Control function T1 must supply an address of 010 to the memory and activate the read and
load A inputs. control function T2 must supply an address 011 to the memory and activate the
read and load B inputs. Control function T3 must supply the function code to the ALU and
shifter to perform an add operation, apply an address 001 to the memory, select the output of
the shifter for the MUX and activate the memory write input.

Some processor employ a 2 port memory in order to overcome the delay caused when reading
two source registers. A 2-port has two separate address lines to select two words of memory
simultaneously. The organization of a processor unit with a 2-port scratchpad memory is shown
in figure

A 2-port memory has two separate address lines to select two words of memory simultaneously.
o Two source registers can be read at the same time.

 If the destination register is same as one of the source registers, then the entire
microoperation can be done within one clock pulse period.
 The memory has two sets of addresses, one for port A and the other for port B.
 Data from any word in memory are read into the register by specifying an address.
 When enabled by the Memory Enable(ME) input, new data can be written into the word
specified by the B address.
 Thus the A and B addresses specify two source registers simultaneously, and the B address
always specifies the destination register.
 The A and B registers, act as latches, accept new information as long as the clock pulse,
CP is in the 1-state.
 When CP goes to 0, the latches are disabled, and they hold the previous information.
 This eliminates any possible race conditions that could occur while new information is
being written into memory.
 The clock input controls the memory read and write operations through the Write Enable
(WE) input. It also controls the transfers into the A and B latches.
 Thus, a microoperation can be done within one clock pulse period.

Accumulator Register
An accumulator is a register for short-term, intermediate storage of arithmetic and logic data
in a computer's CPU (central processing unit).The most elementary use for an accumulator is
adding a sequence of numbers. The numerical value in the accumulator increases as each
number is added, exactly as it happens in a simple desktop calculator (but much faster, of
course). Once the sum has been determined, it is written to the main memory or to another
register. The accumulator register in a processor unit is a multipurpose register capable of
performing not only the add micro-operation, but many other operations as well. The block
diagram shows the processor unit that employs an accumulator units. To form the sum of two
numbers stored in processor registers, it is necessary to add them in the A register using the
following sequence of microoperations:

The sum / result formed in A may be used for other computation or may be transfered to a
required destination.
ARITHMETIC LOGIC UNIT
An arithmetic logic unit (ALU) is a multi operation, combinational-logic digital function. It
can perform a set of basic arithmetic operations and a set of logic operations. The ALU has a
number of selection lines to select a particular operation in the unit. The figure shows the block
diagram of 4 bit ALU.

The design of a typical ALU will be carried out in three stages. First, the design of the
arithmetic section will be undertaken. Second, the design of the logic section will be
considered. Finally, the arithmetic section will be modified so that it can perform both
arithmetic and logic operations.

Design of Arithmetic Circuit

The basic component of the arithmetic section of an ALU is a parallel adder. A parallel adder
is constructed with a number of full-adder circuits connected in cascade. By controlling the
data inputs to the parallel adder, it is possible to obtain different types of arithmetic operations.
The figure demonstrates the arithmetic operations obtained when one set of inputs to a parallel
adder is controlled externally. The number of bits in the parallel adder may be of any value.
The input carry Cin goes to the full-adder circuit in the least significant bit position. The output
carry Cout comes from the full-adder circuit in the most significant bit position

The circuit that controls input B to provide the functions is called a true/complement, one/zero
element. This circuit is illustrated in the following figure. The 2 selection lines s1 and s0 control
the input of each B terminal.

The input A is applied directly to the 4-bit parallel adder and the input B is modified. The
resultant arithmetic circuit is shown in below figure. A 4-bit arithmetic circuit that performs 8
arithmetic operations is shown in following Figure.
Design of Logic Circuit
The logic microoperations manipulate the bits of the operands separately and treat each bit as
a binary variable. The 16 logic operations can be generated in one circuit and selected by means
of four selection lines. Since all logic operations can be obtained by means of AND, OR, and
NOT (complement) operations, it may be more convenient to employ a logic circuit with just
these operations. For three operations, we need two selection variables. But two selection lines
can select among four logic operations, so we choose also the exclusive-OR (XOR) function
for the logic circuit to be designed in this and the next section.

The four gate generate four logic operations OR, XOR, AND, and NOT. The two selection
variables in the multiplexer select one of the gates for the output. The function table lists the
output logic generated as a function of the two selection variables. The logic circuit can be
combined with the arithmetic circuit to produce one arithmetic logic unit. Selection variables
S1 and S0 can be made common to both sections provided we use a third selection variable,
S2, to differentiate between the two. This configuration is illustrated in the below figure.
The outputs of the logic and arithmetic circuits in each stage go through a multiplexer with
selection variable S2. When
S2 = 0, the arithmetic output is selected,
when S2 = 1, the logic output is selected

Design of Combinational Logic Shifter

The shift unit attached to the processor transfers the output of the ALU onto the output bus.
Shifter may function in four different ways.
1. The shifter may transfer the information directly without a shift.
2. The shifter may shift the information to the right.
3. The shifter may shift the information to the left.
4. In some cases no transfer is made from ALU to the output bus.

A shifter is a bi-directional shift-register with parallel load. The information from ALU can be
transferred to the register in parallel and then shifted to the right or left. In this configuration,
a clock pulse is needed for the transfer to the shift register, and another pulse is needed for the
shift. Another clock pulse may also in need of when information is passed from shift register
to destination register.

The number of clock pulses may reduce if the shifter is implemented with a combinational
circuit. A combinational—logic shifter can be constructed with multiplexers. The above figure
will show the same.
Shifter operation can be selected by two variables H1 H0
 If H1 H0 = 0 0 No shift is executed and the signal from F go directly to S lines

 If H1 H0 = 0 1 Shift Right is executed

 If H1 H0 = 1 0 Shift Left is executed

 If H1 H0 = 1 1 No operations

PROCESSOR UNIT
A block diagram of a processor unit is shown in figure. It consists of seven registers R1 through
R7 and a status register. The outputs of the seven registers go through two multiplexers to select
the inputs to the ALU.

Input data from an external source are also selected by the same multiplexers. The output of
the ALU goes through a shifter and then to a set of external output terminals. The output from
the shifter can be transferred to any one of the registers or to an external destination. There are
16 selection variables in the unit, and their function is specified by a Control Word. The 16-bit
control word, when applied to the selection variables in the processor, specifies a given
microoperation. The Control Word is partitioned into 6 fields, with each field designated by a
letter name. All fields, except Cin, have a code of three bits. The functions of all selection
variables are specified in table below.
The 3 bits of A select a Source Register for the input to left side of the ALU.

The B field is the same, but it selects the source information for the right input of the ALU.

The D field selects a Destination Register.

The F field, together with the bit in Cin, selects a Function for the ALU.

 The H field selects the type of Shift in the shifter unit.

STATUS REGISTERS
Status register is a 4 bit register. The four bits are C (carry), Z (zero),S (sign) and V
(overflow).These bits are set or cleared as a result of an operation performed in the ALU

 Bit C is set if the output carry of an ALU is 1

.  Bit S is set to 1 if the highest order bit of the result in the output of the ALU is 1.
 Bit Z is set to 1 if the output of the ALU contains all O's.

 Bit V is set if the exclusive —OR of carries C8 and C9 is 1, and cleared otherwise. This is
the condition for overflow when the numbers are in signed 2's complement representation. For
an 8 bit ALU, V is set if the result is greater than 127 or less than -128.

Relative magnitudes of A and B can be checked by compare operation. If A-B is performed for
twounsigned binary numbers, relative magnitudes of A and B can be determined from the
values transferred tothe C and Z bits. If Z=1,we knows that A=B, since A-B=0. If Z=0, then
we know that A is not equal to B. Similarly C=1 if A>=B and C=0 if A
Q) Design of Accumulator?
• Accumulator register is a multipurpose register capable of performing
many micro-operations. The organization of a processor unit with an
accumulator register is shown below.

• The ALU associated with the register maybe constructed as a

combinational circuit. In this configuration, the accumulator register with
parallel load is connected to the ALU.
• The block diagram of the accumulator that forms as sequential circuit is
shown below:
 • Accumulator can also perform data processing operations. Total of nine
operations are considered here for the design of accumulator circuit.
• These operations are described below.

Design Procedure

1. Add B to A (P1)
• Add micro-operation is initiated when control variable P, is 1. To
perform addition operation, accumulator can use a parallel adder
composed of full adders. The full adder in each stage 1 will accept
the input and and a previous carry bit C1.
• Sum bit is transferred to flip flop Ai, and output carries Ci+1 is
transferred to the next stage as input carry of that stage.
• The state table of a full adder, when considered as a sequential
circuit is shown below.
• The excitation input for the JK flip flop is shown below for reference.

• According to these values the above flip flop inputs are set. The flip flop
input functions and the Boolean functions for the output are simplified in
the maps as shown in fig.
 These two equations should affect the flip flop only when PI is enabled.
Therefore, they should be ANDed with control variable P, Then the equation
becomes.

JAi =B1C1’P1+B1’C1P1

KAi = B1C1’P1+B1’C1P1

Ci+1=A1B1+A1C1+B1C1
2. Clear (P2)

• Control variable P2 clears all flip flops in register A. To cause this transition
in a JK flip flop. we need only apply control satiable P2 to the K input of
the flip flop.
• The J input will he assumed to be 0 if nothing is applied on it. The input
functions can be written as.

JAi =0

KAi =P2
3. COMPLEMENT(P3)

• To cause this transition in a JK flip-flop we need to apply p3 to both

J and K inputs.
JAi =P3 KAi =P3
2. AND (P4)
• This micro operation is initiated with control variable [Link]
operation performs the logic AND operation between Ai and Bi and
transfers the result to A.
• The excitation table for this operation is as shown below.
Present State Input Next State Flip-flop Inputs
Ai Bi Ai JAi KAi
0 0 0 0 X
0 1 0 0 X
1 0 0 X 1
1 1 1 X 0

• The next state of Ai will be 1 only when the present state of Ai and data
input Bi, is 1. The flip flop input functions can be simplified with the maps
and the equations can be written as:

JAi =0
KAi =Bi’
• By including the control variable p4, the equation can be rewritten as:

JAi =0

KAi =Bi’P4
4. OR (P5)
• Control variable P5, initiates the logic OR operation between Ai and Bi The
result is transferred to Ai.
• The excitation table for this operation is as shown below.
Present State Input Next State Flip-flop Inputs
Ai Bi Ai JAi KAi
0 0 0 0 X
0 1 1 1 X
1 0 1 X 0
1 1 1 X 0

• The simplified equations in the maps dictate that the J input be enabled
when Bi =1. When Bi=0, the present state and next state of Ai are the same.
• When Bi=1, the J input is enabled and the next state of Ai, becomes 1.
Input functions for the OR micro operation are:

JAi =BiP5

KAi =0

6. Exclusive-OR (P6)

• Control variable P6 initiates the logic Exclusive-OR operation between Ai

and Bi. The result is transferred to Ai.
• The excitation table and map simplification is as shown below.
 • The flip flop input functions are written as:

JAi =BiP6
KAi = BiP6
7. Shift-right (P7)

• Control variable P7 initiates the shift operation of Ai register one bit to the
right. That is the value of flip flop Ai+1 is transferred to flip flop Ai.
• The flip flop input functions can be written as:

JAi = Ai+1 P7
KAi = Ai+1 P7

8. Shift-left (P8)

• Control variable P8 initiates the shift operation of Ai register one bit to the
left. That is, the value of flip flop Ai-1 is transferred to flip flop Ai .
• The flip flop input functions can be written as:
• JAi = Ai-1 P8
• KAi = Ai-1 P8

9. Increment (P9)
 • These operations increment the content of A register by one. The register
behaves likes a synchronous binary counter with P9 enabling the count.
• A 3 bit synchronous counter is shown in the following figure.

• The Boolean function for a typical stage can be written as:

10. Check for Zero (Z)

• Variable Z is an output from the accumulator. This variable can be used to

indicate a zero content in the A register.
• All the flip flops in the accumulator is cleared Z variable will be set to 1.
When a flip flop is cleared, its complement output Q' is equal to 1.
• The following figure shows the first three stages of the accumulator that
checks for zero content.
 • Each stage generates a variable Zi+1 by ANDing the complement output of
Ai to an input variable Zi. In this way, a chain of AND gates through all
stages will indicate if all flips ate cleared.
• The Boolean function for a typical stage can be expressed as:
Zi+1 = ZiAi i=1,2,3…………………n
Z1=1
Zn+1=Z

One stage of Accumulator

• Combining all the input functions for the J and K inputs flip flop A1
produces a composite set of input Boolean functions for a typical stage.

• Each stage in the accumulator must produce the carry for the next stage.

• The logic diagram for one typical stage of the Accumulator is shown
below:
Complete Accumulator

• For a complete accumulator there will be n stages like this. The inputs and
outputs of each stage can he connected in cascade to form a complete
accumulator.