VHDL Simulation with ModelSim Guide
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ScribdTranslationsVHDL Simulation with ModelSim Guide
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ScribdTranslationsUNIVERSITY OF CARTHAGE
NATIONAL ECOLOGY OF SCIENCES AND
ADVANCED TECHNOLOGIES IN BORJ
CEDRIA
Report TP5 VHDL
Getting started with the MODELSIM software
Realized by
KERFAHI Achref(SETP1)
REGAYAMariem(SETP1)
GHARBI Med Amine(SIC1)
M. KERMANI ENSTAB Supervisor
Marwen
Academic Year: 2015/2016
I. Objective of the practical work
The objective of this lab is to take control of a compiler and a simulator for the VHDL language.
This is the ModelSim software from Mentor Graphics. The various steps are presented to achieve the
simulation of an electronic design and subsequently knowing how to describe and validate through simulation
Characteristics of this design.
II. The VHDL language
VHDL is a hardware description language designed to represent the intrinsic behavior.
the architecture of a digital electronic system. Its full name is VHSIC Hardware Description
Language.
The interest of such a description lies in its executable nature: a specification described in VHDL
may be verified by simulation, before the detailed design is completed. Furthermore, the tools of
computer-assisted conception allowing direct transition from a functional description to
VHDL to a logic gate diagram has revolutionized the design methods of digital circuits.
ASIC or FPGA.
The purpose of a hardware description language such as VHDL is to facilitate the development of a circuit.
digital by providing a rigorous method of describing the functionality and architecture
of the desired circuit. The idea is not to have to create a real component, instead using tools.
of development allowing to verify the expected junction. This language actually allows to use
simulators, whose role is to test the operation described by the designer.
The next step is to synthesize this material description to obtain a component that performs the
desired functions, using concrete logical elements (logic gates, flip-flops or registers). These
will be implemented, depending on the technology used, either directly in transistors (in the case of an ASIC), or
based on the programmable elements of FPGAs. After synthesis come the phases of:
Placement: we choose the physical location of the different elements;
Routing: we determine the connections between elements.
These two operations must take into account the resources available on the ASIC (surface) or in the
FPGA (programmable units).
VHDL having a dual function (simulation and synthesis), only part of VHDL is
synthesizable, the other existing only to facilitate the simulation (writing of models
behavioral and detest benches). Depending on the hardware support and the synthesis software used, this
the part may be more or less extensive. In order to obtain synthesizable and portable VHDL, it is
therefore necessary to limit oneself to simple constructions, whose transcription into doors and tilts is
easy to implement. Standard 1076.6 was initiated to try to define a subset of VHDL "of
synthesis
III. The ModelSim 6.5 SE software
The ModelSim SE software is dedicated to the design of ASIC and FPGA, allowing for temporal simulation.
RT level (register transfer level) or gate level, starting from VHDL or Verilog languages.
IV. Some examples
1. Half adder module
a. VHDL testbench code for half adder
LIBRARY ieee;
use ieee.std_logic_1164.all;
entity testbench_demi_add is
end testbench_demi_add;
architecture testbench of testbench_demi_add is
component demi_add is
port (A,B: in bit;
Som, Ref: out bit);
end component;
signal A: bit;
signal B: bit;
signal Som: bit;
signal Ref: bit;
begin
C1: half_add port map (A,B,Sum,Ref);
A <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 60 ns, '0' after 80 ns;
B<='0', '0' after 20 ns, '0' after 40 ns, '1' after 60 ns, '1' after 80 ns;
end testbench;
b. VHDL code for half adder
LIBRARY ieee;
use ieee.std_logic_1164.all;
entity demi_add is
port (A,B: in bit;
Som, Ref: out bit);
end demi_add;
architecture arch_demi_add of demi_add is
begin
Sum <= A xor B;
Ref <= A and B;
end arch_demi_add;
c. Simulation
2. Example 1 of the practical work
1) F=(A.B+C) xor not(A)
2)
A B C F
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
a. Code testbench example 1
LIBRARY ieee;
use ieee.std_logic_1164.all;
entity testbench_example1 is
end testbench_example1;
architecture testbench of testbench_example1 is
component exemple1 is
port (A,B,C: in bit;
F: out bit);
end component;
signal A: bit;
signal B: bit;
signal C: bit;
signal F: bit;
begin
C1: example1 port map (A, B, C, F);
A <= '0', '0' after 20 ns, '0' after 40 ns, '0' after 60 ns, '1' after 80 ns, '1' after 100 ns, '1' after
120 ns;
B <= '0', '0' after 20 ns, '1' after 40 ns, '1' after 60 ns, '0' after 80 ns, '1' after 100 ns, '1' after
120 ns;
C<='0', '1' after 20 ns, '0' after 40 ns, '1' after 60 ns, '0' after 80 ns, '0' after 100 ns, '1' after
120 ns;
end testbench;
b. VHDL code example 1
library ieee;
use ieee.std_logic_1164.all;
entity example1 is port (A, B, C : in bit; F : out bit);
end example1;
architecture arch_example1 of example1 is
signal S1, S2 : bit;
begin
S1 <= A and B;
S2 <= S1 or C;
F <= S2 XOR (Not A);
end arch_example1 ;
c. Simulation
3. 8-input 1-output multiplexer
a. VHDL testbench code for MUX8_1
library ieee;
use ieee.std_logic_1164.all;
use work.mux8_1;
entity test_mux8_1 is
end test_mux8_1;
architecture test of test_mux8_1 is component mux8_1
port(x0,x1,x2,x3,x4,x5,x6,x7,a0,a1,a2:in bit ; s:out bit );
end component;
signal x0,x1,x2,x3,x4,x5,x6,x7,s:bit ;
signal a0,a1,a2:bit ;
begin
c1: mux8_1 port map (x0,x1,x2,x3,x4,x5,x6,x7,a0,a1,a2,s);
x0<='1', '0' after 20 ns , '0' after 40 ns ,'0' after 60 ns ,'1' after 80 ns ;
x1<='0', '1' after 20 ns, '0' after 40 ns, '0' after 60 ns, '0' after 80 ns;
x2 <= '0', '0' after 20 ns, '1' after 40 ns, '0' after 60 ns, '0' after 80 ns;
x3 <= '0', '0' after 20 ns, '0' after 40 ns, '1' after 60 ns, '0' after 80 ns;
x4 <= '0', '0' after 20 ns, '0' after 40 ns, '1' after 60 ns, '0' after 80 ns;
x5 <= '0', '0' after 20 ns, '0' after 40 ns, '1' after 60 ns, '0' after 80 ns;
x6 <= '0', '0' after 20 ns, '0' after 40 ns, '1' after 60 ns, '0' after 80 ns;
x7<='0', '0' after 20 ns, '0' after 40 ns, '1' after 60 ns, '0' after 80 ns;
a0 <= '0', '0' after 20 ns, '0' after 40 ns, '0' after 60 ns, '1' after 80 ns, '1' after 100 ns, '1'
after 120 ns, '1' after 140 ns;
a1<='0', '0' after 20 ns, '1' after 40 ns, '1' after 60 ns, '0' after 80 ns, '0' after 100 ns, '1'
after 120 ns, '1' after 140 ns;
a2<='0', '1' after 20 ns , '0' after 40 ns ,'1' after 60 ns ,'0' after 80 ns ,'1' after 100 ns ,'0'
after 120 ns, '1' after 140 ns;
end test;
b. VHDL Code MUX8_1
library ieee;
use ieee.std_logic_1164.all;
entity mux8_1 is
port (x0,x1,x2,x3,x4,x5,x6,x7,a0,a1,a2 : in bit ;
s : out bit );
end mux8_1;
architecture arch_mux8_1 of mux8_1 is
signal address : bit_vector (2 downto 0) ;
begin
address <= a2&a1&a0;
s <= x0 when (address = "000") else
x1 when (address = "001") else
x2 when (address="010") else
x3 when (address ="011") else
x4 when (address ="100") else
x5 when (address = '101') else
x6 when (address ="110") else
x7;
end arch_mux8_1;
c. Simulation
4. Bascule D
a. VHDL testbench code for D flip-flop
b. VHDL Code D Flip-Flop
c. Simulation