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CMOS Fabrication Contents

1. Silicon Manufacture

a) Crystal Lattice

b) Mono Crystalline Silicon

c) Wafer Cutting

2. Patterning using Photolithography

3. Add Layers

a) Deposition [epitaxy]

b) Oxidation [SiO2]

c) Sputtering [metallization]

d) Spin coating [photoresist]

4. Change Composition

a) Diffusion

b) Ion Implantation

5. Remove Layers

a) Wet Etching

b) Dry Etching

6. Thermal Treatment

a) Annealing

b) Reflowing c) Alloying
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Silicon Manufacture
* Silicon is second most abundantly available element on earth’s
crust.
* Found in the form of silicon-dioxide (silica) or silicates combined
with other elements.
* Reaction:
SiO₂ + 2C → Si + 2CO ↑ (at ~1900°C)
* Obtained silicon is in non-uniform structure.
* A crystal lattice describes the arrangement of atoms in 3-
dimensions.

* A unit crystal of silicon has 18 atoms.

* Poly crystalline silicon and mono crystalline silicon.
* Crystal structure and symmetry determine many physical
properties
(cleavage for diffusion/ion implantation, band structure).
* MOSFET majority circuits → {100} plane
* BJT majority circuits → {111} plane (high tensile strength).

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Mono Crystalline Silicon

Crystal Growth (Czochralski Process)

 Melting of polysilicon: Polysilicon is melted in a quartz furnace

at 1425°C.
 Introduction of the seed crystal: A rotating shaft with a seed
crystal is introduced into the molten silicon.
 Beginning of the crystal growth: The seed crystal initiates the
growth of a larger single crystal as it is slowly pulled upwards.
 Crystal pulling: The crystal is continuously pulled at a rate of 22
mm/hour, allowing it to grow in length.
 Formed crystal with residue: A single silicon ingot is formed,
with some residual molten silicon remaining in the crucible.

Wafer Cutting:
 Silicon ingot is sliced into wafers using a diamond blade or saw.
 Rough edges are removed by polishing the surface.

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 Diameter of wafer 200mm (8inch wafer) - 300mm (12inch

wafer)
 Thickness of wafer 725um - 775um
 Primary Flat defines the orientation of crystal growth

Patterning using Photolithography

 Areas exposed to UV light → become polymerized and resist
developer chemical.
 Areas not exposed → removed when developed.
 The frequency of UV light is 2.2*10^6 HZ

Adding Layers: Deposition

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 Epitaxy is the method of depositing a mono-crystalline film on a

mono-crystalline substrate.
 Substrate acts as the seed crystal.

Chemical Vapor Deposition (CVD):

 Used to grow a silicon layer on a silicon substrate.

 SiCl4 + 2H2 → Si + 4HCl

 Helps increase resistivity of the region (reverse doping).

Plasma Enhanced CVD (PECVD):

 Plasma is a gas with a significant portion of atoms/molecules

ionized between electrodes.

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 Created using RF (radio frequency) or direct current discharge.

 Suitable for temperature-sensitive structures (100–400°C).

 Fast deposition rate.

 Good film quality.
 Suitable for both deposition and etching.

Adding Layer: Oxidation

 The technique forces an oxidizing agent to diffuse into the
wafer at high temperature and react with it.
Si+O2(800∘C1200∘C)SiO2
 Acts as Insulator,
 Window for Deposition
 Surface Passivation

Adding Layer: Sputtering

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 A process that uses ions of an inert gas (argon) to dislodge atoms from
the surface of a crystalline material.
 The atoms then being electrically deposited on the surface of substrate.
 Magnetic field created used to steer the direction.
 Uses = On chip interconnects

Adding Layer: Spin Coating

Spin Coating

 A small amount of coating material is applied on the center of

the substrate.
 The substrate is then rotated at high speed in order to spread
the coating material by centrifugal force.
 SU-8 is a commonly used epoxy-based negative photoresist.

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Changing Composition: Diffusion

 Diffusion is the movement of chemical species from an area of higher
concentration to an area of lower concentration.
 The diffusion process begins with the deposition of a shallow, high
concentration of the desired impurity in the Si surface through windows
etched in the protective barrier layer (SiO2) at a higher temperature.
 Dopants diffuse into undesired regions.

Changing Composition: Ion

Implantation
 Dopants are forcefully added into the silicon substrate in the form of energetic ion
beam injection.
 Frequency of the beam = 1.366 MHZ(standard)
 It will tilt an angle of 3degree to overcome the penetration into greater depth

 Query successful

Comparison: Ion Implantation & Diffusion

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Diffusion Ion Implantation

High Temperature Low Temperature
No Proper control over junction Depth and Good Control over Junction Depth
Concentration and Concentration
Hard mask (SiO2) to protect region of non-
Photo Resist Mask
interest from contamination

Removing Layers: Etching

Wet Etching Dry Etching
Reactive Ion Etching
Plasma Etching

Removing Layers: Wet Etching

 The wafer is immersed in a bath of etchant, to remove oxide and

photoresist layers.
 Buffered hydrofluoric acid (BHF) is used commonly to etch silicon dioxide
over a silicon substrate.
o SiO2+6HF→H2SiF6+H2O
o Where H2SiF6 (Hexaflourosilicic acid) is water soluble.
 Buffered hydrofluoric acid (BHF) is a combination of ammonium fluoride
(NH4F), and hydrofluoric acid (HF) used to control the rate of etching.
 Low Precision etching.
 Isotropic Etching (round sidewalls)

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Removing Layers: Dry Etching

Reactive Ion Etching

 Reactive ion etching (RIE) is a directional etching process utilizing ion

bombardment to remove material.
 Due to the large voltage difference between Electrodes, the positive ions tend to drift
toward the wafer plates, where they collide with the samples to be etched.
 The ions react chemically with the materials on the surface of the samples, but can
also knock off (sputter) some material by transferring some of their kinetic energy.

Removing Layers: Dry Etching

 Dry Etching also known as Plasma Etching.

 The plasma produces energetic free radicals, neutrally charged, that
react at the surface of the wafer.
 Low pressure
 Anisotropic etching (one direction)
 Very High Precision
o A perfectly anisotropic etch produces vertical sidewalls.

Removing layer: Clean

 The RCA clean is a standard set of wafer cleaning steps which need to be performed
before high-temperature processing steps (oxidation, diffusion, CVD) of silicon
wafers in semiconductor manufacturing.
 Removal of the organic contaminants (organic clean + particle clean)
 Removal of thin oxide layer (oxide strip, optional)

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 Removal of ionic contamination (ionic clean)

 Wafers are cleaned using Solvent clean
o followed by a Deionized water (DI) rinse, followed by a
o RCA clean
o followed by DI rinse and then
o HF (hydrochloric acid) dip
o Followed by DI rinse and blow dryer.

Removing Layers: CMP

 Chemical mechanical polishing or planarization is a process of

smoothing surfaces with the combination of chemical and mechanical
forces. It can be thought of as a hybrid of chemical etching and free
abrasive polishing.

Removing Layers: CMP

 Patterning (deposition, lithography, and etch) leaves topography on the

wafer.
 Topography complicates subsequent processing
o Coating over topography is hard (step coverage, shadowing)
o Lithography suffers from depth of focus loss
 Some processes absolutely require planarization (STI, tungsten plugs,
copper damascene process)

Thermal treatment: Annealing, Alloying & Reflowing

 High temperature annealing is needed for a number of applications,

including the repair of implantation damage, the densification of
deposited insulators, the diffusion of dopants, for silicide formation, etc.
 The fabrication of Ohmic contacts frequently includes a high-
temperature step so that the deposited metals can either alloy with the
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semiconductor or the high-temperature anneal reduces the

unintentional barrier at the interface.
 In the case of silicon, one can simply deposit a metal such as aluminum
and obtain a reasonable Ohmic contact. However, subsequent annealing
at 475°C in a reducing ambient such as forming gas (20:1 N2/H2) will
further improve the contact resistivity.

CMOS-FABRICATION

Step1: Substrate

Primarily, start the process with a P-substrate.

Step2: Oxidation

The oxidation process is done by using high-purity oxygen and hydrogen, which are
exposed in an oxidation furnace approximately at 1000 degree centigrade.

Step3: Photoresist

A light-sensitive polymer that softens whenever exposed to light is called as

Photoresist layer. It is formed.

Step4: Masking

The photoresist is exposed to UV rays through the N-well mask

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Step5: Photoresist removal

A part of the photoresist layer is removed by treating the wafer with the basic or
acidic solution.

Step6: Removal of SiO2 using acid etching

The SiO2 oxidation layer is removed through the open area made by the removal of
photoresist using hydrofluoric acid.

Step7: Removal of photoresist

The entire photoresist layer is stripped off, as shown in the below figure.

Step8: Formation of the N-well

By using ion implantation or diffusion process N-well is formed.

Step9: Removal of SiO2

Using the hydrofluoric acid, the remaining SiO2 is removed.

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Step10: Deposition of polysilicon

Chemical Vapor Deposition (CVD) process is used to deposit a very thin layer of
gate oxide.

Step11: Removing the layer barring a small area for the Gates

Except the two small regions required for forming the Gates of NMOS and PMOS,
the remaining layer is stripped off.

Step12: Oxidation process

Next, an oxidation layer is formed on this layer with two small regions for the
formation of the gate terminals of NMOS and PMOS.

Step13: Masking and N-diffusion

By using the masking process small gaps are made for the purpose of N-diffusion.

The n-type (n+) dopants are diffused or ion implanted, and the three n+ are formed
for the formation of the terminals of NMOS.

Step14: Oxide stripping

The remaining oxidation layer is stripped off.

Step15: P-diffusion

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Similar to the above N-diffusion process, the P-diffusion regions are diffused to form
the terminals of the PMOS.

Step16: Thick field oxide

A thick-field oxide is formed in all regions except the terminals of the PMOS and
NMOS.

Step17: Metallization

Aluminum is sputtered on the whole wafer.

Step18: Removal of excess metal

The excess metal is removed from the wafer layer.

Step19: Terminals

The terminals of the PMOS and NMOS are made from respective gaps.

Step20: Assigning the names of the terminals of the NMOS and PMOS

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CHANNEL – STOP IMPLANT/FOX(feils oxide)

 Insulating Layer: FOX is a thick layer of silicon dioxide (SiO2) that acts as
an electrical insulator. Its primary purpose is to isolate individual
transistors and other active devices on a semiconductor chip, preventing
them from interfering with each other.
 Prevents Parasitic Transistors: By creating a thick insulating barrier, FOX
prevents the formation of unwanted or "parasitic" transistors between
devices. A channel stop implant is often performed in the FOX region to
further increase the threshold voltage and ensure this parasitic
 Formation Process: FOX is most commonly created using the LOCOS
(LOCal Oxidation of Silicon) process. This involves masking the active
device areas with silicon nitride and then growing a thick oxide layer in
the unmasked "field" regions through high-temperature oxidation.
 Creates "Bird's Beak": A notable side effect of the LOCOS process is the
formation of a "bird's beak" shape at the edges of the FOX. This is a
gradual tapering of the oxide where it meets the active area, which
consumes some valuable chip real estate.

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 Replaced by STI: Due to the space limitations caused by the bird's beak, the LOCOS
process and its resulting FOX layer have largely been replaced in modern, high-density chips
by a more advanced isolation technique called STI (Shallow Trench Isolation).

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