library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use [Link];
entity d_ff is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end d_ff;
architecture Behavioral of d_ff is
begin
process(d,clk,rst)
begin
if(rst='1')then
q<='0';
elsif(rising_edge(clk))then
q<=d;
qbar<= not d;
end if;
end process;
end Behavioral;
tb
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:25:34 10/27/2025
-- Design Name:
-- Module Name: C:/Users/student/d_ff/d_ff_tb.vhd
-- Project Name: d_ff
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: d_ff
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY d_ff_tb IS
END d_ff_tb;
ARCHITECTURE behavior OF d_ff_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT d_ff
PORT(
d : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : OUT std_logic;
qbar : OUT std_logic
);
END COMPONENT;
--Inputs
signal d : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal q : std_logic;
signal qbar : std_logic;
-- Clock period definitions
-- constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: d_ff PORT MAP (
d => d,
clk => clk,
rst => rst,
q => q,
qbar => qbar
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for 20 ns;
clk <= '1';
wait for 20 ns;
end process;
-- Stimulus process
stim_proc: process
begin
rst<='0';
d<='0';
-- hold reset state for 100 ns.
wait for 100 ns;
d<='1';
-- hold reset state for 100 ns.
wait for 100 ns;
--wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;