SCHOOL OF COMPUTER ENGINEERING
OPEN ENDED LAB REPORT
Name of the Experiment: Submitted to :
2. Combinational : 2-bit Comparator using 1. Mayank Mishra
sop form
2. Arindam Basak
Submitted by :
1. Rishab kharal (24052747)
2. Harshit jayswal (24052684)
3. Abu Anas Molla (24052649)
4. Sujal RAJ San (24052641)
Subject: DSD Lab Report
Programme: - BTECH
Branch: -CSE
Group: - 13
Submission Date: - 2025-10-27
REMARKS ..............................
SCHOOL OF COMPUTER ENGINEERING
OPEN ENDED LAB REPORT
Name of the Experiment: Submitted To:
1. Sequential: Frequency divider using 1. Mayank Mishra sir
D Flip flop
2. Arindam Basak sir
Submitted By:
1. Rishab kharal (24052747)
2. Harshit jayswal (24052684)
3. Abu Anas Molla (24052649)
4. Sujal RAJ San (24052641)
Subject:- DSD Lab Report
Programme:- BTECH
Branch: - CSE
Group: - 13
Submission Date: - 2025-10-27
REMARKS ..............................
OBJECTIVES
Sequential Experiment: Frequency Divider using D Flip-Flop
AIM: To design and implement a frequency divider circuit using D flip flop and
verify that the output frequency is half of the input clock
frequency
To design and implement a frequency divider circuit that produces an output clock whose frequency is
half of the input clock frequency using a D flip-flop. The aim is to demonstrate the divide-by-2 action,
explain the design aspects (logic connections, timing behavior and verification), and verify the output
frequency experimentally or by simulation.
OBJECTIVES
Combinational Experiment: 2-bit Comparator using SOP form
AIM: - To design and implement a 2-bit digital comparator using basic logic
gates, derived from the Boolean expression in sum of product sop form
and verify its truth table
To design and implement a 2‑bit digital magnitude comparator using basic logic gates, derive its
Boolean expressions in Sum‑of‑Products (SOP) form, simplify where appropriate, and verify the
complete truth table by simulation and/or hardware testing the design aspects involved include:
1. Deriving SOP Boolean expressions for outputs: A > B, A = B, and A < B.
2. Simplifying expressions (algebraic reduction or K‑map) and mapping to basic gates (NOT,
AND, OR, XOR).
3. Verifying the circuit by constructing and validating the truth table for all 16 input
combinations (A1A0 vs B1B0).
THEORY
A D flip-flop (Data or Delay flip-flop) is a digital storage element that stores the logic level present
at its D input whenever a clock edge (usually the rising edge) occurs. The output Q of the D flip-
flop follows the input D only at the clock transition and remains constant until the next active
clock edge. This property can be utilized to design a frequency divider circuit, which produces an
output signal whose frequency is half of the input clock frequency.
In this experiment, the frequency divider is realized by connecting the inverted output of the D
flip-flop (denoted as Q̅) back to the D input. This means that the value of D is always the
complement of the current output Q. When a clock pulse arrives, the D flip-flop transfers this
inverted value to the output, effectively toggling its state at every clock edge. Therefore, for every
two clock pulses, the output completes one full cycle — thus dividing the frequency of the input
signal by two.
Mathematically, the operation of the circuit can be expressed as:
Qn+1=D=¬Qn
Here QnQ_nQn is the output before the nth clock pulse, and Qn+1Q_{n+1}Qn+1 is the output
after the next clock pulse. This relation shows that the output changes state (toggles) on every
clock edge. After the next clock pulse, we get,
Qn+2=¬Qn+1=¬(¬Qn)=Qn
This indicates that the output waveform repeats its state every two clock pulses. Hence, the period
of the output waveform (ToutT_{out}Tout) is twice the period of the input clock (TinT_{in}Tin),
which gives the frequency relationship as: fout=fin/2
THEORY
A digital comparator is a combinational logic circuit that compares two binary numbers and
determines their relative magnitudes. In this experiment, we design a 2-bit comparator that
compares two 2-bit binary numbers, A (A1A0) and B (B1B0). The comparator produces three
outputs: one for A greater than B (GT), one for A equal to B (EQ), and one for A less than B (LT).
Only one of these outputs will be HIGH (logic 1) at any given time, ensuring that the comparator
produces a unique result for each input combination.
The comparison is based on binary logic rules. The most significant bits (MSBs) are compared first.
If the MSBs are different, they determine the output directly. If the MSBs are equal, the comparison
then depends on the least significant bits (LSBs). The Boolean equations for each condition can be
derived using logical relationships and expressed in the Sum of Products (SOP) form.
REQUIREMENTS
SOFTWARE REQUIREMENT
For the design and verification of the frequency divider circuit using a D flip-flop, both simulation
and hardware implementation setups can be used depending on the laboratory environment and
available facilities. In the case of simulation, the experiment can be performed using standard digital
circuit simulation platforms such as Multisim, Proteus, LTSpice, Logisim, ModelSim, or Xilinx
Vivado
HARDWARE REQUIREMENT
The setup requires a D-type flip-flop integrated circuit, such as the 74LS74 or 74HC74 dual D flip-
flop IC, which operates on a regulated +5V DC supply. A stable clock source, such as a function
generator or a 555-timer configured in a stable mode, is required to provide the input clock signal.
REQUIREMENTS
SOFTWARE REQUIREMENT
For software-based simulation, various digital logic simulation platforms can be used to design and
verify the 2-bit comparator circuit. Logisim is one of the simplest tools suitable for students as it
allows easy schematic design and real-time output visualization. Vivado 2016.1 and Proteus Design
Suite are advanced simulation platforms that provide detailed circuit analysis, waveform
visualization, and logic verification capabilities.
HARDWARE REQUIREMENT
For hardware implementation, the 2-bit comparator can be constructed using standard TTL
(Transistor-Transistor Logic) ICs on a breadboard. The primary components include basic logic
gate ICs such as IC 7408 (AND), IC 7432 (OR), IC 7404 (NOT), and IC 7486 (XOR), which can be
combined to form the required logic expressions. The inputs A1, A0, B1, and B0 can be provided
through SPST switches to represent binary combinations, while the outputs GT, EQ, and LT can be
displayed using LEDs connected through current-limiting resistors. A 5V DC regulated power
supply is necessary to operate the TTL ICs.
CIRCUIT DIAGRAM
At the gate level, the D flip-flop can be constructed using basic logic gates such as NAND, NOR, and
NOT gates. A typical D flip-flop consists of a pair of cross-coupled NAND or NOR gates that form
an SR latch, along with additional gates to ensure that the D input value is transferred to the latch
only during the active clock transition. Once the D flip-flop is formed, its inverted output (Q̅) is
connected back to the D input.
FIGURE :- 1.1 Frequency Divider Circuit Using D Flip-Flop
CIRCUIT DIAGRAM
The circuit uses fundamental logic gates such as AND, OR, NOT, and XNOR to realize the derived
equations for GT, EQ, and LT. The gate-level design starts with two XNOR gates that compare the
corresponding bits (A1 with B1 and A0 with B0) to generate equality outputs.
FIGURE:- 2.1 Circuit Diagram of 2-Bit Digital Comparator
HDL CODE DEVELOPMENT
VERILOG CODE FOR FREQUENCY DIVIDER USING D FLIP-FLOP
module freq_div_dff(input wire clk, wire rst, output reg);
always @ (posedge clk) begin
if (rst)
q <= 1'b0;
else
q <= ~q;
end
endmodule
EXPLAIN:
clk → input clock signal.
rst → synchronous reset (initializes output to 0).
q → output signal, frequency is half of clk
HDL CODE DEVELOPMENT
VERILOG CODE FOR 2-BIT COMPARATOR USING SOP FORM
module comparator_2bit (
input [1:0] A,
input [1:0] B,
output GT,
output EQ,
output LT
);
wire A1B1_eq, A0B0_eq;
assign A1B1_eq = ~(A [1] ^ B[1]);
assign A0B0_eq = ~(A [0] ^ B [0]);
assign EQ = A1B1_eq & A0B0_eq;
assign GT = (A [1] & ~B[1]) | (A1B1_eq & A [0] & ~B [0]);
assign LT = (~A [1] & B[1]) | (A1B1_eq & ~A [0] & B [0]);
end
endmodule
HDL CODE DEVELOPMENT
TEST BENCH CODE FOR FREQUENCY DIVIDER USING D FLIP-FLOP
module tb_freq_div_dff();
reg clk;
reg rst;
wire q;
freq_div_dff uut (
.clk(clk),
.rst(rst),
.q(q)
);
initial clk = 0;
always #10 clk = ~clk;
initial begin
rst = 1;
#40;
rst = 0;
#400;
$finish;
end
endmodule
EXPLAIN :
Clock toggles every 10 ns → 50 MHz input clock.
Reset applied at the start for proper initialization.
Output q toggles every two clock cycles → frequency divided by 2.
HDL CODE DEVELOPMENT
TEST BENCH CODE FOR 2-BIT COMPARATOR USING SOP FORM
module tb_comparator_2bit;
reg [1:0] A, B;
wire GT, EQ, LT;
comparator_2bit uut (
.A(A),
.B(B),
.GT(GT),
.EQ(EQ),
.LT(LT));
integer i, j;
initial begin
$display ("A B | GT EQ LT");
$display (" ---------------- ");
for (i = 0; i < 4; i = i + 1) begin
for (j = 0; j < 4; j = j + 1) begin
A = i;
B = j;
#10; // Wait for output to settle
$display ("%b %b | %b %b %b", A, B, GT, EQ, LT);
end
end
$finish;
end
endmodule
RESULTS
FIGURE: 1.2 Test bench of Frequency Divider Using D Flip-Flop
TABLE:- 1.1 T r u t h Table of Frequency Divider Using D Flip-Flop
RESULTS
FIGURE 2.2 : Test bench of 2-bit Comparator using SOP form
TABLE 2.1 : Truth Table of 2-bit Comparator using SOP form
DISCUSSION OF RESULT
In this experiment, the frequency divider circuit using a D flip-flop was designed to produce an
output signal with half the frequency of the input clock. During simulation, the output waveform
confirmed the expected behavior: the Q output toggled on every rising edge of the input clock,
resulting in a frequency exactly equal to half of the input frequency. The timing diagram obtained
from simulation clearly shows that the output has a 50% duty cycle and maintains a consistent
period that is twice the input clock period.
For hardware implementation, the measured output waveform closely resembled the simulated
waveform; however, minor deviations were observed. These deviations can be attributed to factors
such as the propagation delay of the D flip-flop, finite setup and hold times, and slight signal
distortion or jitter in the input clock. Additionally, the LED indicator used for visual observation
may introduce a small delay due to its turn-on time, which slightly affects the measured timing. The
oscilloscope probe loading and limited bandwidth may also contribute to small differences between
simulated and measured results.
Overall, despite these minor deviations, the output frequency was effectively half of the input
frequency, confirming the correct operation of the divide-by-2 circuit. The experiment demonstrates
that the D flip-flop can reliably function as a frequency divider both in simulation and in hardware.
Parametric variations such as changes in input clock frequency or supply voltage were not
significant enough to alter the toggle behavior, highlighting the robustness of this simple frequency
division design.
DISCUSSION OF RESULT
In this experiment, a 2-bit comparator was designed and implemented using the SOP (Sum of
Products) form to compare two 2-bit binary numbers and determine whether one is greater than,
equal to, or less than the other. The simulation results showed that the outputs correctly followed
the expected behavior for all input combinations, as derived from the SOP expressions. When
implemented on hardware, the comparator also produced the correct outputs, although minor
deviations were observed. These differences can be attributed to factors such as propagation delays
of real logic gates, switching noise, variations in power supply, and the inherent limitations of
physical components compared to idealized simulation models. Despite these small discrepancies,
the overall functionality of the comparator was successfully verified, demonstrating the accuracy of
the SOP-based design and highlighting the importance of comparing simulation and hardware
results to understand practical implementation challenges in digital circuits.
CONCLUSION
implemented, and verified. The circuit produced an output signal with exactly half the frequency of
the input clock, demonstrating the toggle behavior of the D flip-flop when its D input is connected
to the inverted output. Both simulation and hardware implementation confirmed the expected
functionality, with only minor deviations in the hardware due to propagation delays, setup and hold
times, and slight signal distortion. This experiment highlights the simplicity and effectiveness of
using a D flip-flop as a divide-by-two frequency divider, and it forms the basis for constructing more
complex frequency dividers and binary counters in digital systems.
CONCLUSION
The 2-bit comparator designed using the SOP (Sum of Products) compares two 2-bit binary
numbers and provides correct outputs for all possible input combinations. The experiment verified
that the SOP-based logic expressions accurately implement the desired functionality, both in
simulation and on hardware. Minor deviations observed in hardware were due to real-world
limitations such as propagation delays, noise, and component tolerances. Overall, the experiment
demonstrates the effectiveness of the SOP method in designing combinational logic circuits and
highlights the importance of validating designs through both simulation and practical
implementation.
CONTRIBUTION
RISHAB KHARAL (24052747): Editor of this report
HARSHIT JAYSWAL (24052684): Research the topics
SUJALRAJ SAN (24052641): All the software part ie , Design and Testbench
ABU Anas Molla (24052649): Printing the report with proper documentation
and giving idea to design
............................................... ...............................................
RISHAB KHARAL HARSHIT JAYSWAL
............................................... ...............................................
SUJAL RAJ SAN ABU ANAS MOLLA
CONTRIBUTION
RISHAB KHARAL (24052747): Editor of this report
HARSHIT JAYSWAL (24052684): Research the topics
SUJAL RA J SAN (24052641): All the software part ie, Design and Testbench
ABU Anas Molla (24052649): Printing the report with proper documentation
and giving idea to design
............................................... ...............................................
RISHAB KHARAL HARSHIT JAYSWAL
............................................... ...............................................
SUJAL RAJ SAN ABU ANAS MOLLA