Minimum microprocessor system

Processor
The central processing unit (CPU) is where data is manipulated. The CPU is contained in a
very small chip called microprocessor. They have 2 basic parts: control unit and arithmetic logic unit.
Each instruction in the instruction set is accompanied by a microcode, which are instructions.
very basic ones that tell the CPU how to execute the instructions.
Operation of the microprocessor
The most important elements of a microprocessor are: Arithmetic Logic Unit (ALU) and Unit of
Control (UC).
The arithmetic logic unit is the one that performs the operations of the microprocessor, it is responsible for adding,
subtract, perform logical operations, etc. with the operands that arrive from registers X and Y.
The control unit governs all the other elements with the control lines that turn on.
turning off synchronously with the clock signal.

Processor in minimum system

A microprocessor is capable of handling two elements of information: instructions and data. The
instructions form the programs that run on the machine and the data are the elements with which
those programs work.

Minimum digital system (opto-electronic)

In a minimum system, the input device has the function of being the interface between the user and the
system, that is to say, it captures the information so that the system can interpret it.
In the proposed system, the input device is the computer keyboard; so that when entering
the information is instantly encoded and displayed on the LCD screen, thanks to the software
developed.
Structure of a program
Todos los programas escritos en C se componen de una o mas rutinas o funciones, no teniendo por que estar
all in one file (that is, a program can be written whose code is spread over several
files).

EXTERNAL ARCHITECTURE OF THE 8088 MICROPROCESSOR

Address, data, and control bus.

In the 8088, the address, data, and control bus is divided into three parts:
a. The 8 least significant bits of address/data (AD0–AD7) multiplexed between addresses and data.
b. Los 8 bits centrales (A8–A15) No multiplexados.
c. The 4 most significant bits (A16–A19) multiplexed between addresses and control signals.
You can work with multiplexed or demultiplexed buses.
AD7–AD0, address and data bus: They are multiplexed between address buses (T1) and data buses (T2,
T3, Tw, T4) and contain the 8 least significant bits: They remain in a high impedance state during the
interrupt and bus request recognition.
A15–A8, address bus: It has the upper half of the addresses (T1, T2, T3, Tw, T4), they are not
multiplexed and remain in high impedance during the interruption and request recognition.
bus.
A19–A16 / S6–S3, address and status bus: They are multiplexed between the 4 most significant bits.
of addresses (T1) and status (T2, T3, Tw, T4)
In the I/O case during T1 they remain at zero.
S6 is always at 0.
S5 indicates the condition of the interrupt flag IF.
S3 and S4 indicate which segment is being accessed.
RD, reading: When it is at 0 (T2, T3, Tw) it indicates that the data bus can receive data. It is guaranteed that
During T2 it will be high until the 8088 bus is in high impedance.
INTR, interrupt request: Input that is shown in the last clock cycle of each interrupt for
determine if the 8088 should enter an interrupt acknowledgment operation. It can be
masked. It syncs and is active in high.
TEST, test: It is an input used by the WAIT instruction. If TEST=0, WAIT functions as a NOP.
If TEST=1, WAIT waits for TEST to become 0. It is used to synchronize with external devices.
NMI, non-maskable interrupt: It is a positive edge active input that causes an interrupt.
of type 2. The interrupt is completed at the end of the current instruction and is internally synchronized.
RESET, restoration: For restoration, it must remain high for at least 4 clock cycles and is activated.
on the negative flank.
CLK, clock: Clock input that must have a duty cycle of 33%.
VCC, power supply: 5V ± 10%, reference for digital logic.
GND, ground:0V, reference for digital logic.
MN/MX, minimum mode, maximum mode.
The 86/88 will be able to operate in one of two possible modes defined as: Maximum Mode and Minimum Mode.
The mode to be selected will depend on the specific application to be implemented.
Minimum Mode: Simple applications for small systems; it behaves similarly to a Microprocessor.
8 bit but 16 internally.
Maximum Mode: More complex applications, generates almost all compatible signals for the
implementation of the Multibus standard. Allows multiple processors to be supported on the Bus. The CPU cannot
generate the control signals of the system directly and is assisted by the 8288 Bus controller.
There is a terminal called MN/MX that selects the working mode.
If MN/MX = 1 => Maximum Mode.
If MN/MX = 0 => Minimum Mode.
IO/M, memory or I/O state line: Indicates whether the address is for memory or I/O. Stays high.
impedance during a bus request acknowledgment.
WR, writing. It is a signal that indicates that the 8088 will write to memory or I/O.
It is activated (low) during T2, T3, and Tw of a write cycle and indicates that the bus contains valid data.
Remains in high impedance during a bus request recognition.
INTA, recognition of interruption.
Output that is activated (low) during T2, T3, and Tw of each interrupt recognition cycle. It is a
response to the INTR input and is used as a read pulse in an interrupt recognition cycle.
ALE, enabling the steering lock: Exit that indicates (when high during the lower part of the clock
From T1) that there is a valid address on the bus. ALE never remains in a high impedance state.
DT/R, transmit/receive data: Indicates that the data bus transmits data (DT/R=1) or receives it (DT/R=0)
This signal is necessary to enable the external data bus coupling circuits.
It remains in high impedance during a bus request acknowledgment.
DEN, data enablement.
Output used to enable the coupling circuits of the data bus
external.
It is activated low during each memory access and interrupt cycles.
For INTA reading or cycles, it is activated from the middle of T2 to the middle of T4.
For writing cycles, it is activated from the beginning of T2 to the middle of T4.
Remains in high impedance during a bus request acknowledgment.
HOLD, request for direct access to memory.
If HOLD=1, the 8088 stops executing the current program and brings its address, data, and control bus to high.
impedance.
If HOLD=0, the 8088 executes programs normally.
Requires external synchronization.
HLDA, response to the direct memory access request: Output indicating (HLDA=1) that the 8088 has
granted the buses (this is the response of the 8088
at the entrance HOLD)
SSO, status line: This output signal is combined with IO/M and DT/R to decode the cycle function.
the current bus.
The bus cycle consists of at least 4 clock cycles, which are called
T1, T2, T3, and T4, as shown in the following figure.
M IO

The addresses are issued during T1 and the data transfer occurs between T3 and T4.
In T1: The addresses are sent and the control signals ALE, DT/R, and IO/M are provided.
In T2: The DEN, RD (read) or WR (write) signals are provided. In the case of writing, the...
Data that will be written to the data bus. At the end of T2, the READY signal is shown.
In T3: Time is given to the memory to access the data. In the case of a read cycle, the bus of
data is shown at the end of T3.
In T4: All control signals are deactivated to prepare for the next bus cycle.
At the moment, the positive flank of WR transfers data to memory, which are activated and written when the
signal WR returns to 1.
In T2: After the emission of the addresses, the 8088 emits the data to be written in the addressed location.
This data remains valid at least until the middle of T4.
During T2, T3, and Tw, the 8088 sends the write control signal (WR) which goes active in the
beginning of T2. The data is written to memory on the positive edge of WR.
The RD signal in the reading is slightly delayed compared to the WR in the writing to allow time for the
bus remained in high impedance.
Reading cycle
It begins at T1 with the appearance of the ALE signal, whose negative edge is used to latch the addresses.
which are valid on the address/data bus (AD0–AD7)
The address lines A8–A15 do not need to be latched as they remain valid throughout the cycle.
bus.
From T1 to T4, the IO/M signal indicates whether it is a memory operation or an I/O device operation.
In T2, the addresses are taken from the address/data bus and the bus is set to high impedance (AD0–AD7)
The read control signal (RD) appears on T2 and causes the addressed device to enable its bus.
data.
Some time later, the valid data about the bus should be available.
When the 8088 returns the RD signal to a high level, the addressed device will put its output in high impedance.
data output.
CIRCUIT TO GENERATE THE CLOCK PULSE.
In addition to the circuit for the signaling of the μP proposed by the manufacturer (8284A), which is used for CLOCK
And RESET, we can use other circuits, one of which is proposed below:
We take the operating frequency and the duty cycle percentage from the microP specification sheet.
For low speeds, we can take 50% as the duty cycle; since the oscillation is determined by the network.
RC, we propose the value of C and
we calculate R, adjusting the obtained value to the nearest market value.
Generally, we use inverters for this calculation example: we take a frequency equal to 2MHz, as
inverter a Schmitt trigger MC74HC14AC and a ceramic capacitor of 0.001μF. The circuit to be used
is shown below:

For the calculation of the resistance R, the previous data and the ones corresponding to the Schmitt trigger are considered.
the values obtained from the reference tables are: VT+ = 2.7V VCC = 4.5V VT- = 1.8V
The formula for frequency is given by:

Substituting values:

Isolating R and substituting the values of f and C:

CIRCUIT TO GENERATE THE RESET SIGNAL.

The μP requires that the minimum duration time at this terminal be 50 μs. Therefore, we can use the
Intel 8284A integrated circuit that generates
the clock pulse and the reset one, or alternatively, do it using an inverter and an RC network that ensures the timing of
duration of 50 μs.
We must design an RC circuit to ensure at least 50 μs of duration with a Schmitt trigger.
(inverter) considering the parameters VT+ and VT- of said inverter.
In the design, we will use the formulas of the transient effect, considering the data from the Schmitt trigger as:
VT- = 1.8V = VC and VCC = 5V.
For the RC network with Schmitt trigger, the following development is obtained:

We propose C = 0.1 μF and solving for R:

The circuit for restoration is:

CIRCUIT TO DEMULTIPLEX THE ADDRESS BUS OF THE DATA BUS AND

CONTROL.
Demultiplexing of channels.
The address and data bus of the 8086/8088 is multiplexed to reduce the number of terminals.
required in the integrated circuit. Unfortunately, this increases the designer's workload with the task of
multiplex the information contained in these terminals.
Why not leave the channels multiplexed? Memory and I/O require that the address remains
Validates and establishes a reading or writing cycle. If the channels are multiplexed, there are direction changes.
in the memory and in the I/O what causes reading or writing data in the wrong locations.
microprocessor and memory and I/O in the system and 3) a control channel that applies control signals in
the memory and I/O cause reading or writing data in wrong locations.
Demultiplexing of the 8088.
The following figure shows the 8088 microprocessor and the components required for demultiplexing.
their channels. In this case, two transparent registers 74LS573 are used to demultiplex the connections
AD7-AD0 of the address and data bus in the multiplexed terminals A19 and S6-A16/S3.
These records, with D-type multivibrators that are like wires, when the enable signal (ALE) of
the address becomes a logical 1 transfers the inputs to the outputs.
After a short time, ALE returns to the logical 0, which causes the registers to remember the inputs in
the moment of the change to a logical 0. In this case, ~remember~ from A7-A0 in the lower register and to A19
up to A16 in the upper register.
This produces a channel of independent addresses for terminals A19 to A0 that allow for
8088 addresses 1MB of memory space. The fact that the data channel is separate allows
connect it with any 8-bit memory peripheral device.
The following figure illustrates an 8088 with three multiplexed channels: Addresses (A19 to A0 and
BHE), the data (D15 to D0) and the control (IO/M, RD and WR)
Demultiplexing of the 8086.
The 8086 requires separate channels for addresses, data, and control. The main difference is the number of
multiplexed terminals. In the 8088 only AD7 to AD0, A19 and S6 to A16 and S3 are multiplexed. In
In the case of the 8086, the multiplexed terminals include AD15-AD0 and A19 and S6 to A16 and S3 BHE/S7. There is
to demultiplex all these signals.
For the 8086, the circuit is almost identical to the following figure except that a 74LS573 will be added.
additional for demultiplexing the address/data terminals of the channel AD15-AD8 and BHE/SE7, was added
at the input of the 74LS573 at the top to select the high bank in the 16 memory system
bits of the 8086. Here the memory and the I/O system see the 8086 as a device with a channel of
addresses or 20 bits (A19-A0), a 16-bit data channel (D15-D0) and a control channel of three lines
(IO/M, RD and WR)

The coupled system.

If there are more than 10 logical loads connected at any terminal of a channel, the totality must be coupled.
8086 or 8088 system. The demultiplexed terminals are already connected to the transparent registers.
74LS573, which have been designed to handle the high capacitance channels found in systems
of microcomputers. The output currents of the registers have been increased so that they can be
handle more TTL load units; a logical output of 0 provides up to 32mA of current dissipation
and a logical output provides up to 5.2mA of current.
Once we have demultiplexed the address bus from the data and control, we can connect blocks of
RAM and/or PROM and parallel I/O ports or cards containing several parallel I/O ports. Also
We can connect serial ports, as described in the topic of memories and I/O.

ORGANIZATION AND INTERNAL ARCHITECTURE OF THE CPU

Block diagram

The basic functional blocks are: the central processing unit (CPU), the main memory, and the
input-output processor.

Central processing unit: this is responsible for interpretation and execution of

instructions contained in the main memory, the communications between the CPU and the main memory
They are carried out through 2 functionally distinct channels: the address channel and the data channel.
To introduce a specific instruction into the memory, the CPU sends the address of that memory
instruction through the address channel and receives through the same medium the instruction that is at that address.
Part of the instruction is used by the CPU to identify the operation. This part is called the code of
operation of the instruction. The remaining information is used to determine the location or locations of the
data with which the operation will be carried out.
The action of reading an instruction in the CPU and preparing it for execution is called the cycle of
search. To complete an instruction, the CPU decodes the opcode, generates the signals of
Controls are needed to input the required operands and to control the execution of the instruction.
For example, assuming that the specified operation consists of adding 2 required numbers in 2
registers of the CPU and store the result in a third CPU register. To carry out this instruction, the
CPU will identify the 2 registers and generate the appropriate control signals to connect the registers to the
arithmetic and logic unit (ALU).
The CPU would also make the ALU function as an adder and direct the output to the third register. The
The process of completion that specifies a function is called an execution cycle.
The names search cycles and execution cycles derive from the cyclical nature of the operation of the
a computer once it starts operating repeats the search and execution cycles in a manner
continue. To refer to each cycle, the term machine cycle is often used.
logic for example AND, OR and a set of records dedicated to data storage in the CPU and
certain control functions.

The CPU contains a set of high-speed temporary data storage locations.

call register. Some of the records are dedicated to control, and only the control unit has
access to them. The remaining records are general use records and the programmer is the user
who has access to them.
The following must be included in the basic set of control records:

1) Contador de programa (PC).

2) Memory Address Register (MAR).
3) Data registration (DR).
4) Instruction Register (IR).
5) Program Status Word (PSW).

1)(PC): The function of the PC is to track the instruction by searching (capturing) in the
next machine cycle, therefore it contains the address of the next instruction to be executed. The PC is
modified within the search cycle of the current instruction by adding a constant. The
The number added to the PC is the length of an instruction in words.
Therefore, if an instruction has a word length, 1 is added to the PC, if an instruction has
two words long, add 2, and so on.

2) Memory Address Register (MAR): it acts as a link register between the CPU and the
address bus. When access to memory is achieved, the address is placed in the MAR by the
control unit and it remains there until the transaction is completed. The number of bits in the MAR
is the same as the address channel.
The difference that exists between the PC and the MAR is that during the execution cycle of an instruction, the
PC and the MAR serve the same purpose. However, many of the machine's instructions refer to
the memory and operate with the data that is in it. Since the address of the data is usually different from the
next instruction requires the MAR.

3) Data registration: the function of the RD is to provide a temporary storage area.

(intermediate, accumulated or buffered) memory of data that is exchanged between the CPU and memory. The data
they can be instructions (obtained in the execution cycle) or operand data (obtained in the cycle of
execution). Due to its direct connection with the data channel, the RD contains the same number of bits as
said channel.

4) Instruction Register (IR): it is a register that holds the operation code of the instruction.
throughout the machine cycle. The code is used by the CPU control unit to generate the
appropriate signals that control the execution of the instruction. The length of the ER is the length in bits of
operation code.

5) Program Status Word (PSW): the status or condition word of the program stores
relevant information about the program that is currently running. For example, upon completing a function of the
The arithmetic logic unit modifies a set of bits called codes (or condition signals). These bits
They specify whether the result of an arithmetic operation was 0 or negative or if the result overflowed.
The program can check these bits in the following instructions to conditionally change its
control flow according to its value.
In addition, the PSW contains bits that enable the computer to respond to service requests.
asynchronous signals generated by Input-Output devices, or conditions of internal error. These signals
they are called interruptions.
The remaining registers that can be found in a microprocessor are general-purpose. These
they are used to temporarily store information. They also retain operands that participate in
ULA operations.
Sometimes the computer's instruction set and the addressing scheme of the
architecture restricts the use of some of these registers.
Although in all machines the information contained in the register can be manipulated as data.
During the execution of some instructions, the data is used explicitly to decide.
a memory address. The advantage of using registers to hold operation data is speed.
Type of instructions

Instructions can be classified into 5 categories:

1. Instructions in arithmetic and logic.

2. Data movement instructions.
3. Block data operations.
4. Program control instructions.
5. Input - Output Instructions.

1) Instructions of Arithmetic and Logic:

Among them are binary operations, which require two operands and produce a result.
unique. Addition, subtraction, multiplication, and division are standard operations in most of the
machines except for some mini-computers and microprocessors. The logic operations
included in the set of instructions are the operations AND, NAND, NOR, XAND, XOR.
Also within the instructions of arithmetic and logic are the operations. of
displacement and rotation.

2) Data movement instructions:

This instruction results in copying data from one operand location to another; in addition to the
operation code, these instructions require information that identifies the source operands and
destinations. On a general-purpose computer, data can be moved from:

record by record.
Memory registration.
Memory to register.
Memory to memory.

3) Block data operations:

They are those that are performed with a set of operands and not with a single operand. Also within
this instruction is the program control one. This makes it possible for a program to adapt to the
inherent sequence of the computer machine cycle. In other words, they can be bypassed.
instruction sections as a result of the activation of a conditions code or as a result
program design director.

4) Program control instructions

Input-output instructions:

From the point of view of programming for access to memory or a peripheral, it simply
it requires the same set of instructions. These systems are referred to as Input - Output systems.
mapped by memory.
The programming of a device in these systems requires knowledge of this device and its
characteristics, although no special instructions are needed. The device is characterized as a
set of memory locations that are divided into two subcategories: a set of state registers
for control and information record.

State and control register. These usually contain information about inactive, occupied state, etc.
This log also stores control information, such as the type of parity and the
data transmission speed.
The information contained in the state and control records is primarily used to provide
a global image of the hardware when it is in the program

Information record: these constitute an intermediate memory for the information that is transferred
between the CPU and the peripheral. In the case of a device, data is transferred on a character basis by
character and there are usually only two registers. One that holds data from the CPU to the device and another that is used
device data to the CPU. If the programmed Input - Output is performed on a unidirectional device
(only transmits or only receives) then only one record will be needed.

Memory
 An operating system is a set of programs that makes it possible for the user of a system to
computing has controlled access to its resources, among those resources are the CPU, memory and
Input-Output devices. The operating system allocates time to the CPU, distributes space
available in memory, assigns and controls Input - Output devices for each user. These
functions are performed transparently, meaning the programmer writes the program as if everything
the computer system was dedicated to that program. To offer some features of the system
the architecture of the machine must have certain properties. First, the machine must have
at least 2 different modes of operation.
One mode is called supervisor mode and the other user mode.
When the machine is in supervisor mode, the CPU can execute all the instructions of the
machine. This is the operating mode in which programs from different operating systems run.
which gives control of the system. All service requests from peripheral devices go through the
operating system since the Input - Output instructions can only be issued when the machine
is in supervisor mode.
In user mode, the CPU cannot execute the entire instruction set (in particular, it cannot execute the
allows the execution of machine control instructions and Input - Output.

Organization of memory

Memory is a capacitor that retains current if it is 1 and if not, it is 0; one capacitor is needed per bit.
For example, 32 Mb is equal to 32000000 bytes, that is, 32000000 * 8 capacitors.

+ -

There are two types of memory: dynamic memories and static memories. The memories that are
are usually used in computer systems (RAM) are dynamic, leaving the static ones relegated to
somewhat special applications such as being able to keep data in them after being disconnected
equipment and feeding these through batteries.
Static memories have a number of disadvantages compared to dynamic ones; for example
they have a slower response than the dynamics and their integration is more difficult as it requires more electronics
to create the bistable cell that is responsible for generating the corresponding logical 0 or 1 bit.
Another problem is its higher consumption, as its internal structure is more complicated than the
from a dynamic memory.
Dynamic memories are the most widespread and represent the bulk of the computer's RAM.
They have the advantage of having a higher speed compared to most memories.
storage capacity and lower consumption. On the downside, they have the disadvantage that
they require a special electronics for their use, the function of this electronics is to generate the refresh of the
memory. The need for refreshes of dynamic memories is due to their operation,
since it is based on generating the information it contains for a period of time. After this period, the signal
the contents of the bistable cell are lost. To prevent this loss, it is necessary that before
as time elapses, the maximum duration that memory can hold the signal, a reading of the value that it has is made
and recharge it.
It is important to consider that each bit of memory corresponds to a small capacitor to which it
we apply a small electric charge and maintain it for a time based on the constant of
download. Usually, the memory refresh is done cyclically and when the DMA is working.
Normal mode memory refresh is managed by the channel controller, which also fulfills the function.
to optimize the time required for the operation of the refreshment.
Possibly, on more than one occasion, parity errors in memory appear on the computer due to
that the memories being used are of an inadequate speed since they discharge.
before they can be refreshed.

Memory distribution

The distribution of memory within the computer is commonly referred to as a memory map and in it is
It is possible to observe in which zone the operating system records and programs are located. Of
according to the number of bits handled by the microprocessor, it is the maximum allowed capacity that can be
direct on the machine.
Regardless of this memory availability, the real addressing limit will be given by
by the operating system being used, for example the D.O.S. operating system regardless of
the installed memory can address a working area of 640 Kb.

Input - Output Devices

physical and electrical characteristics of the devices, the interface or controller with which the central processor interacts and the
support of the operating system software in use.
The Input-Output unit can actually consist of many interfaces or controllers, including a
special-purpose Input - Output processor but managed by the CPU or both.
The Input-Output problem can generally be restricted from other logical considerations and
electric signals in a computing system because it requires a conversion in one or several of the following
areas:
Speed: data transfer speed
Logic: data format, encoding.
Electrical: signal levels, analog-digital and digital-analog modalities.
Physics: electromechanical, optical, audio functions, etc.

Input-Output operations almost always require a speed change to synchronize the CPU.
with the Input-Output device. This imposes restrictions on both hardware and software. For
For example, the most well-known peripheral, the video terminal, can typically be updated through a
serial communication line, at a speed not exceeding 960 characters per second, a printer
matrix in which electromechanical components operate at 2000 characters per second. However
a CPU can process instructions hundreds or thousands of times faster than this. It also has to handle
multiple input-output devices simultaneously and perform other calculation functions instead of
wait for each input-output operation to complete.
In input-output transactions, there are always operations between the CPU and the peripheral and a
support of a logical protocol that often involves synchronized data transfer communications
(request and acknowledgment). The specification and overall design of the device influence the logical format.
from the data. Furthermore, almost all Input-output involves a fundamental change in representation
electrical or physical information.
Inside the computer, data and control signals usually take the form of levels of
voltage or according to a given logic.
The input-output operation often involves a conversion between analog, mechanical, magnetic,
of audio or another form for storage, transmission, or display of data. It is considered the field of
Input-Output from 3 main perspectives: hardware, software, and design.

Types and examples of devices

Four main classes of techniques are commonly applied either individually or in combination to
control the input - output data transfer

1. Input - Output controlled by program: the processor monitors all Input transfers.
Output through order initiation and device status verification. This technique...
used in specialized applications and device diagnostics. The Input - Output by program uses
the hardware interface in a simpler form but does not efficiently utilize resources.
2. Input - Output by Interrupts: the functions are initiated under the control of the program but t
Synchronization is managed through interruption requests to the hardware and the associated device.
interrupts the routine service. They are used in low or medium speed applications in an environment
specialized or multiprocessor. The Input - Output interrupt-driven uses hardware of
relatively low complexity and allows for efficient software design.
3. Direct Memory Access (DMA): the Input-Output transfer of a block of data
complete is established under the control of the program and is implemented with special-purpose hardware that
transfers data directly to or from main memory. This occurs without further intervention from the CPU.
concurrently with the execution of the program. DMA is used in medium-speed devices or
highly efficient registration but requires a more complete hardware interface. Among the most common uses
Commonly included are tape or magnetic disk controllers, linking between processors and processors.
high-speed graphics.
4. Memory-mapped input-output: data transfer occurs between the CPU and the
logical region of the addressable space of the program, which is actually part of an Input device.
Output, like an image screen or an address channel instead of the main memory. This
the technique allows both the manipulation of the data program and direct transfers between the
input-output device and the final storage of the information. The Input-Output mapped by
directions is an efficient and transparent mechanism used with structured devices, it is not a
not an extension of the DMA but an alternative technique for certain applications.

Input-output channel structures

The Input-Output configuration is generally the least standardized section of a

applications. Furthermore, the Input-Output configuration tends to change as it develops and expands.
the system.
It is very desirable to be able to add or remove devices without having to reconfigure the machine.
basically minimizing both cost and complexity at the same time. The fundamental method to achieve
these goals are the design of the hardware and the modularity of that design.
The usual vehicle to achieve this in the input-output system is the common input-output channel.
In this channel, input-output devices, the CPU, and the main memory are interconnected, and it allows
flexible communications between these units. The main functions of the Input-Output channel are
possible that multiple devices:
They transfer information through common data trajectories by sharing and reducing complexity.
of the hardware.
2) Devices are added or removed simply by plugging or unplugging their cables (plug and
play).
3) Link via a mechanism, the Input-Output channel using logical specifications,
standardized electrical and physical. This standardization makes it possible for entire families of
computers with varying levels of performance use the same peripherals. In addition, the designer
A device input-output interface does not need to be familiar with the design of the
CPU, you should not know with which specific machine the interface will work. It only needs to understand the
characteristics of the channel, whose necessary specifications can be classified into 3 categories:
a) Logics: definition and grouping of related signals of logical polarity, for example:
address, data, control, synchronization, etc.
b) Electrical and physical: signal levels, types of cables, connectors, etc.
c) Protocol: rules for using the channel, such as timing relationships (timing,
synchronization, recognition, and arbitration.

Logical and physical organization of magnetic storage

Logical organization

Magnetic Storage: data storage on a magnetic medium is carried out

magnetizing the medium in one direction or another. During the reading, each change in magnetic state (transition)
produce a pulse in the reading head, the sense of the transition is irrelevant, what matters are the times
In which transitions occur. The recording technique is known as MFM (modulation in
frecuencia modificada) esta es una mejora del método anterior (MF: modulación en frecuencia) que se
applied to devices of simple density.
In FM, every approximately 4 milliseconds is considered a cell, which encodes a BIT.
The cell limits are given by fixed transitions that serve to synchronize or the controller.
with the read medium (clock). In the middle of each cell, an extra transition indicates 1, and its absence indicates 0.
Las características del medio imponen una restricción al tamaño de la celda y a la densidad de información
recorded. The MFM method is based on suppressing clock transitions. Except between two zeros. Like
As a consequence, the time between transitions is at least equivalent to a full cell. Cells can
then make it half the size of FM and therefore achieve double the recording density.

Sectorization: each track of the disk stores a chain of bits that encodes information. This
coding includes, in addition to user data, additional information that allows synchronization
reading and sectoring the track.
The tracks are divided into a certain number of sectors on which the information is distributed.
user.
The synchronization needed to determine the start of the track is obtained through a mark.
optics called index hole.
A photosensor determines the moment it passes through a specific point, there the reading begins.
track. The beginning of the track contains synchronization bytes and then one after another the sectors that
includes spaces without information or magnetic transitions. Access to a sector is in a certain way
sequential.
An alternative technique that is not used in floppy disks but is used in some hard drives is sectorization.
hard. In addition to the index, sector house includes 2 information records: the identification record and the data record.
The identification record includes a label that indicates which track and which side the sector belongs to.
What is your number and which side does the sector belong to, what is your number and what is the length of the data. The record
The data contains the specifically narrated data, both contain a pair of control bytes (CRC)
it allows to verify if there has been corruption in the information or error in the reading.

Positioning: A sector of a floppy is characterized by 3 parameters: track, side or head, and number of
 The positioning of the reading or recording head is done through a stepper motor, during the
When the machine is powered on, the position of the head is recalibrated, moving the head to track 0, which
determines through an optical or mechanical sensor. When access needs to be made on track N, the head is
advanced or reversed the number of steps needed.

LOGICAL ORGANIZATION OF INFORMATION

The management of a file system relies on a delicate balance: the consistency of the
data that allows access to the information contained in the files.
When that consistency is lost, the information, although present and unaltered, can become
irrecoverable. D.O.S. manages access to a file system in a manner analogous to a manual system of
indexes and page numbering.

System area:

The first area to consider is the partition table, there is one for each logical unit, in the first sector.
of the same; in the first logical unit, it shares the sector with the Master Boot code of the disk. The
The partition table includes a few fundamental data, mainly the position and size of the partition (measured in
cylinders). It only changes during operations such as partitioning or formatting the disk and not during
the normal operation.
In the following cylinder, the partition table begins the boot sector and then the table of
file allocation (FAT). While the number of FATs is customizable, magnetic media includes
uniformly 2; one primary and the other secondary, which should be identical. The function of the copy
secondary is, exclusively that of a safeguard in case a reading error of the table occurs
primary.
Below both FATs is presented the root directory area.

Clusters:

For organizational purposes, each disk is divided into small elements called clusters, each one
of which it covers 1 or more sectors and is considered numbered consecutively starting from the beginning
from the disk file area (that is, following the system area).
It is common to use 2 Kb clusters, 4 sectors of 512 bytes.
A D.O.S. file takes an integer number of clusters (although the last one is only occupying
partially).
It is not required for the clusters of a file to be consecutive; in fact, a file can include clusters
scattered throughout the disk.
Accessing a file involves knowing this sequence of clusters that make it up, and eventually
alter it to elongate or truncate it; the necessary information for this is stored in directories and in the FAT.

Root directory:

It is an area divided into 32-byte entries, each of which corresponds to a file. The number of
entries is a variable (generally 512) and determines the size of the directory, which takes an integer.
from sectors. Each entry is divided into fields that contain the filename, its attributes, date and
last modified time and information about the file location.

Subdirectory: a special class of files are subdirectories. Although D.O.S. does not allow access to them.
In a manner similar to files, he treats them in a similar way.
A subdirectory differs from a regular file by an attribute flag, and its content
structure in entries, as it happens with the root directory.

FAT

It is a map of the disk, divided into clusters. The FAT is an array of as many cells as there are clusters.
they integrate the disk; in each cell a pointer is stored that indicates which clusters follow the corresponding one to the
cell in the sequence.
Note that in no way does the FAT indicate which file a cluster belongs to; it simply does
they encode strings.
the clusters 2033-3854..., in that order. A value of -1 (FFF or FFFF in hexadecimal) indicates the end of the chain
that is, the last cluster of the file.
The storage of the file is then deduced based on the directory entry and by traversing the
encoded sequence in the FAT.
Naturally, not all clusters belong to a file. The free clusters are marked in the FAT.
with a 0.
Unoccupied clusters, but whose use is generally prohibited as they correspond to defective sectors.

Mismatch between the file length (which should occupy 3 clusters) and that of the string
What does the FAT present.

Localization

The information in each directory entry that allows determining which clusters make up the file is
data in the form of pointers. Each entry contains the length (bytes) of the file and the number of the 1st.
clusters of the same.
The rest of the clusters of the file arise from the examination of the FAT.

Organization

The outlined scheme is quite rudimentary: a simple alteration of the FAT can 'confuse' the
operational regarding the location of the files. The organization of D.O.S. is not redundant and if
exposed to inconsistencies.
The best way to understand the inconsistencies in the systems area is through the consideration of
specific errors. D.O.S. does not perform any global recognition (the utility CHKDSK hardly performs
rudimentarily this function), so that even a chaos in the area of systems are "seen" by
D.O.S. as a large number of specific errors or as a set of correct situations that do not
they have consistencies with each other.

Some of the inconsistencies that may arise:

The number of clusters that make up a file is illegal: O (free clusters), FFFF (bad clusters, no
usable), or a number that exceeds the capacity of the logical disk.
Mismatch between the stored file length in the directory entry and the
length of the chain (which is given by the number of threaded clusters until the code is found
of the last clusters or end of file). D.O.S. only detects one of the 2 possibilities: that the string
finished before reaching the total length of the file. If the string is longer than the
corresponding to the declared length, D.O.S. will ignore it.
Crosslink: Nothing in the FAT prevents declaring the same cluster as subsequent to two others.
A global analysis reveals an error). It is enough that 2 cells of the FAT contain the same
Pointer. Thus, the strings from 2 files can converge at a given point into a single string.

Consecuencias:Cuando se escribe el archivo A, también se esta escribiendo el archivo B. La cadena

common is truncated or elongated according to the operation on A or B, indiscriminately. In particular, this is how it is erased.
A, B is truncated, (the common string for both is removed, and subsequently an inconsistency will appear
upon accessing B: the cluster in which the cross-linking occurred will appear as free, when it was expected
that will be part of chain B).

Multiple cross-link: more than 2 files can converge into a single chain.
Circular chains: The crosslink may involve only 1 single .D.O.S file. it will read (or write)
cyclically the file, whose sequence of clusters encoded in the FAT could be, in an example
arbitrary: 2033-3854-2033....
Lost chains, a normal or anomalous chain may not be pointed to by any entry.
directory (that is, not belonging to any file).
Anomalies in the directory entry. The cluster defined in the directory entry as the 1st.
The file may be illegal. Likewise, the file attribute may be incorrect (e.g.: a text file
that appears with the subdirectory attribute).

Loss of consistency: postponing the consideration of possible origins, it is observed that the architecture of
The D.O.S. file system is clearly exposed to a (even a specific) error in the information.
 Paradoxically, in those cases, the 'lost' information continues to remain on the disk... mixed with
tens of thousands of clusters of other pieces of information. What has dissipated is the possibility of
rescue her properly

Processor families
it is the name of the line ofmicroprocessorslow cost [Link] goal was to be able to,
this second brand, penetrate closed markets to thePentiumof higher performance and price.
The first Celeron was launched in August of1998and was based on theIntel Pentium [Link],
new models based on the technologies were releasedIntel Pentium IIIIntel Pentium 4eIntel Core 2 [Link]
the latest is based on the Core 2 Duo (Allendale).
At the moment when the Celeron was introduced, Intel was concerned about the already mentioned loss of market share.
market in the low purchasing power sectors (low-end). To avoid competition, they set aside the
standardizedSocket 7and they replaced it with theSlot [Link] other brands(AMD,Cyrixthey had difficulties
of a technical and legal nature to manufacture compatible microprocessors.
Celeron processors can perform the same basic functions as others, but their performance is
inferior. For example, Celerons usually have less [Link] some functionalities
advanced features disabled. These differences impact the overall performance of the processor variably.
Although many Celerons can work practically at the same level as other processors,
someapplicationsadvancedvideo gamesvideo editing, engineering programs, etc.) maybe not
they function the same on a Celeron.
They are divided into three categories, which are further divided into several subclasses:
P6: Based on the processorsPentium IIyPentium III
Netburst: Based on the processorsPentium 4
Intel Core: Based on the processorsIntel Core 2 Duo

Intel Pentium

It is a range ofmicroprocessorsfifth generation witharchitecturex86produced byIntel

Corporation.
The first Pentium was launched on the market onMarch 22of1993,1with initial speeds of 60 and 66 MHz,
3,100,000 transistors, 8 KiB internal cache for data and 8 KiB for instructions; succeeding the
processorIntel [Link] did not call it 586 because it is not possible to register amarcacomessed up
only fromnumbers.
Pentium was also known by its codename P54C. It was marketed at speeds between 60 and 200.
MHz, with a bus speed of 50, 60, and 66 MHz. The versions that included MMX instructions not only
they provided the user with better management of multimedia applications, such as reading movies
not on DVD but offered at speeds of up to 233 MHz, including a 200 MHz version and the most
basic provided about 166 MHz of clock.
The arrival of this processor took place with an impressive economic movement, putting an end to
the competition, which until then produced equivalent processors, such as the80386the80486and his
variations or evenNPUs.
The following companies were affected by the emergence of the Pentium:
Advanced Micro Devices, better known [Link] had to create his processors from scratch.
This is the K5 and the K6 (These processors were named this way because 'K' stands for Kryptonite, and as
It is known that Kryptonite weakens the superhero from comics and [Link] is as a result of it
What did Intel do to its competitors with the emergence of Pentium?
Cyrix, which produced very good 486, was then acquired byVIA
Harris
LU-MATH
These last two were not very well known although their high-performance processor versions (such as
the Harris 80386) arrived late and unfortunately could not make a place in the market.
Pentium had an architecture capable of executing two operations at the same time thanks to its twopipelinedata
32-bit each, one equivalent to the 486DX(u) and the other equivalent to the 486SX(u). In addition, it had a bus of
64-bit data, allowing 64-bit memory access (although the processor continued to maintain
32-bit compatibility for internal operations and the registers were also 32 bits.

Intel Core is a brand used for various mid-range to high-end consumer products and
businessof microprocessorscarried out byIntel.
In general, Core processors are sold as the more powerful variants of the same processors.
that are marketed as entry-levelCeleronyPentiumSimilarly, the same or
more capable Core processors also sell asXeonprocessors for the server and the market
of workstations.
The current lineup of Core processors includes the latestIntel Core i7, Intel Core i5yIntel Core i3, and the
mayorIntel Core 2 Solo processor , Intel Core 2 Duo , Intel Core 2 Quad yCore 2 Extreme of
The Semprones is a category ofmicroprocessorlow cost witharchitectureX86manufactured [Link]
AMD Sempron replaces the processorrDuronbeing its main competitor the processorCeleronofIntel.
The first versions were released to the market inAugust 2004.
The initial versions of this processor were based on the Thoroughbred/Thornton [Link] XP
with acacheof second level 256KiBand abusfrom 333MHz(FSB 166MHzIts performance index
relative (PR) was situated between 2400+ and 2800+ depending on the model, although the index is not calculated from the
same form as for the Athlon XP, with the Sempron being slightly slower at the same performance index
relatives.
Later, the Sempron was based on the Barton core of the Athlon XP. This version had a rating of
performance relative to 3000+ and had a second level cache of 512 KiB. The versions of Sempron
based on the Athlon XP can be used inmotherboardswith processing socketrSocketA.
En el transcurso de tiempo en que se agotaron las versiones basadas en los
Bartony Thoroughbred/Thorton cores, these were replaced with a variant of the core of theAthlon
64callParis, which does not implement theset of instructions AMD64but yes the controller of
memory, with a 256 KiB level 2 cache. These versions of the Sempron can be used in
motherboards with processor socketSocket 754.
For several years now, all Sempron processors sold come with the set of
instructionsAMD64activated, based on the Palermo core, which incorporates partial support for
SSE3 instructions, and it can come with a second-level cache of 128 or 256 KiB, depending on its
relative benefits, which have a cap in model 3800+ within the new socketAM2.
AMD Athlon
The original Athlon, Athlon Classic, was the first processorx86of seventh
generation and initially maintained its performance leadership over the
microprocessors [Link] continued to use the name Athlon for its
eighth generation processorsAthlon 64.

Phenomenon
it is the name given byAdvanced Micro Devices(AMD) to the first generation ofprocessorsfrom three and
fournucleibased on [Link] name was made known at the end.
ofAprilof the2007thus replacing AMD's high-performance series(Athlon 64 X2). The first two
models of the 8000 series (Phenom X3 8400 at 2.1GHzand the X3 8600 at 2.3 GHz) were launched on the market
inMarchof [Link] microprocessors have three cores (actually four, with one of them
disabled) and AMD claims that they improve performance by up to 30% compared to a microprocessor
dual-core AMD at the same frequency, giving the user a better experience of High
definition(HD) with support for the latest and most demanding formats, includingVC-1MPEG-
2yH.264in aPCof the mass market.
A month before the official launch, AMD was already selling three-core processors based on the
stepping 'B2', which had a failure(bug) when a clock acceleration was performed
(that is, when they were appliedoverclocking)For the design of the Phenom, the included thetechnologyof management
the cache of this stepping "B3", which fixes all the bugs of its prototype version.