Universityof Global Village (UGV), Barishal

Department of Electrical And Electronics Engineering

EEE 0714-3106
Microprocessor &
Interfacing
Course Content

Edited By :
Abdul Hai Utsho
Lecturer
Dept of EEE, UGV
1
 Basic Course Information:

❖ Course Title : Electronics – 1

❖ Course Code: EEE 0714 – 3106
❖ CIE Marks: 90
❖ SEE Marks: 60
❖ Exam Hours: 2 hours (Mid term Examination)
3 hours ( Semester End Examination)
❖ Semester: 3rd Semester
❖ Academic Session: Winter 2025

2
 Assessment Pattern

C: I E – Continuous Internal Evaluation (90 Marks)

Bloom’s Mid Term (45) Assignment (15) Quiz (15) Attendance &
External
Category Marks
(out of 90)

Remember 05 05
Understand 05 05 05
Apply 10 05 15
Analyze 10
Evaluate 10
Create 05 05

3
 Assessment Pattern

S:E E – Semester End Examination (60 Marks)

Bloom’s Final Examination

Category Marks Term (60)
(out of 90)
Remember 15
Understand 10
Apply 10
Analyze 10
Evaluate 10
Create 05

4
 Course Learning Outcome (CLO’s):

CLO1 Explain the architecture, instruction set, memory and input/output

interface for 8086/8088 microprocessor
CLO2 Relate microprocessor working principle, instruction set execution and
peripheral connection for specific applications

CLO3 Program in assembly language for executing microprocessor instructions

set
CLO4 Investigate microprocessor-based systems by designing and conducting
experiments
CLO5 Design a microprocessor-based system that meets specified
requirements

5
Course Rationales:

The course familiarizes the architecture of the 8086 processor, assembling

language programming and interfacing with various modules. The student can also
understand 8051 Microcontroller concepts, architecture, programming, and
application of Microcontrollers. Student able to do any type of VLSI, embedded
systems, industrial and real time applications by knowing the concepts of
Microprocessor and Microcontrollers.

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Course Objectives:

● To develop an in-depth understanding of the operation of microprocessors.

● To master assembly language programming using concepts like assembler directives,
procedures, macros, software interrupts etc.
● To create an exposure to basic peripherals, its programming and interfacing
techniques.
● To understand the concept of Interrupts and interfacing details of 8086.
● To impart the basic concepts of serial communication in 8086.

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Course Contents Summary
Serial Course Contents Hours
No
1 Microprocessor Introduction, Microprocessor based System, 10
Assembly Language, memory basic, 8085 basic, Block
diagram, registers, Demultiplexing, Flag Registers, Flags

2 8086, Pin diagrams, Block Diagram, Pin Working Principle, 12

addressing modes, instruction sets, basic programs

3 Peripherals: Basic of 8255, 8255 block diagram, Bus, modes, 12

control words, basic programs, 8259 basic, Block diagram,
Registers Master slave operation, Control Words, USART,
Synchronous , Asynchronous communication, Serial, Parallel
Communication

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 COURSE PLAN MAPPED WITH CLO
Week Content of Course Teaching-Learning Assessment Corresponding
Strategy Strategy CLOs
1 Introduction to Microprocessors: Basic Lecture, Visual Quiz, Discussion CLO-1
concepts, microprocessor-based systems, Demonstration
history, and applications

2 8085 Microprocessor Overview: Block Lecture, Interactive Problem Solving, CLO-1

diagram, registers, addressing modes Discussion Quiz

3 8085 Instruction Set: Data transfer, Lecture, Assembly Problem Solving, CLO-2
arithmetic, logical, and branching Language Example Assignment
instructions
4 Demultiplexing and Flag Registers: Lecture, Circuit Quiz, Problem CLO-1
Understanding the operation of flag Demonstration Solving
registers and demultiplexing of
address/data bus
5 Basic Programs in 8085: Writing and Practical, Hands-On Lab Report, CLO-2
debugging simple programs using the Lab Assignment
8085-instruction set
6 Introduction to 8086: Block diagram, Lecture, Visual Aids, Quiz, Assignment CLO-1
registers, pin diagram, and working Demonstration
principle

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COURSE PLAN MAPPED WITH CLO
Week Course Content Teaching- Assessment Correspond
Strategy Strategy ing CLOs

7 Addressing Modes and Instruction Set Lecture, Quiz, Problem CLO-2

of 8086: Direct, indirect, register, and Problem Solving
immediate addressing modes Solving
8 8086 Programming: Writing basic Lab Session, Practical Exam, CLO-2
programs using assembly language Practical Quiz
Demonstration
9 Introduction to 8255: Block diagram, Lecture, Circuit
Quiz, Assignment CLO-3
operation, and modes (input/output, Demonstration
bidirectional, handshake)
10 8255 Control Words and Basic Lecture, Hands- Lab Report, CLO-3
Programming: Understanding control On Lab Problem Solving
words and programming 8255 for I/O
operations
11 8259 Interrupt Controller: Basic Lecture, Circuit Quiz, Assignment CLO-3
operation, master-slave configuration, Simulation
and control words
12 USART: Introduction to synchronous and Lecture, Problem Solving, CLO-4
asynchronous communication, serial Practical Written Exam
data transmission Examples 10
COURSE PLAN MAPPED WITH CLO
Week Course Content Teaching- Assessment Correspon
Strategy Strategy ding CLOs

13 Synchronous and Asynchronous Lecture, Quiz, Problem CLO-4

Communication: Working principles Demonstratio Solving
and applications n
14 Serial and Parallel Communication: Lecture, Assignment, CLO-4
Overview of different communication Circuit Quiz
methods and interfaces Simulation

15 Interfacing Microprocessors: Lab Session, Lab Report, CLO-4

Interfacing 8085/8086 with peripherals Practical Problem
(LED, 7-segment display, switches) Circuit Solving
Design
16 Course Review and Integration: Review Group Quiz, Problem CLO-1,
of microprocessor architecture, Problem Solving CLO-2,
programming, and interfacing with Solving, CLO-3,
peripherals Review CLO-4
17 Viva and Presentation: Comprehensive Viva-Voce, Viva, CLO-1,
evaluation through oral exams and Student Presentation CLO-2,
student presentations Presentations CLO-3,
CLO-4 11
References:

- Ramesh S. Goankar, “Microprocessor Architecture,

Programming and Applications with 8085”, 5th Edition,
Prentice Hall

- Bharat Acharya Education - YouTube

12
Week - 1

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 Basic Concepts of Microprocessors

• Differences between:
– Microcomputer – a computer with a
microprocessor as its CPU. Includes memory, I/O
etc.
– Microprocessor – silicon chip which includes
ALU, register circuits & control circuits
– Microcontroller – silicon chip which includes
microprocessor, memory & I/O in a single
package.

14
 What is a Microprocessor?
• The word comes from the combination micro and
processor.
– Processor means a device that processes whatever. In
this context processor means a device that processes
numbers, specifically binary numbers, 0’s and 1’s.
• To process means to manipulate. It is a general term that
describes all manipulation. Again in this content, it means to
perform certain operations on the numbers that depend on the
microprocessor’s design.

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 What about micro?
• Micro is a new addition.
– In the late 1960’s, processors were built using discrete
elements.
• These devices performed the required operation, but were too
large and too slow.

– In the early 1970’s the microchip was invented. All of

the components that made up the processor were now
placed on a single piece of silicon. The size became
several thousand times smaller and the speed became
several hundred times faster. The “Micro”Processor
was born.

16
 Was there ever a “mini”-
processor?
• No.
– It went directly from discrete elements to a
single chip. However, comparing today’s
microprocessors to the ones built in the early
1970’s you find an extreme increase in the
amount of integration.

• So, What is a microprocessor?

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Definition of the Microprocessor

The microprocessor is a programmable device

that takes in numbers, performs on them
arithmetic or logical operations according to
the program stored in memory and then
produces other numbers as a result.

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 Definition (Contd.)
– Takes in: The data that the microprocessor
manipulates must come from somewhere.
• It comes from what is called “input devices”.
• These are devices that bring data into the system
from the outside world.
• These represent devices such as a keyboard, a
mouse, switches, and the like.

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 Definition (Contd.)
– Numbers: The microprocessor has a very narrow view on life. It
only understands binary numbers.

A binary digit is called a bit (which comes from binary digit).

The microprocessor recognizes and processes a group of bits

together. This group of bits is called a “word”.

The number of bits in a Microprocessor’s word, is a measure of its

“abilities”.

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 Definition (Contd.)
– Words, Bytes, etc.
• The earliest microprocessor (the Intel 8088 and Motorola’s
6800) recognized 8-bit words.
– They processed information 8-bits at a time. That’s why they are
called “8-bit processors”. They can handle large numbers, but in
order to process these numbers, they broke them into 8-bit pieces
and processed each group of 8-bits separately.

• Later microprocessors (8086 and 68000) were designed with

16-bit words.
– A group of 8-bits were referred to as a “half-word” or “byte”.
– A group of 4 bits is called a “nibble”.
– Also, 32 bit groups were given the name “long word”.

• Today, all processors manipulate at least 32 bits at a time and

there exists microprocessors that can process 64, 80, 128 bits
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 Definition (Contd.)
– Stored in memory:
• First, what is memory?
– Memory is the location where information is kept while not in
current use.
– Memory is a collection of storage devices. Usually, each storage
device holds one bit. Also, in most kinds of memory, these
storage devices are grouped into groups of 8. These 8 storage
locations can only be accessed together. So, one can only read or
write in terms of bytes to and form memory.
– Memory is usually measured by the number of bytes it can hold.
It is measured in Kilos, Megas and lately Gigas. A Kilo in
computer language is 210 =1024. So, a KB (KiloByte) is 1024
bytes. Mega is 1024 Kilos and Giga is 1024 Mega.

22
 Definition (Contd.)
– Stored in memory:
• When a program is entered into a computer, it is
stored in memory. Then as the microprocessor starts
to execute the instructions, it brings the instructions
from memory one at a time.

• Memory is also used to hold the data.

– The microprocessor reads (brings in) the data from
memory when it needs it and writes (stores) the results
into memory when it is done.

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 A Microprocessor-based system
From the above description, we can draw the
following block diagram to represent a
microprocessor-based system:

Output
Input

Memory

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 Organization of a microprocessor-
based system
• Let’s expand the picture a bit.
I/O
ALU Register Input/ Output
Array
System Bus
Control
Memory
ROM RAM

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 Microprocessor Fifth Generation Pentium

Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology  Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors  40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities
Second Generation
Flexible I/O port addressing
During 1973
NMOS technology  Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors  16 pins nesting
8 and 16 bit processors  40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are 11
multiplexed Intel 8085 (8 bit processor) 26
 Memory
• Memory stores information such as instructions
and data in binary format (0 and 1). It provides
this information to the microprocessor whenever
it is needed.

• Usually, there is a memory “sub-system” in a

microprocessor-based system. This sub-system
includes:
– The registers inside the microprocessor
– Read Only Memory (ROM)
• used to store information that does not change.
– Random Access Memory (RAM) (also known as
Read/Write Memory).
• used to store information supplied by the user. Such as
programs and data.
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 Memory Map and Addresses
• The memory map is a picture representation
of the address range and shows where the
different memory chips are located within
the address range.
0000 EPROM 0000
Address Range of EPROM Chip
3FFF
4400
RAM 1 Address Range of 1st RAM Chip
5FFF
Address Range

RAM 2 6000
Address Range of 2nd RAM Chip
8FFF
RAM 3 9000
Address Range of 3rd RAM Chip
A3FF
RAM 4 A400

Address Range of 4th RAM Chip

F7FF
FFFF

28
 Machine Language
• The number of bits that form the “word” of a
microprocessor is fixed for that particular
processor.
– These bits define a maximum number of combinations.
• For example an 8-bit microprocessor can have at most 28 = 256
different combinations.

• However, in most microprocessors, not all of these

combinations are used.
– Certain patterns are chosen and assigned specific
meanings.
– Each of these patterns forms an instruction for the
microprocessor.
– The complete set of patterns makes up the
microprocessor’s machine language.
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Week - 2

30
 The 8085 Machine Language
• The 8085 (from Intel) is an 8-bit microprocessor.
– The 8085 uses a total of 246 bit patterns to form its
instruction set.
– These 246 patterns represent only 74 instructions.
• The reason for the difference is that some (actually most)
instructions have multiple different formats.

– Because it is very difficult to enter the bit patterns

correctly, they are usually entered in hexadecimal
instead of binary.
• For example, the combination 0011 1100 which translates into
“increment the number in the register called the accumulator”,
is usually entered as 3C.

31
 Assembly Language
• Using the same example from before,
– 00111100 translates to 3C in hexadecimal (OPCODE)
– Its mnemonic is: “INR A”.
– INR stands for “increment register” and A is short for
accumulator.

• Another example is: 1000 0000,

– Which translates to 80 in hexadecimal.
– Its mnemonic is “ADD B”.
– “Add register B to the accumulator and keep the result in the
accumulator”.

32
8085 Microprocessor Architecture

• 8-bit general purpose µp

• Capable of addressing 64 k of memory
• Has 40 pins
• Requires +5 v power supply
• Can operate with 3 MHz clock

33
 Pin diagram
Power
Supply: +5 V
Frequency
Generator is
connected to
those pins

Input/Output/
Memory

Read

Write

Enable
Multiplexed
Address Data
Bus

Address
Bus

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Architecture of Intel 8085 Microprocessor

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• System Bus – wires connecting memory & I/O to
microprocessor
– Address Bus
• Unidirectional
• Identifying peripheral or memory location
– Data Bus
• Bidirectional
• Transferring data
– Control Bus
• Synchronization signals
• Timing signals
• Control signal

36
 The ALU
• In addition to the arithmetic & logic circuits, the
ALU includes the accumulator, which is part of
every arithmetic & logic operation.

• Also, the ALU includes a temporary register used

for holding data temporarily during the execution
of the operation. This temporary register is not
accessible by the programmer.

38
• Registers
– General Purpose Registers
• B, C, D, E, H & L (8 bit registers)
• Can be used singly
• Or can be used as 16 bit register pairs
– BC, DE, HL
• H & L can be used as a data pointer (holds memory
address) Accumulator Flags

– Special Purpose Registers B

D
C
E

• Accumulator (8 bit register) H

Program Counter
L

– Store 8 bit data Stack Pointer

– Store the result of an operation

– Store 8 bit data during I/O transfer Address 16 8 Data

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Week - 3

40
• Flag Register
– 8 bit register – shows the status of the microprocessor before/after an
operation
– S (sign flag), Z (zero flag), AC (auxillary carry flag), P (parity flag) &
CY (carry flag)

D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY

– Sign Flag
• Used for indicating the sign of the data in the accumulator
• The sign flag is set if negative (1 – negative)
• The sign flag is reset if positive (0 –positive)

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• Zero Flag
– Is set if result obtained after an operation is 0
– Is set following an increment or decrement operation of that register
10110011
+ 01001101

1 00000000
• Carry Flag
– Is set if there is a carry or borrow from arithmetic operation

1011 0101 1011 0101

+ 0110 1100 - 1100 1100

Carry 1 0010 0001 Borrow 1 1110 1001

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• Auxillary Carry Flag
– Is set if there is a carry out of bit 3
• Parity Flag
– Is set if parity is even
– Is cleared if parity is odd

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• The Program Counter (PC)
– This is a register that is used to control the sequencing
of the execution of instructions.
– This register always holds the address of the next
instruction.
– Since it holds an address, it must be 16 bits wide.

44
• The Stack pointer
– The stack pointer is also a 16-bit register that is
used to point into memory.
– The memory this register points to is a special
area called the stack.
– The stack is an area of memory used to hold
data that will be retreived soon.
– The stack is usually accessed in a Last In First
Out (LIFO) fashion.

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Week - 4

46
Memory
 Demultiplexing AD7-AD0
8085
A15-A8

ALE

Latch
AD7-AD0 A7- A 0

D7- D0

– Given that ALE operates as a pulse during T1, we will

be able to latch the address. Then when ALE goes low,
the address is saved and the AD7–AD0 lines can be
used for their purpose as the bi-directional data lines.

50
 Demultiplexing AD7-AD0
– From the above description, it becomes obvious
that the AD7– AD0 lines are serving a dual purpose
and that they need to be demultiplexed to get all the
information.
– The high order bits of the address remain on the bus
for three clock periods. However, the low order bits
r ain for only on lo k p riod and t y would
be lost if they are not saved externally. Also, notice
that the low order bits of the address disappear
when they are needed most.
– To make sure we have the entire address for the full
three clock cycles, we will use an external latch
to save the value of AD7– AD0 when it is carrying
the address bits. We use the ALE signal to enable
this latch.
51
 Demultiplexing the Bus AD7 – AD0
• The high order address is placed on the address bus and hold for 3 clk
periods,
• The low order address is lost after the first clk period, this address
needs to be hold however we need to use latch
• The address AD7 – AD0 is connected as inputs to the latch 74LS373.
• The ALE signal is connected to the enable (G) pin of the latch and the
OC – Output control – of the latch is grounded

52
53
 How Does the Microprocessor
Work?
➢ Assume that a program and data are already entered in the
R/W memory.
➢ The microprocessor fetches the first instruction from its
memory sheet, decodes it, and executes that instruction.
➢ The sequence of fetch, decode, and execute is continued
until the microprocessor comes across an instruction to stop.
➢ During the entire process, the microprocessor uses the
system bus to fetch the binary instructions and data from the
memory.
➢ It uses registers from the register section to store data
temporarily, and it performs the computing function in the
ALU section.
➢ Finally, it sends out the result in binary, using the same
bus lines, to memory or an output device. 4
54
 How Does a Microprocessor Differentiate Between Data
and Instruction Code?
The microprocessor interprets the first byte it Mnemonics Hex Memory
Code Address
fetches as an opcode. In the example, we tell the
processor that our program begins at location MVI A, 3E 2000H
2000H. The first code it fetches is 3EH. When it 32H 32 2001H
decodes that code, it knows that it is a two-byte MVI 06 2002H
instruction. Therefore, it assumes that the second B,48H 48 2003H
code, 32H, is a data byte. If we forget to enter 32H
and enter the next code, 06H, instead, the 8085 will ADD B 80 2004H
load 06H in the accumulator, interpret the next
code, 48H, as an opcode, and continue the
execution in sequence. As a consequence, we may
encounter a totally unexpected result.

5
55
Week - 5

56
 PROGRAM
Example: Write a program to perform 16 bit addition of
1234H & 4321H. Store answer at H & L registers.
MVI B, 21H B=21H
MVI A, 34H A=34H
MVI C, 43H C=43H
MVI D, 12H D=12H
ADD B A=34+21H
MOV L, A L=55H
MOV A, C A=43H
ADC D A=43+12H
MOV H, A H=55H
HLT STOP.
57
 PROGRAM
Example:Write a program to exchange contents of
memory location D000H to D001H

LDA D000H Load Acc with data from D000

MOV B, A
Move the data to B
LDA D001H Load Acc with data from D001
STA D000H Store Acc data at D000
MOV A,B
Move B’s data to A
STA D001H Store Acc data at D001

16
58
 PROGRAM
Write a program to reset last 4 bits of the number 32H
Store result at C200H.
MVI A, 32H A=32H
ANI F0H 00110010 AND
1111000
STA C200H C200=30H
RST1 Stop

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 PROGRAM
Write a program to add 10 data bytes. Data is stored from
locations C200H. Store result at C300H.

LXI H,C200H
MVI C, 0AH
MVI A,00H
UP MOV B,M
ADD B
INX H
DCR C
JNZ UP
STA C300H
RST1

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 8086 Features
• 16-bit Arithmetic Logic Unit

• 16-bit data bus

• 20-bit address bus - 220 = 1,048,576 = 1 meg

61
Week - 6

62
Pinouts

63
 8086 Pins
The 8086 comes in a 40 pin package which means that some pins have
more than one use or are multiplexed. The packaging technology of time
limited the number of pin that could be used.

In particular, the address lines 0 - 15 are multiplexed with data lines 0-15,
address lines 16-19 are multiplexed with status lines. These pins are

AD0 - AD15, A16/S3 - A19/S6

The 8086 has one other pin that is multiplexed and this is BHE’/S7.
BHE stands for Bus High Enable. This is an active low signal that is
asserted when there is data on the upper half of the data bus.

The 8086 has two modes of operation that changes the function of some pins.
The SDK-86 uses the 8086 in the minimum mode with the MN/MX’ pin tied to 5
volts. This is a simple single processor mode. To work in maximum mode, the
MN/MX’ pin is tied to ground. This is the mode required for a coprocessor like
the 8087.

64
 8086 Pins
In the minimum mode the following pins are available.
HOLD When this pin is high, another master is requesting control of the
local bus, e.g., a DMA controller.

HLDA HOLD Acknowledge: the 8086 signals that it is going to float

the local bus.

WR’ Write: the processor is performing a write memory or I/O operation.

M/IO’ Memory or I/O operation.

DT/R’ Data Transmit or Receive.

DEN’ Data Enable: data is on the multiplexed address/data pins.

ALE Address Latch Enable: the address is on the address/data pins.

This signal is used to capture the address in latches to establish the
address bus.

INTA’ Interrupt acknowledge: acknowledges external interrupt requests.

65
8086 Block Diagram

66
 8086 Architecture
• The 8086 has two parts, the Bus Interface Unit (BIU) and the
Execution Unit (EU).

• The BIU fetches instructions, reads and writes data, and computes the
20-bit address.

• The EU decodes and executes the instructions using the 16-bit ALU.

• The BIU contains the following registers:

IP - Instruction Pointer
CS - Code Segment Register
DS - Data Segment Register
SS - Stack Segment Register
ES - Extra Segment Register

The BIU fetches instructions using the CS and IP, written CS:IP, to contruct the
20-bit address. Data is fetched using a segment register (usually the DS) and
an effective address (EA) computed by the EU depending on the addressing
mode.

67
 8086 Architecture
The EU contains the following 16-bit registers:

AX – Accumulator
BX - Base Register
CX - Count Register
DX - Data Register
SP - Stack Pointer \ defaults to stack segment
BP - Base Pointer /
SI - Source Index Register
DI - Destination Register

These are referred to as general-purpose registers, although, as seen by

their names, they often have a special-purpose use for some instructions.

The AX, BX, CX, and DX registers can be considers as two 8-bit registers, a
High byte and a Low byte. This allows byte operations and compatibility with
the previous generation of 8-bit processors, the 8080 and 8085. 8085 source
code could be translated in 8086 code and assembled. The 8-bit registers are:

AX --> AH,AL
BX --> BH,BL
CX --> CH,CL
DX --> DH,DL
I-11
68
 Execution Unit (EU)
Auxiliary Carry Flag Carry Flag
Flag Register This flag is set, when there is
This flag is set, when there is a carry
out of low-nibble in case of addition or a carry out of MSB in case of
a borrow in case of subtraction addition or a borrow in case
of subtraction.

Sign Flag Zero Flag Parity Flag

After any operation if the
MSB is 1, then it indicates This flag is set, if the result of This is even parity flag. When
that the number is negative. the computation or comparison result has even number of 1, it
And this flag is set to 1 performed by an instruction is will be set to 1, otherwise 0 for
zero odd number of 1s

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Trap Flag
If this flag is set, the processor
Over flow Flag
enters the single step execution
mode by generating internal
The overflow flag is set to 1 when the result of a signed operation
is too large to fit.
interrupts after the execution of
each instruction

Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.11
towards the lowest address, i.e., auto decrementing mode.

69
8086 Microprocessor Architecture

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
3

70
8086 Microprocessor
Architecture
Bus Interface Unit (BIU)

Dedicated Adder to generate

20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Segment Registers >> 4

71
 Memory Address Calculation
❑Segment addresses must be stored in
segment registers
❑Offset is derived from the combination of
pointer registers, the Instruction Pointer Segment address 0000

(IP), and immediate values + Offset

Memory address

❑ Examples

CS 3 4 8 A 0 SS 5 0 0 0 0
IP + 4 2 1 4 SP + F F E 0
Instruction address 3 8 A B 4 Stack address 5 F F E 0

DS 1 2 3 4 0
DI + 0 0 2 2
Data address 1 2 3 6 2

72
8086 Microprocessor
Architecture
Bus Interface Unit (BIU)

Segment
Registers

8086’s 1-megabyte The 8086 can directly Programs obtain access

memory is divided address four segments to code and data in the
into segments of up (256 K bytes within the 1 segments by changing
to 64K bytes each. M byte of memory) at a the segment register
particular time. content to point to the
desired segments.

73
8086 Microprocessor
Architecture
Bus Interface Unit (BIU)

Segment Code Segment Register

Registers
16-bit

CS contains the base or start of the current code segment;

IP contains the distance or offset from this address to the
next instruction byte to be fetched.

BIU computes the 20-bit physical address by logically

shifting the contents of CS 4-bits to the left and then
adding the 16-bit contents of IP.

That is, all instructions of a program are relative to the

contents of the CS register multiplied by 16 and then offset
is added provided by the IP.

74
 Architecture
8086 Microprocessor
Bus Interface Unit (BIU)

Segment Data Segment Register

Registers
16-bit

Points to the current data segment; operands for most

instructions are fetched from this segment.

The 16-bit contents of the Source Index (SI) or

Destination Index (DI) or a 16-bit displacement are used
as offset for computing the 20-bit physical address.

75
Week - 7

76
8086 Microprocessor
Architecture
Bus Interface Unit (BIU)

Segment Stack Segment Register

Registers 16-bit
Points to the current stack.
The 20-bit physical stack address is
calculated from the Stack Segment (SS)
and the Stack Pointer (SP) for stack
instructions such as PUSH and POP.
In based addressing mode, the 20-bit
physical stack address is calculated from the
Stack segment (SS) and the Base Pointer
(BP).

77
8086 Microprocessor
Architecture
Bus Interface Unit (BIU)

Segment Extra Segment Register

Registers
16-bit

Points to the extra segment in which data (in excess of

64K pointed to by the DS) is stored.

String instructions use the ES and DI to determine the 20-

bit physical address for the destination.

78
 Architecture
8086 Microprocessor
Bus Interface Unit (BIU)

Segment Instruction Pointer

Registers
16-bit
Always points to the next instruction to be
executed within the currently executing code
segment.
So, this register contains the 16-bit offset
address pointing to the next instruction code
within the 64Kb of the code segment area.
Its content is automatically incremented as
the execution of the next instruction takes
place.
79
8086 Microprocessor
Architecture
Bus Interface Unit (BIU)

Instruction queue

A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched from
the memory ahead of
time.

This is done in order to

speed up the execution by
overlapping instruction
fetch with execution.

This mechanism is known

as pipelining.

80
 8086 Microprocessor
Architecture Execution Unit (EU)

EU decodes and
executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 8
DX can be used as DH and DL
81
8086 Microprocessor
Architecture
Execution Unit (EU)

EU Accumulator Register (AX)

Registers
Consists of two 8-bit registers AL and AH,
which can be combined together and used as
a 16-bit register AX.
AL in this case contains the low order byte
of the word, and AH contains the high-order
byte.
The I/O instructions use the
AX or AL for inputting /
outputting 16 or 8 bit data to or from an I/O
port.
9
Multiplication and Division instructions
82
also use the AX or AL.
8086 Microprocessor
Architecture
Execution Unit (EU)

EU Base Register (BX)

Registers
Consists of two 8-bit registers BL and BH,
which can be combined together and used as
a 16-bit register BX.
BL in this case contains the low-order byte
of the word, and BH contains the high-order
byte.
This is the only general purpose register
whose contents can be used for addressing
the 8086 memory.
All memory references utilizing this 10
register content for addressing use DS as the
83
Week - 8

84
 Addressing
8086 Microprocessor
Modes
Every instruction of a program has to operate on a data.
The different ways in which a source operand is denoted
in an instruction are known as addressing modes.

1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing memory data
7. Based Index Addressing

8. String Addressing

9. Direct I/O port Addressing

Group III : Addressing modes for
10. Indirect I/O port Addressing I/O ports

11. Relative Addressing Group IV : Relative Addressing mode

12. Implied Addressing Group V : Implied Addressing m1o

5 de

85
8086 Microprocessor Group I : Addressing modes for
Addressing Modes register and immediate data

1. Register Addressing The instruction will specify the name of the

register which holds the data to be operated by
2. Immediate Addressing the instruction.

3. Direct Addressing Example:

4. Register Indirect Addressing
MOV CL, DH
5. Based Addressing
The content of 8-bit register DH is moved to
6. Indexed Addressing another 8-bit register CL

7. Based Index Addressing (CL) → (DH)

8. String Addressing

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

16
8086 Microprocessor Group I : Addressing modes for
Addressing Modes register and immediate data

1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL

7. Based Index Addressing (DL) → 08H

8. String Addressing
MOV AX, 0A9FH
9. Direct I/O port Addressing
The 16-bit data (0A9FH) given in the instruction is
10. Indirect I/O port Addressing moved to AX register
11. Relative Addressing
(AX) → 0A9FH
12. Implied Addressing

17
 Addressing
8086 Microprocessor Group II : Addressing modes
Modes for memory data

1. Register Addressing

2. Immediate Addressing
Here, the effective address of the memory
3. Direct Addressing
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.

5. Based Addressing The effective address is just a 16-bit number

written directly in the instruction.
6. Indexed Addressing
Example:
7. Based Index Addressing
MOV BX, [1354H] Use Bx only
8. String Addressing MOV BL, [0400H]

9. Direct I/O port Addressing The square brackets around the 1354H denotes
the contents of the memory location. When
10. Indirect I/O port Addressing
executed, this instruction will copy the contents of
11. Relative Addressing the memory location into BX register.

12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.

18
8086 Microprocessor
Addressing
Group II : Addressing modes

Modes for memory data

1. Register Addressing In Register indirect addressing, name of the

register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.

3. Direct Addressing Registers used to hold EA are any of the following

registers:
4. Register Indirect Addressing
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for base
6. Indexed Addressing
address calculation.
7. Based Index Addressing
Example:
Note : Register/ memory
8. String Addressing enclosed in brackets refer
MOV CX, [BX]
to content of register/
9. Direct I/O port Addressing memory
Operations:
10. Indirect I/O port Addressing
EA = (BX)
11. Relative Addressing BA = (DS) x 1610
Used as offset of the DS
MA = BA + EA
12. Implied Addressing
(CX) → (MA) or,

(CL) → (MA)
(CH) → (MA +1)

19
Week - 9

90
8086 Microprocessor

Instruction Set
8086 supports 6 types of instructions.

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Logical Instructions

4. String Manipulation Instructions

5. Process Control Instructions

6. Control Transfer Instructions

91
8086 Microprocessor
Instruction Set
1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

MOV reg2/ mem, reg1/ mem

MOV reg2, reg1 (reg2) → (reg1)

MOV mem, reg1 (mem) → (reg1)
MOV reg2, mem (reg2) → (mem)

MOV reg, data (reg) → data

MOV mem, data (mem) → data

XCHG reg2/ mem, reg1

XCHG reg2, reg1 (reg2) x (reg1)

XCHG mem, reg1 (mem) x (reg1)

10

92
8086 Microprocessor Instruction Set
1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

IN A, [DX] OUT [DX], A

IN AL, [DX] PORTaddr = (DX) OUT [DX], AL PORTaddr = (DX)

(AL) → (PORT) (PORT) → (AL)

IN AX, [DX] PORTaddr = (DX) OUT [DX], AX PORTaddr = (DX)

(AX) → (PORT) (PORT) → (AX)

IN A, addr8 OUT addr8, A

IN AL, addr8 (AL) → (addr8) OUT addr8, AL (addr8) → (AL)

IN AX, addr8 (AX) → (addr8) OUT addr8, AX (addr8) → (AX)

12
8086 Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADD reg2/ mem, reg1/mem

ADD reg2, reg1 (reg2) → (reg1) + (reg2)

ADD reg2, mem (reg2) → (reg2) + (mem)
ADD mem, reg1 (mem) → (mem)+(reg1)

ADD reg, data (reg) → (reg)+ data

ADD mem, data (mem) → (mem)+data

ADD A, data

ADD AL, data8 (AL) → (AL) + data8

ADD AX, data16 (AX) → (AX) +data16

13
8086 Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADC reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2) → (reg1) + (reg2)+CF

ADC reg2, mem (reg2) → (reg2) + (mem)+CF
ADC mem, reg1 (mem) → (mem)+(reg1)+CF

ADC reg/mem, data

ADC reg, data (reg) → (reg)+ data+CF

ADC mem, data (mem) → (mem)+data+CF

ADDC A, data

ADD AL, data8 (AL) → (AL) + data8+CF

ADD AX, data16 (AX) → (AX) +data16+CF

14
8086 Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SUB reg2/ mem, reg1/mem

SUB reg2, reg1 (reg2) → (reg1) - (reg2)

SUB reg2, mem (reg2) → (reg2) - (mem)
SUB mem, reg1 (mem) → (mem) - (reg1)

SUB reg, data (reg) → (reg) - data

SUB mem, data (mem) → (mem) - data

SUB A, data

SUB AL, data8 (AL) → (AL) - data8

SUB AX, data16 (AX) → (AX) - data16

15
8086 Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SBB reg2/ mem, reg1/mem

SBB reg2, reg1 (reg2) → (reg1) - (reg2) - CF

SBB reg2, mem (reg2) → (reg2) - (mem)- CF
SBB mem, reg1 (mem) → (mem) - (reg1) –CF

SBB reg/mem, data

SBB reg, data (reg) → (reg) – data - CF

SBB mem, data (mem) → (mem) - data - CF

SBB A, data

SBB AL, data8 (AL) → (AL) - data8 - CF

SBB AX, data16 (AX) → (AX) - data16 - CF

16
8086 Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

INC reg/ mem

INC reg8 (reg8) → (reg8) + 1

INC reg16 (reg16) → (reg16) + 1

INC mem (mem) → (mem) + 1

DEC reg/ mem

DEC reg8 (reg8) → (reg8) - 1

DEC reg16 (reg16) → (reg16) - 1

DEC mem (mem) → (mem) - 1

17
8086 Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
Doesn't change the value of the register. result is not stored anywhere
CMP reg2/mem, reg1/ mem

CMP reg2, reg1 Modify flags → (reg2) – (reg1)

MOV AL, 5 If (reg2) > (reg1) then CF=0, ZF=0, SF=0

MOV BL, 5 If (reg2) < (reg1) then CF=1, ZF=0, SF=1
CMP AL, BL ; AL = 5, ZF = 1 (so equal!) If (reg2) = (reg1) then CF=0, ZF=1, SF=0

CMP reg2, mem Modify flags → (reg2) – (mem)

If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0

CMP mem, reg1 Modify flags → (mem) – (reg1)

If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0

21
8086 Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg/mem, data

CMP reg, data Modify flags → (reg) – (data)

If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0

CMP mem, data Modify flags → (mem) – (mem)

If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0

22
8086 Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP A, data

CMP AL, data8 Modify flags → (AL) – data8

If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0

CMP AX, data16 Modify flags → (AX) – data16

If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0

23
Week - 10

102
8086 Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, ROL …

24
8086 Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, ROL …

25
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, ROL …

26
 Basic Interfacing Concept

• Any application of Microprocessor Based system

Requires the transfer of data between external
circuitry to the Microprocessor and Microprocessor to
the External circuitry. User can give information (i.e.
input) to the Microprocessor using keyboard and user
can see the result or output information from the
Microprocessor with the help of display.

• Hence interfacing is used to exchange information

between two different applications/devices.
106
 Memory Mapped I/O

• Device address is of 16 Bit. means A0 to A15 lines are

used to generate device address.
• MEMR and MEMW control signals are used to control
read and write I/O operations.
• Data transfer is between Any register and I/O device.
• Maximum number of I/O devices are 65536.
• Decoding 16 bit address may requires more hardware.
• For e.g. MOV R M, ADD M,CMP M etc.

107
 INTERFACING IN MEMORY
MAPPED I/O
A15
A14 D0 D0
A13 D7 D7 PA0
A12 A0 A0 PA7
A11 A1 A1
A10 PB0
MEMR RD
A9
MEMW WR PB7
A8
A7 RESET OUT RESET
A6 PC0

A5
A4
8255 PC7

A3 CS
A2
108
 8255 PPI
• The INTEL 8255 is a 40 pin IC having total 24 I/O
pins. consisting of 3 numbers of 8 –bit parallel I/O
ports (i.e. PORT A, PORT B,PORT C). The ports can
be programmed to function either as a input port or
as a output port in different operating modes. It
requires 4 internal addresses and has one logic LOW
chip select pin. Its main functions are to interface
peripheral devices to the microprocessor. Basically
used for parallel data transfer. operates in mainly
two modes.
• (1) Bit Set Reset Mode (BSR Mode).
• (2) I/O Mode.
109
Week - 11

110
 Block Diagram of 8255 PPI
POWER +5V PA
SUPPLIES Ground GROUP A
GROUP A
PORT A (8)
CONTROL PA7-PA0
Bidirectional
Data Bus
D7- D0 GROUP A PCU
DATA BUS
BUFFER PORT C
8 Bit UPPER (4) PC7-PC4
Internal
Data Bus
GROUP B PCL
PORT C
LOWER (4) PC3-PC0
READ/
RD
WR WRITE
GROUP B PB
A0 CONTROL GROUP B
A1
LOGIC CONTROL
RESET PORT B (8)
PB7-PB0
cs 111
 Function of Blocks
BLOCK FUNCTION OF BLOCK

It is used to interface the internal data bus of 8255 to the

Data Bus Buffer system data bus by reading and writing operations.
It accepts the input from the address bus and issues
Read/write commands to the individual group blocks. also issues
Control logic appropriate enabling signals to access the required
data/control words/status words.
It can be programmed in three modes Mode0, Mode1 and
Port A Mode2.

It can be programmed in three modes Mode0 and Mode1.

Port B

It can be programmed for Bit Set/reset operation.

Port C
112
 Pin Diagram of 8255 PPI

8255 Pin
Diagram

113
 Function of Pins
PIN FUNCTION OF PIN

These are bidirectional, tri-state data bus lines are connected to the
system data bus. They are used to transfer data and control word
D0-D7 (Data Bus) from microprocessor (8085) to 8255 or receive data or status word
from 8255 to the 8085.

These are 8 Bit bidirectional I/O pins used to send data to output
device and to receive data from input device. It functions as an 8 Bit
PA0-PA7 (Port A) data output latch/buffer when used in output mode and as an 8 Bit
data input latch/buffer when used in input mode.

These are 8 Bit bidirectional I/O pins used to send data to output
device and to receive data from input device. It functions as an 8 Bit
PB0-PB7 (Port B) data output latch/buffer when used in output mode and as an 8 Bit
data input latch/buffer when used in input mode.

114
 Function of Pins
PIN FUNCTION OF PIN

These are 8 bit bidirectional I/O pins divided into two groups PCL
(PC3-PC) and PCU (PC7-PC4).these groups can individually transfer
PC0-PC7 data in or out when programmed for simple I/O, and used as
(Port C) handshake signals when programmed for handshake or
bidirectional modes.

When this pin is low, the CPU can read data in the ports or the
RD status word through the data bus buffer.
When this pin is low, the CPU can write data on the ports or in the
WR control register through the data bus buffer.

This pin can be enabled for data transfer operation between the CPU
CS and 8255.

This pin is used to reset 8255.i.e control register gets cleared and
RESET all the ports are set to the input mode.
115
 Operating Modes Of 8255
• There are two main operational modes of 8255:
(1) Input/output mode,
(2) Bit set/reset mode (BSR Mode).

I/O mode again classified into three types

• (1) Mode 0,
• (2) Mode 1,
• (3) Mode 2.

116
 MODE 0
• In this mode, the ports can be used for simple input/output
operations without handshaking.
• If both port A and B are initialized in mode 0, the two halves
of port C can be either used together as an additional 8-bit
port, or they can be used as individual 4-bit ports.
• Since the two halves of port C are independent, they may be
used such that one-half is initialized as an input port while the
other half is initialized as an output port.

The mode 0 has following features:

• O/p are latched.

• I/p are buffered not latched.
• Port do not have handshake or interrupt capability.
117
 MODE 1
• When we wish to use port A or port B for handshake
(strobed) input or output operation, we initialize that port in
mode 1.
• For port B in this mode (irrespective of whether is acting as
an input port or output port), PC0, PC1 and PC2 pins function
as handshake lines.

The mode 1 has following features:

• Two ports i.e. port A and B can be use as 8-bit i/o port.
• Each port uses three lines of port c as handshake signal and
remaining two signals can be function as i/o port.
• Interrupt logic is supported.
• Input and Output data are latched.
118
 MODE 2
• Only group A can be initialized in this mode.
• Port A can be used for bidirectional handshake data
transfer. This means that data can be input or output on
the same eight lines (PA0 - PA7).
• Pins PC3 - PC7 are used as handshake lines for port A.
• The remaining pins of port C (PC0 - PC2) can be used as
input/output lines if group B is initialized in mode 0.
• In this mode, the 8255 may be used to extend the
system bus to a slave microprocessor.

119
Week - 12

120
Control Word Format in I/O Mode
0 D6 D5 D4 D3 D2 D1 D0 GROUP B
PORT C (LOWER)
1=I/P, 0=O/P
PORT B
1=I/P, 0=O/P
MODE SELECTION
0 = MODE 0
1 = MODE 1

GROUP A
PORT C (UPPER)
1=I/P, 0=O/P
PORT A
1=I/P, 0=O/P
MODE SELECTION
00 = MODE 0
MODE SET FLAG 01 = MODE 1
1 = ACTIVE 1X = MODE 2
121
Control Word Format in BSR Mode
0 D6 D5 D4 D3 D2 D1 D0
BIT SET/RESET
1 = SET
2 = RESET
DON’T CARE

BIT SELECT

0 1 2 3 4 5 6 7
0 1 0 1 0 1 0 1 B0
0 0 1 1 0 0 1 1 B1
0 0 0 0 1 1 1 1 B2

BIT SET/RESET FLAG

0 = ACTIVE
122
Write a program to initialize 8255 in the configuration
below.(assume address of the CW register as 83H).
(1) Port A: simple input (2) Port B: simple output
(3) Port CL: output (4)Port CU: input

• Solution:
1 0 0 1 1 0 0 0
= 98H
Program:
MVI A,98H ; LOAD CONTROL WORD

OUT 83H ; SEND CONTROL WORD

123
 Write a program to initialize 8255 in the configuration
below.(assume address of the CW register as 23H).
(1) Port A: output with handshake
(2) Port B: input with handshake
(3) Port CL: output (4)Port CU: input

• Solution:
1 0 1 0 1 1 1 0
= AEH
Program:
MVI A,AEH ; LOAD CONTROL WORD

OUT 23H ; SEND CONTROL WORD

124
 Find the control word for the register arrangement
of the ports of intel 8255 for mode 0 operation.
• Port A: Output, Port B: Output,
• Port CU: Output, Port CL: Output

Solution:

1 0 0 0 0 0 0 0
= 80H

The control word register for the above ports of intel

8255 is 80H.
125
 Find the control word for the register arrangement
of the ports of intel 8255 for mode 0 operation.
• Port A: Input, Port B: Input,
• Port CU: Input, Port CL: Input

Solution:

1 0 0 1 1 0 1 1
= 9BH

The control word register for the above ports of intel

8255 is 9BH.
126
Week - 13

127
8259 Programmable Interrupt Controller (PIC)
1. This IC is designed to simplify the implementation of the interrupt interface in the 8088
and 8086 based microcomputer systems.
2. This device is known as a ‘Programmable Interrupt Controller’ or PIC.
3. It is manufactured using the NMOS technology and It is available in 28-pin DIP.
4. The operation of the PIC is programmable under software control (Programmable)and it
can be configured for a wide variety of applications.
5. 8259A is treated as peripheral in a microcomputer system.
6. 8259A PIC adds eight vectored priority encoded interrupts to the microprocessor.
7. This controller can be expanded without additional hardware to accept up to 64
interrupt request inputs. This expansion required a master 8259A and eight 8259A
slaves.

8. Some of its programmable features are:

· The ability to accept level-triggered or edge-triggered inputs.
· The ability to be easily cascaded to expand from 8 to 64 interrupt-inputs.
· Its ability to be configured to implement a wide variety of priority schemes.1293
ASSINGMENT OF SIGNALS FOR 8259:
1. D7- D0 is connected to microprocessor data bus D7-D0 (AD7-AD0).
2. IR7- IR0, Interrupt Request inputs are used to request an interrupt and to connect to a slave
in a system with multiple 8259As.
3. WR - the write input connects to write strobe signal of microprocessor.
4. RD - the read input connects to the IORC signal.
5. INT - the interrupt output connects to the INTR pin on the microprocessor from the master,
and is connected to a master IR pin on a slave.
6. INTA - the interrupt acknowledge is an input that connects to the INTA signal on the system.
In a system with a master and slaves, only the master INTA signal is connected.
7. A0 - this address input selects different command words within the 8259A.
8. CS - chip select enables the 8259A for programming and control.
9. SP/EN - Slave Program/Enable Buffer is a dual-function pin.

❖ When the 8259A is in buffered mode, this pin is an output that controls the data bus
transceivers in a large microprocessor-based system.
❖ When the 8259A is not in buffered mode, this pin programs the device as a master
(1) or a slave (0).
❖ CAS2-CAS0, the cascade lines are used as outputs from the master to the slaves for
cascading multiple 8259As in a system. 1304
8259A PIC- PIN DIGRAM

8
2
5
9
8259A PIC- BLOCK DIAGRAM
Week - 14

134
 Slave 8259A
Interrupt controller

External e device 00
IR0
……..…

……..…
INT

External e device 07 IR7

Microprocessor

Master 8259A
Interrupt controller
INTR
…………………

IR0

……..…
INT INT

IR7

Slave 8259A
Interrupt controller

External e device 53 IR0

……..…

……..…

INT

External e device 64 IR7

CONNECTING MULTIPLE (64) INTERRUPTED I/O DEVICES TO

145
18
PROCESSOR
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148
 Programming the 8259A: -
The 82C59A accepts two types of command words generated by the
CPU:
1. Initialization Command Words (ICWs):
Before normal operation can begin, each 82C59A in the
system must be brought to a starting point - by a sequence of 2 to
4 bytes timed by WR pulses.
2. Operational Command Words (OCWs):
These are the command words which command the 82C59A
to operate in various interrupt modes. Among these modes are:
a. Fully nested mode.
b. Rotating priority mode.
c. Special mask mode.
d. Polled mode.
The OCWs can be written into the 82C59A anytime after
initialization.
Initialization Command Words: -
There are four Initialization
Command Words for the 8259A that are
selected with the help of logic level of A0
pin.
When the 8259A is first powered
up, it must be sent ICW1, ICW2 and ICW4.
If the 8259A is programmed in
cascade mode by ICW1, then we also
must program ICW3.
So, if a single 8259A is used in a
system ICW1, ICW2 and ICW4 must be
programmed.
If cascade mode is used in a
system, then all four ICWs must be
programmed.
BASICS OF SERIAL COMMUNICATION
& USART

153
AGENDA
 Data Transmission Types
 Parallel VS Serial
 Synchronous VS Asynchronous
 USART
 WHY DO WE NEED FAST INTERFACES?

- Microcontrollers need fast ways of communication to the outside

world for:

1 Communicating with other microcontrollers, DSPs or even FPGAs.

(ex. SRIO, PCIe, I2C)

2 Capturing input from user and displaying outputs.

3 Communicating with other microcontrollers on different boards for
applications with network of microcontrollers. (ex. CAN and LIN)
 Communicating with other microcontrollers on different boards for
applications with network of microcontrollers.
 Communicating with other microcontrollers, DSPs or even FPGAs.
(ex. SRIO)
DATA TRANSMISSION TYPES
1. Simplex:
- Communication is possible in one direction only. [Link]

TX RX

2. Half duplex:
- Communication is possible in both directions,
but only one TX and one RX at a time. Ex. Police radio.

TX/RX TX/RX
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159
 DATA TRANSMISSION TYPES

3. Full duplex:
- Communication is possible in both directions,
both sides can transmit and receive in the same time.

TX/RX TX/RX
 PARALLEL COMMUNICATION
 The process of sending several bits as a
whole, on a link with several parallel
channels.

 It requires a separate channel for each bit to

be transmitted

 A parallel link use simpler hardware as

there is no need for a serializer/deserializer.

 Usually used for very short distances.

 PARALLEL COMMUNICATION
❖ Problems of parallel communication:
1. Clock skew:
-The clock signal (sent from the clock circuit) arrives at different components
(at different times).

-This happens because of wire-interconnect length, capacitive coupling,

material imperfections …etc. It reduces the speed of every link to the slowest of
all of the links.
 PARALLEL COMMUNICATION
2. Crosstalk:
- Crosstalk happens If the transmitted signal is badly affected by another
nearby signal, when electromagnetic energy from one cable leaves an
imprint on adjacent cables.
 PARALLEL COMMUNICATION
- In parallel communication,
it can refer to electromagnetic interference from one unshielded
pair to another pair, normally running in parallel.

- This issue places an upper limit on the length of a parallel data

connection that is usually shorter than a serial connection.
 PARALLEL COMMUNICATION
❖ Features of parallel communication:
1. Very simple.
2. Crosstalk places an upper limit on the length of a parallel data
connection (usually shorter than a serial connection).

3. Clock skew between different channels.

4. Low data rate compared to a serial connection for long
distances. (Due to the last two reasons).

5. Has a cable cost higher than a serial connection.

 SERIAL COMMUNICATION
 The process of sending data bit by bit
sequentially, over a single channel between
sender and receiver.

 For correct data transmission, there has to

be some form of synchronization between
transmitter and receiver.

 Cost of cable and synchronization difficulties

make parallel communication impractical.
 SERIAL COMMUNICATION
4. Serial links can be clocked considerably faster than parallel
links, and achieve a higher data rate.

5. Used for all long-haul communication and most computer

networks
 COMPARISON
Parallel Serial
Crosstalk Limits the cable length Not a problem because of using
fewer conductors.

Clock skew Slowing up the data rate Not an issue for asynchronous
communication

Length of the Short Long

used cable

Cost High Low

Simplicity Simple Needs a serializer/ deserializer

 BASICS OF SERIAL COMMUNICATION
❖ The basic idea of serial communication:
- To convert parallel data from a computer bus to serial bits, or to receive serial
data we need to use two kinds of shift registers:

1. Transmitter:
- A parallel-in, serial-out
shift register

2. Receiver:
- A serial-in, parallel-out
shift register.

- For each clock pulse,

the data is shifted in or out.
BASICS OF SERIAL COMMUNICATION
- The sender and receiver must agree on a set of rules
(Protocol) on :
1. When data transmission begins and ends.
2. The used bit rate and data packaging format.

- If there is no reference for the receiver to know when

transmission begins or the used bit rate,
→ it’ll sample the wrong values and data will be lost.
Week - 17

171
 SYNCHRONOUS VS ASYNCHRONOUS
1. Synchronous transmission:
Rx
Tx
Rx Tx
Clk

1. Asynchronous transmission:
Rx
Tx
Rx Tx
 SYNCHRONOUS VS ASYNCHRONOUS
- In synchronous transmission, a separate link is dedicated for the
clock from one terminal (Master) to another (Slave).

- In asynchronous transmission, no link for the clock.

Synchronization is done → using a fixed baud rate and using start
and stop bits.
HOW SYNCHRONIZATION IS DONE?
❖ For asynchronous transmission:
- Synchronization is done every word
→ A start bit with the value 0 indicate the beginning of each word, then eight
data bits are sent bit by bit, and finally a stop bit with the value 1 to indicate
the end of the word.

- Both the transmitter and receiver use the same baud rate.

- When the transmitter pauses because it does not have data to transmit (idle
state), it keeps a sequence of stop bits (logic high) in its output.
 Over speed clock (x16 baud rate)
Universal Synchronous
Asynchronous Receiver
Transmitter
(USART)
 USART

- The USART module is a full duplex, serial I/O communication peripheral.

- It contains all shift registers, clock generators and data buffers needed for
serial communication.

- It can work in synchronous mode, or in asynchronous mode.

- The USART uses two I/O pins to transmit and receive serial data. Both
transmission and reception can occur at the same time i.e. ‘full duplex’
operation.
 USART
- To send a byte, the application writes the byte to the transmit buffer.
- The UART then sends the data, bit by bit in the requested format,
adding Stop, Start, and parity bits as needed.

- In a similar way, the UART stores received bytes in a buffer.

- Then the UART can generate an interrupt to notify the application or
software can poll the port to find out if data has arrived.
USART
❖ Asynchronous Mode:
Data transfer happens in the following way:
1. In idle state, data line has logic high (1).
2. Data transfer starts with a start bit, which is always a zero.
3. Data word is transferred (8 or 9 bit), LSB is sent first.
4. Each word ends with a stop bit, which is always high (1).
5. Another byte can be sent directly after, and will start also with a
start bit befor data.
TRANSMITTER
1. The module is enabled by setting the TXEN bit.

2. Data to be sent should be written into the TXREG register. When using 9-
bit, TX9D must be written before writing TXREG.

3. Byte will be immediately transferred to the shift register TSR after the STOP
bit from the pervious load is sent.

4. From there, data will be clocked out onto the TX pin preceded by a START
bit and followed by a STOP bit.
RECEIVER
1. The clock of the receiver is a multiple of the bit rate, in PIC 16f877A,it’s x16
or x64.
So, each bit is transmitted/received in 16 clock cycle.

2. If the receiver detects a start bit for a period= bit period (16 clock cycles),
then it waits for the period of half bit, and then sample the value on the RX
pin and shift it in the receiving shift register.
RECEIVER
3. Every received bit is sampled at the middle of the bit’s time period.
4. The USART can be configured to receive eight or nine bits by the RX9 bit
in the RCSTA register.
5. After the detection of a START bit, eight or nine bits of serial data are
shifted from the RX pin into the Receive Shift Register, one bit at a time.
6. After the last bit has been shifted in, the STOP bit is checked and the data
is moved into the FIFO buffer.