Instruction Execution in Computer Architecture (For MCA Students)
1. What is an Instruction?
An instruction is a binary command given to the CPU to perform a specific operation.
It consists of:
• Opcode (Operation Code) → tells CPU what to do (e.g., ADD, MOV, SUB).
• Operands → data or memory addresses on which operation is performed.
Example (in assembly):
ADD R1, R2
Meaning: Add contents of Register R2 to Register R1.
2. Phases of Instruction Execution
The CPU executes every instruction in a cycle. This cycle is called the Instruction
Cycle.
It consists of the following stages:
(a) Fetch Cycle
• CPU fetches the instruction from memory (RAM) using the Program Counter
(PC).
• PC holds the address of the next instruction.
• Instruction is placed in the Instruction Register (IR).
• PC is incremented to point to the next instruction.
(b) Decode Cycle
• The Control Unit (CU) decodes the instruction in IR.
• It identifies the operation (opcode) and operands.
• Prepares signals for execution.
(c) Operand Fetch
• If the instruction needs data (operands), the CPU fetches it:
o From registers (fastest)
o From cache
o From main memory
(d) Execution Cycle
• The Arithmetic Logic Unit (ALU) or relevant execution unit performs the
operation.
• Example: ADD, SUB, LOAD, STORE, SHIFT, etc.
(e) Result Storage
• The result is stored back:
o In a register (temporary storage), or
o In memory (permanent storage).
(f) Next Instruction
• CPU checks if there is another instruction (via PC).
• Process repeats until a HALT instruction is encountered.
3. Instruction Cycle Diagram
+------------------+
| Fetch |
+------------------+
+------------------+
| Decode |
+------------------+
+------------------+
| Operand Fetch |
+------------------+
+------------------+
| Execute |
+------------------+
+------------------+
| Store Result |
+------------------+
(Next Instruction / HALT)
4. Types of Instruction Execution
Depending on CPU design, instructions may be executed differently:
• Single-cycle Execution → One instruction per cycle (simple, older CPUs).
• Multi-cycle Execution → Instruction broken into multiple steps (common).
• Pipelined Execution → Multiple instructions overlapped (modern CPUs).
• Superscalar Execution → Multiple instructions executed in parallel.
5. Example: ADD Instruction Execution
Instruction: ADD R1, R2
Steps:
1. Fetch → CPU fetches opcode for ADD.
2. Decode → CU understands it is ADD with R1, R2.
3. Operand Fetch → Get values of R1 and R2.
4. Execute → ALU performs R1 + R2.
5. Store → Result stored in R1.
Instruction Fetch and Execution in Computer Architecture
A computer executes instructions using the Instruction Cycle, which consists of
several phases.
The main steps are:
1. Instruction Fetch
2. Instruction Decode
3. Operand Fetch (if required)
4. Instruction Execution
5. Result Write-back
6. Next Instruction (PC update)
1. Instruction Fetch (IF)
• Goal: Bring the next instruction from memory into the CPU.
• Steps:
1. Program Counter (PC) holds the address of the next instruction.
2. The Memory Address Register (MAR) is loaded with the address from the
PC.
3. CPU sends a request to main memory.
4. The instruction is fetched from memory and placed in the Memory Buffer
Register (MBR) (or MDR).
5. It is then moved to the Instruction Register (IR).
6. PC is incremented to point to the next instruction.
2. Instruction Decode (ID)
• Goal: Understand what the fetched instruction means.
• Steps:
1. The Opcode (operation code) is extracted from the instruction in IR.
2. The Control Unit (CU) decodes the opcode to determine:
▪ The type of operation (e.g., ADD, LOAD, JUMP).
▪ The number of operands.
▪ Whether operands are in registers, memory, or immediate
values.
3. Operand Fetch (OF) / Address Calculation
• Goal: Get the data needed to execute the instruction.
• Steps:
1. If operands are in registers → CU reads directly from register file.
2. If operands are in memory → Effective Address is calculated using
addressing mode (e.g., direct, indirect, indexed).
3. MAR is loaded with the operand’s address, memory is accessed, and
value is brought into MDR.
4. Operand is made available for ALU.
4. Instruction Execution (EX)
• Goal: Perform the required operation.
• Steps:
o ALU or CU performs the operation:
▪ Arithmetic (ADD, SUB, MUL, DIV)
▪ Logical (AND, OR, NOT, XOR)
▪ Data transfer (LOAD, STORE, MOVE)
▪ Control transfer (JUMP, CALL, RETURN)
o Intermediate results may be stored in registers.
5. Result Write-back (WB)
• Goal: Store the result of execution.
• Steps:
o If result is to be stored in a register → write result into destination register.
o If result is to be stored in memory → write result into memory location
using MAR and MDR.
6. Next Instruction (PC Update)
• Normally, PC already points to the next instruction (incremented earlier).
• If the instruction was a branch/jump, the PC is updated with a new address.
• Control returns to the Fetch stage, starting the next instruction cycle.
Instruction Cycle Summary (Diagram)
+-------------------+
| Fetch (PC → IR) |
+-------------------+
+-------------------+
| Decode (CU) |
+-------------------+
+-------------------+
| Operand Fetch |
+-------------------+
+-------------------+
| Execute (ALU) |
+-------------------+
+-------------------+
| Write Back (Reg/Mem)|
+-------------------+
+-------------------+
| PC Update / Next |
+-------------------+
Example
Instruction: ADD R1, R2, R3
(Meaning: R1 = R2 + R3)
1. Fetch → Get instruction into IR.
2. Decode → CU understands it’s an ADD instruction.
3. Operand Fetch → Read values from R2 and R3.
4. Execute → ALU performs addition.
5. Write-back → Store result into R1.
6. Next Instruction → PC updated.
Control Signals in Computer Architecture
1. Introduction
In computer architecture, control signals are electronic signals that coordinate
and manage the execution of instructions in the CPU.
They are generated by the control unit (CU) and are used to direct the flow of
data between the processor, memory, and input/output devices.
Control signals ensure that every part of the computer performs its role at the
right time.
2. Types of Control Signals
Control signals are broadly classified into two categories:
(A) Internal CPU Control Signals
These control the internal operations of the processor:
• Register Control Signals
o Load (LD): Load data into a register.
o Clear (CLR): Reset a register to 0.
o Increment (INC): Increase register value by 1.
• ALU Control Signals
o ADD, SUB, AND, OR, NOT, SHIFT etc.
o These tell the Arithmetic Logic Unit which operation to perform.
• Clock Signals
o Synchronize all operations inside the CPU.
(B) External Control Signals
These control communication between CPU, Memory, and I/O devices:
• Memory Control Signals
o Memory Read (MEMR): Read data from memory.
o Memory Write (MEMW): Write data to memory.
o Memory Enable (MEMEN): Activate memory for operation.
• I/O Control Signals
o I/O Read (IOR): Read data from input device.
o I/O Write (IOW): Write data to output device.
• Bus Control Signals
o Address Enable (ALE): Enable address bus to send memory location.
o Data Enable (DEN): Enable data bus for data transfer.
o Read/Write (R/W): Decide whether to read or write.
3. Control Signal Categories
Control signals can also be grouped based on their function:
1. Data Transfer Control Signals
o Move data between CPU, memory, and I/O.
o Example: MEMR, MEMW, IOR, IOW.
2. Execution Control Signals
o Manage ALU operations and instruction execution.
o Example: ADD, SUB, AND, etc.
3. Sequencing Control Signals
o Ensure proper instruction cycle stages (Fetch, Decode, Execute).
o Example: PC Increment, Instruction Register Load.
4. Role of Control Signals in Instruction Cycle
The Instruction Cycle has 4 main steps:
1. Fetch
o Signals: MEMR, PC Increment, Instruction Register Load.
2. Decode
o Control unit decodes instruction (no external signals, only internal).
3. Execute
o Signals depend on operation (e.g., ALU control, MEMR/MEMW, IOR/IOW).
4. Write Back
o Signals: Register Load to store result.
5. Hardwired vs Microprogrammed Control Signals
• Hardwired Control Unit
o Control signals are generated using fixed logic circuits.
o Faster but less flexible.
• Microprogrammed Control Unit
o Control signals are stored as microinstructions in control memory.
o More flexible but slower.
6. Examples of Control Signals in Processors
• 8085 Microprocessor
o Control Signals: RD, WR, ALE, IO/M, S1, S0.
• Modern CPUs
o Use advanced control signals for pipelining, branch prediction, and cache
control.
Hardwired Control in Computer Architecture
1. What is Hardwired Control?
• Hardwired control is a control unit implementation technique in which the
control signals are generated using combinational logic circuits (decoders, flip-
flops, gates, etc.).
• It is called hardwired because the logic for control is “wired” directly into the
hardware rather than stored as instructions (like in microprogrammed control).
• This method is fast but inflexible—any change in instruction set or control logic
requires redesigning the circuit.
2. Role of Control Unit
The Control Unit (CU) is responsible for:
1. Fetching instructions from memory.
2. Decoding them.
3. Generating the correct sequence of control signals to drive the datapath (ALU,
registers, memory, I/O).
In hardwired control, this sequencing is done through direct logic design.
3. Basic Working
• Instruction → Goes to Instruction Decoder.
• Decoder identifies Opcode.
• Based on the opcode, the control logic activates signals for datapath units (like
ALU, MUX, registers, memory).
• A sequence counter (SC) is used to generate the proper timing steps (T0, T1,
T2…).
Example: Execution Steps
Let’s take a simple instruction:
ADD R1, R2 → R3
Steps:
• T0: Load instruction from memory into Instruction Register (IR).
• T1: Decode opcode and fetch operands.
• T2: Send contents of R1 and R2 to ALU.
• T3: Perform addition, store result in R3.
Each step is controlled by gates + decoders → generating the control signals.
4. Block Diagram of Hardwired Control
The main components are:
1. Instruction Register (IR) – holds the instruction.
2. Instruction Decoder – decodes opcode into control signals.
3. Control Logic Gates – generates required control lines.
4. Timing Signals / Sequence Counter – ensures correct order of operations.
5. Control Signals – sent to datapath (ALU, registers, memory).
┌───────────────┐
│ Instruction │
│ Register │
└───────┬───────┘
┌───────▼────────┐
│ Instruction │
│ Decoder │
└───────┬────────┘
┌─────────▼─────────┐
│ Control Logic (AND │
│ OR, Flip-Flops, │
│ Sequence Counter) │
└─────────┬─────────┘
┌───────▼────────┐
│ Control │
│ Signals │
└───────────────┘
5. Characteristics
Advantages
• Very fast execution (no microinstruction fetching).
• Simple for RISC (Reduced Instruction Set) processors.
Disadvantages
• Very complex for large instruction sets (like CISC).
• Inflexible → hard to modify (changes require rewiring).
• Difficult to support modern pipelining and parallelism.
6. Comparison: Hardwired vs Microprogrammed Control
Feature Hardwired Control Microprogrammed Control
Speed Faster Slower
Low (needs hardware High (modify microcode
Flexibility
changes) easily)
Complexity High for large ISAs Easier for complex ISAs
Lower (fewer memory Higher (requires control
Cost
needs) memory)
Used in RISC, simple CPUs CISC, complex CPUs
7. Applications
• Used in RISC processors (where the instruction set is small and simple).
• Suitable for high-performance processors where speed is critical.
• Example: Early Intel and ARM architectures used hardwired control for efficiency.
CISC – Style Processors in Computer Architecture
1. Introduction
• CISC stands for Complex Instruction Set Computer.
• It is a type of processor architecture where a single instruction can execute
several low-level operations (like memory access, arithmetic, or addressing
modes).
• The main idea: fewer lines of assembly code, even if each instruction is more
complex.
Example:
A CISC processor might have an instruction like:
MUL R1, R2, R3
Which multiplies the values in R2 and R3 and stores the result in R1 in a single
instruction.
2. Characteristics of CISC Processors
1. Large Instruction Set
o Typically 100–250 instructions.
o Some very specialized instructions.
2. Complex Instructions
o A single instruction can perform multiple operations.
o Example: "Copy from memory, add, and store back to memory".
3. Multiple Addressing Modes
o Provides flexibility in accessing operands (immediate, direct, indirect,
indexed, etc.).
4. Instruction Length is Variable
o Instructions can be 1 to 15 bytes long (not fixed).
5. Memory-Oriented Architecture
o Many instructions directly access memory (load/store not always
required separately).
6. Microprogramming Control Unit
o Instructions often decoded using microcode (firmware inside CPU).
7. Performance Goal
o Reduce the number of instructions per program, even if individual
instructions take more cycles.
3. Advantages of CISC
• Reduced program size (fewer instructions needed).
• Easier to write assembly language programs (since instructions are closer to
high-level languages).
• Backward compatibility (older software still runs on new versions).
• Good for systems where memory is expensive.
4. Disadvantages of CISC
• Complex hardware design (more transistors needed for decoding).
• Instructions take multiple cycles to execute (slower than simpler instructions).
• Inefficient pipelining (due to variable instruction length).
• May include rarely used instructions, wasting silicon area.
5. Examples of CISC Processors
• Intel x86 family (8086, 80286, Pentium, Core i7, etc.)
• VAX (Digital Equipment Corporation)
• Motorola 68000 series
6. CISC vs RISC (Quick Comparison)
Feature CISC RISC
Instruction Set Large, complex Small, simple
Instruction
Variable (1–15 bytes) Fixed (mostly 4 bytes)
Size
Execution
Multiple cycles Mostly single cycle
Time
Complex, microcode- Simple, hardwired
Hardware
based control
Memory Higher (more
Lower (compact code)
Usage instructions)
Example Intel x86, VAX ARM, MIPS, SPARC
7. Use Cases
• CISC processors are widely used in desktop, laptops, servers (Intel x86, AMD).
• Suitable for systems where program memory is limited, but execution speed is
less critical.