List of Experiments mapped with COs
SLno. ListofExperiments
1. Implementing HALF ADDER, FULL ADDER using basic logic gates
2. Implementing Binary-to-Gray, Gray-to-Binary code conversions.
3. Implementing 3–8-line DECODER.
4. Implementing 4x1 and 8x1 MULTIPLEXERS.
5. Verify the excitation tables of various FLIP-FLOPS.
6. Design of an 8-bit Input/Output system with four8-bit Internal Registers.
7. Design of an 8-bit ARITHMETIC LOGIC UNIT.
8. Design the data path of a computer from its register transfer language
description.
9. Design the control unit of a computer using either hardwiring or micro
programming based on its register transfer language description.
LAB EXPERIMENT1
OBJECTIVE:Design and implementation of Half Adder and Full Adder.
EQUIPMENTS & COMPONENTS REQUIRED:
[Link]. Equipment’s Specification Quantity
1 Digital IC Trainer kit - 1
2 Digital Multimeter 1
[Link]. Components Specification Quantity
7400,7402,7404,
1each
1 Digital ICs 7408,7432,7486.
- 6
2 Patch cords
BRIEF DESCRIPTION:
To design and implement half adder using logic gates
HALFADDER
OUTPUTS
INPUTA INPUTB
S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Circuit Diagram Truth Table
To design and implement full adder using logic gates.
FULLADDER
CIRCUITDIAGRAM TRUTHTABLE
PRE-EXPERIMENT QUESTIONS: -
1. Explain the truth table of half adder.
2. How many Ex-rounder or gate can be used to make a half adder?
PROCEDURE: -
Identify the pins.
Connect the circuit as per circuit diagram.
Obtain outputs with various input combinations.
Verify it with the Boolean function using truth table
ComputerOrganizationandArchitectureLab(BCS-352)
LAB EXPERIMENT- 2
OBJECTIVE: Design and implementation of Binary to Gray, Gray to Binary Code conversions
EQUIPMENTS & COMPONENTS REQUIRED:
SL.
Equipments Specification Quantity
No.
1 Digital IC Trainerkit - 1
2 Digital Multimeter 1
SL.
Components Specification Quantity
No.
7400,7402,
7404,
7408,7432, 1each
1 Digital ICs
7486.
- 6
2 Patch cords
BRIEFDESCRIPTION:
a) To design and implement Binary to Gray Code conversions
Pin diagram of Binary to gray code converter using 7486 IC EX-OR Gate
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INPUTS OUTPUTS
A B C D G4 G3 G2 G1
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0
Circuit Diagram of Binary to Gray Code Converter 1 1 1 0 1 0 0
Truth Table
b) To design and implement Binary to Gray Code conversions
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Pin diagram of Gray to Binary code converter using 7486 IC (EX-OR Gate)
INPUTS OUTPUTS
A B C D B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
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Circuit Diagram for Gray to Binary Code Converter
PRE-EXPERIMENT QUESTIONS: -
1 What is a code converter.
2 Differentiate between translator and code converter.
PROCEDURE: -
Collect the components necessary to accomplish this experiment.
Plug the IC chip into the breadboard.
Connectthesupplyvoltageandgroundlinestothechips.PIN7=GroundandPIN14 =
+5V.
Make connections as shown in there spective circuit diagram.
Connect the inputs of the gate to the input’s witches of the LED.
Connect the output of the gate to the output LEDs.
Once all connections have been done, turn on the powers witch of the bread board
Operate the switches and fill in the truth table(Write"1"if LED is O Nand "0"ifL1 is
OFF Apply the various combination of inputs according to the truth table and observe
the condition of Output LEDs.
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LAB EXPERIMENT- 3
OBJECTIVE: Design and implementation of 2-4 and 3-8linedecoder.
EQUIPMENTS & COMPONENTS REQUIRED:
Sl. No. Equipment Specification Quantity
1 Digital IC Trainer kit - 1
2 Digital Multi meter 1
S Components Specification Quantity
7400,7402,
7404,
1 Digital ICs 1 each
7408,7432,
7486.
2 Patch cords - 6
BRIEFDESCRIPTION:
a) 2 to 4 Decoder using logic gates:
b) 3 to 8 decoder using logic gates:
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SYMBOL TRUTHTABLE
LOGIC DIAGRAM OF 3TO 8 DECODER:
PROCEDURE:
Collect the components necessary to accomplish this experiment.
Plug the IC chip into the breadboard.
Connect the supply voltage and ground lines to the chips. PIN7=Ground
andPIN14=+5V.
Make connections as shown in the respective circuit diagram.
Connect the inputs of the gate to the input’s witches of the LED.
Connect the output of the gate to the output LEDs.
Once all connections have been done, turn on the power switch of the bread board
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Operate the switches and fill in the truth table (Write"1"ifLEDisONand"0"ifL1 is
OFF Apply the various combination of inputs according to the truth tab a lend
observe the condition of Output LEDs.
ComputerOrganizationandArchitectureLab(BCS-352)
LAB EXPERIMENT- 4
OBJECTIVE: Implementation of 4x1 and 8x1 Multiplexer
EQUIPMENTS & COMPONENTS REQUIRED:
SL. No. Equipment’s Specification Quantity
1 Digital IC Trainer kit - 1
2 Digital Multimeter 1
SL. No. Components Specification Quantity
7400,7402,
7404,
1 Digital ICs 1each
7408,7432,
7486.
2 Patch cords - 6
BRIEF DESCRIPTION:
a)4 to 1 MULTIPLEXERS:
Addressing Input
b a Selecte
d
0 0 A
0 1 B
1 0 C
1 1 D
LOGIC DIAGRAM: TRUTH TABLE:
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d) 8x1 Multiplexer
PINDIAGRAMOF8:1MUXUSINGTWO4:1MUX
CIRCUIT OF 8:1 MUX USING DUAL 4:1 MUX
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Select Lines Inputs Output
Ea S0 S1 Io I1 I2 I3 I4 I5 I6 I7 Za Zb Y
0 0 0 0 × × × × × × × 0 × 0
0 0 0 1 × × × × × × × 1 × 1
0 0 1 × 0 × × × × × × 0 × 0
0 0 1 × 1 × × × × × × 1 × 1
0 1 0 × × 0 × × × × × 0 × 0
0 1 0 × × 1 × × × × × 1 × 1
0 1 1 × × × 0 × × × × 0 × 0
0 1 1 × × × 1 × × × × 1 × 1
1 0 0 × × × 0 × × × × 0 0
1 0 0 × × × × 1 × × × × 1 1
1 0 1 × × × × × 0 × × × 0 0
1 0 1 × × × × × 1 × × × 1 1
1 1 0 × × × × × × 0 × × 0 0
1 1 0 × × × × × × 1 × × 1 1
1 1 1 × × × × × × × 0 × 0 0
1 1 1 × × × × × × × 1 × 1 1
TRUTH TABLE OF 8:1 MUX USING DUAL 4:1 MUX PRE
PROCEDURE: -
Collect the components necessary to accomplish this experiment.
Plug the IC chip into the bread board.
Connect the supply voltage and ground lines to the chips. PIN7=Ground
and PIN14 = +5V.
Make connections as shown in the respective circuit diagram.
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Connect the inputs of the gate to the input switches of the LED.
Connect the output of the gate to the output LEDs.
Once all connections have been done, turn on the power switch of the breadboard
Operate the switches and fill in the truth table (Write"1"ifLEDisONand"0"ifL1 is
OFF Apply the various combination of inputs according to the truth table and
observe the condition of Output LEDs.
Computer Organization and Architecture Lab (BCS-352)
LABEXPERIMENT5
OBJECTIVE: Verify the excitation tables of various FLIP-FLOPS.
EQUIPMENTS & COMPONENTS REQUIRED:
Digital IC trainer kit, IC7400, IC7410, IC7473, IC7474, IC 7476
BRIEFDESCRIPTION:
Flip flops are the basic building blocks in any memory systems since its output will
remain in its state until it is forced to change it by some means.
SRFLIP FLOP:
Sand R stands for set and reset. There are four input combination possible at the inputs.
But = =1 is forbidden since the output will be indeterminate.
LOGIC DIAGRAM OF R S FLIP FLOPS: TRUTH TABLE:
J K FLIP FLOP
The indeterminate output state of SRFF when S=R=1is avoided by converting it to a J K F F.
When flip flop is switched on its output state is uncertain. When an initial state is to be
assigned two separate inputs called preset and clear are used. They are active low inputs
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LOGIC DIAGRAM OF R-S FLIP FLOPS TRUTHTABLE
D-Flipflop
It has only one input called as D input or Data input. The input data is transferred to the
output after a clock is applied. DFF can be derived from JKFF by using J input as D input
and J is inverted and fed to K input.
LOGIC DIAGRAM TRUTH TABLE
T Flip Flop
T stands for Toggle. The output to gales when a clock pulse is applied. T Flip Flop can be
derived from JK FF by shorting J and K input.
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T FLIP FLOP LOGIC DIAGRAM TRUTH TABLE
PROCEDURE: -
Test all components and IC packages using digital IC tester and multimeter
Set up FF using Gates and verify their truth tables
Verify the Truth tables of 7473,7474, and7476ICs
Computer Organization and Architecture Lab (BCS-352)
LAB EXPERIMENT- 6
OBJECTIVE: Design And Implementation of Shift Registers (SISO&SIPO)
EQUIPMENTS & COMPONENTS REQUIRED:
SL. No. Equipment Specification Quantity
1 Digital IC Trainer kit - 1
2 Digital Multimeter - 1
SL. No. COMPONENT SPECIFICATION QTY.
1. D FLIP FLOP IC7474 2
2. IC TRAINER KIT - 1
3. PATCH CORDS - 15
BRIEFDESCRIPTION:
A register can shift its binary information in one or both directions is known as shift
register. The logical configuration of shift register consists of a D-Flip flop cascaded with
output of one flip flop connected to input of next flip flop. All flip flops receive common
clock pulses which causes the shift in the output of the flip flop. The simplest possible
shift register is one that uses only flip flop. The output of a given flip flop is connected to
the input of next flip flop of the register. Each clock pulse shifts the content of register
one bit position to right.
(a) Serial in serial out Shift Register
(b) Serial in parallel out Shift Register
PINDIAGRAM
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LOGIC DIAGRAM: SERIAL IN SERIAL OUT
Serialin Serialout
CLK
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1
TRUTH TABLE
SERIAL IN PARALLEL OUT
OUTPUT
CLK DATA QA QB QC Q
D
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
LOGIC DIAGRAM TRUTH TABLE
Computer Organization and Architecture Lab (BCS-352)
PRE-EXPERIMENT QUESTIONS: -
1. State the features of IC 7495.
2. State the features of IC 74195.
PROCEDURE: -
Connections are given as per circuit diagram.
Logic all inputs are given as per circuit diagram.
Observe the output and verify the truth table.
Computer Organization and Architecture Lab (BCS-352)
LAB EXPERIMENT- 7
OBJECTIVE: Design and implementation of an 8-bit arithmetic logic unit.
EQUIPMENTS & COMPONENTS REQUIRED:
SL. No. Equipment Specification Quantity
1 Digital IC Trainer kit - 1
2 Digital Multimeter 1
SL. No. COMPONENT SPECIFICATION QTY.
1. ALU IC IC7474 2
2. PATCH CORDS - 15
BRIEFDESCRIPTION:
ALU stands for the arithmetic and logic all unit and is one of the important units in
almost all the calculating machine these days be it with the hand-held mobile, or
computers. All the computational work in the system are carried out by this unit. The
typical ALU sizes are: 4-bit ALU: ALU that processes two 4-bit numbers.
8-bitALU: ALU that processes two 8-bitnumbers.
StillinthelatestsystemsALUsizesare16,32,64-bitetc. Figure-1showstheblockdiagram of a
typical ALU.
BlockDiagramofALU:
In figure-1, the 1x2 selector on the left is as a mode selector to select one of the two unit
either the arithmetic unit or the logical unit. The function select lines are then used to select
one of the many functions of arithmetic or the logical type.
MSI package for ALU: -IC 74181 a 4-bit Arithmetic and logic unit:
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PIN DIAGRAM OF IC74181 ALU
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PROCEDURE: -
Keep the data sheet of IC74181 ready.
Insert the IC on the Breadboard.
Make connections as shown in figure.
Verify the connections
Computer Organization and Architecture Lab (BCS-352)
LABEXPERIMENT- 8
OBJECTIVE: Design a data path of a computer from its register transfer language
description.
EQUIPMENTS&COMPONENTSREQUIRED:
SL. No. Equipment’s Specification Quantity
1 Digital IC Trainer kit - 1
2 Digital Multimeter 1
SL. No. Components Specification Quantity
7400,7402,7404,
1each
1 Digital ICs 7408,7432,7486.
- 6
2 Patch cords
BRIEFDESCRIPTION:
The symbolic notation used to describe the micro-operation transfers among registers is called
Register Transfer Language. The term “register transfer” implies the availability of hardware
logic circuits that can perform a stated micro-operation and transfer the result of the
operation to the same or another register.
Astatementthatspecifiesaregistertransferimpliesthatcircuitsareavailablefromtheoutputs of the
source register to the inputs of the destination register and that the destination register has a
parallel load capacity. If the transfer is to occur under a predetermined condition i.e.
If(P=1) thenR2←R1
Where P is the control signal generated in the control section. A Control Function is a Boolean
variable that is equal to 0 or 1
P: R2←R1
P
ControlUnit R2
clock
load r
n=noofbitsoftheregiste
R1
BLOCKDIAGRAM
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PROCEDURE: -
Data bits Ready to be transferred
In the first clock tick Register R1 stores the value
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In the next clock pulse the value gets transferred to register R2 if its Enable input is high, i.e. its
control function x.(y+z) =1
Register Transfer using BUS
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Computer Organization and Architecture Lab (BCS-352)
LABEXPERIMENT- 9
OBJECTIVE: Design a data path of a computer from its register transfer language description.
EQUIPMENTS&COMPONENTSREQUIRED:
Registers
AND Gates
OR Gate
Connecting Wires
BREIFDESCRIPTION:
Thesymbolicnotationusedtodescribethemicro-operationtransfersamongregistersis called
Register Transfer Language.
The term “register transfer” implies the availability of hardware logic circuits that can per form
astatedmicro-operationandtransfertheresultoftheoperationtothesameoranotherregister.
Astatementthatspecifiesaregistertransferimpliesthatcircuitsareavailablefromtheoutputs of the
source register to the inputs of the destination register and that the destination register has a
parallel load capacity.
If the transfer is to occur under a predetermined condition i.e.
If(P=1) thenR2←R1
Where P is the control signal generated in the control section. A Control Function is a Boolean
variable that is equal to 0 or 1
P: R2←R1
P
ControlUnit R2
clock
load
n=noofbitsoftheregister
R1
BLOCK DIAGRAM
PROCEDURE: -
Data bits Ready to be transferred
Computer Organization and Architecture Lab (BCS-352)
In the first clock tick Register R1 stores the value
In the next clock pulse the value gets transferred to register R2 if its Enable input is high,i.e. its
control function x.(y+z) =1
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REGISTER TRANSFER USING BUS
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